From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: edgar.iglesias@gmail.com
Subject: [PATCH 68/77] target/microblaze: Convert dec_bcc to decodetree
Date: Tue, 25 Aug 2020 13:59:41 -0700 [thread overview]
Message-ID: <20200825205950.730499-69-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/insns.decode | 36 +++++++++++++
target/microblaze/translate.c | 99 ++++++++++++++++++----------------
2 files changed, 88 insertions(+), 47 deletions(-)
diff --git a/target/microblaze/insns.decode b/target/microblaze/insns.decode
index 94520e92dd..21d08289f7 100644
--- a/target/microblaze/insns.decode
+++ b/target/microblaze/insns.decode
@@ -20,8 +20,10 @@
&typea0 rd ra
&typea rd ra rb
&typea_br rd rb
+&typea_bc ra rb
&typeb rd ra imm
&typeb_br rd imm
+&typeb_bc ra imm
# Include any IMM prefix in the value reported.
%extimm 0:s16 !function=typeb_imm
@@ -35,12 +37,18 @@
# Officially typea, but with ra as opcode.
@typea_br ...... rd:5 ..... rb:5 ........... &typea_br
+# Officially typea, but with rd as opcode.
+@typea_bc ...... ..... ra:5 rb:5 ........... &typea_bc
+
# Officially typeb, but any immediate extension is unused.
@typeb_bs ...... rd:5 ra:5 ..... ...... imm:5 &typeb
# Officially typeb, but with ra as opcode.
@typeb_br ...... rd:5 ..... ................ &typeb_br imm=%extimm
+# Officially typeb, but with rd as opcode.
+@typeb_bc ...... ..... ra:5 ................ &typeb_bc imm=%extimm
+
# For convenience, extract the two imm_w/imm_s fields, then pack
# them back together as "imm". Doing this makes it easiest to
# match the required zero at bit 5.
@@ -65,6 +73,34 @@ andi 101001 ..... ..... ................ @typeb
andn 100011 ..... ..... ..... 000 0000 0000 @typea
andni 101011 ..... ..... ................ @typeb
+beq 100111 00000 ..... ..... 000 0000 0000 @typea_bc
+bge 100111 00101 ..... ..... 000 0000 0000 @typea_bc
+bgt 100111 00100 ..... ..... 000 0000 0000 @typea_bc
+ble 100111 00011 ..... ..... 000 0000 0000 @typea_bc
+blt 100111 00010 ..... ..... 000 0000 0000 @typea_bc
+bne 100111 00001 ..... ..... 000 0000 0000 @typea_bc
+
+beqd 100111 10000 ..... ..... 000 0000 0000 @typea_bc
+bged 100111 10101 ..... ..... 000 0000 0000 @typea_bc
+bgtd 100111 10100 ..... ..... 000 0000 0000 @typea_bc
+bled 100111 10011 ..... ..... 000 0000 0000 @typea_bc
+bltd 100111 10010 ..... ..... 000 0000 0000 @typea_bc
+bned 100111 10001 ..... ..... 000 0000 0000 @typea_bc
+
+beqi 101111 00000 ..... ................ @typeb_bc
+bgei 101111 00101 ..... ................ @typeb_bc
+bgti 101111 00100 ..... ................ @typeb_bc
+blei 101111 00011 ..... ................ @typeb_bc
+blti 101111 00010 ..... ................ @typeb_bc
+bnei 101111 00001 ..... ................ @typeb_bc
+
+beqid 101111 10000 ..... ................ @typeb_bc
+bgeid 101111 10101 ..... ................ @typeb_bc
+bgtid 101111 10100 ..... ................ @typeb_bc
+bleid 101111 10011 ..... ................ @typeb_bc
+bltid 101111 10010 ..... ................ @typeb_bc
+bneid 101111 10001 ..... ................ @typeb_bc
+
br 100110 ..... 00000 ..... 000 0000 0000 @typea_br
bra 100110 ..... 01000 ..... 000 0000 0000 @typea_br
brd 100110 ..... 10000 ..... 000 0000 0000 @typea_br
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 73c956cd76..f79b02e987 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1139,6 +1139,58 @@ DO_BR(brad, braid, true, true, false)
DO_BR(brld, brlid, true, false, true)
DO_BR(brald, bralid, true, true, true)
+static bool do_bcc(DisasContext *dc, int dest_rb, int dest_imm,
+ TCGCond cond, int ra, bool delay)
+{
+ TCGv_i32 zero, next;
+
+ if (delay && setup_dslot(dc)) {
+ return true;
+ }
+
+ dc->jmp_cond = cond;
+
+ /* Cache the condition register in cpu_bvalue across any delay slot. */
+ tcg_gen_mov_i32(cpu_bvalue, reg_for_read(dc, ra));
+
+ /* Store the branch taken destination into btarget. */
+ if (dest_rb) {
+ dc->jmp_dest = -1;
+ tcg_gen_addi_i32(cpu_btarget, cpu_R[dest_rb], dc->base.pc_next);
+ } else {
+ dc->jmp_dest = dc->base.pc_next + dest_imm;
+ tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest);
+ }
+
+ /* Compute the final destination into btarget. */
+ zero = tcg_const_i32(0);
+ next = tcg_const_i32(dc->base.pc_next + (delay + 1) * 4);
+ tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget,
+ reg_for_read(dc, ra), zero,
+ cpu_btarget, next);
+ tcg_temp_free_i32(zero);
+ tcg_temp_free_i32(next);
+
+ return true;
+}
+
+#define DO_BCC(NAME, COND) \
+ static bool trans_##NAME(DisasContext *dc, arg_typea_bc *arg) \
+ { return do_bcc(dc, arg->rb, 0, COND, arg->ra, false); } \
+ static bool trans_##NAME##d(DisasContext *dc, arg_typea_bc *arg) \
+ { return do_bcc(dc, arg->rb, 0, COND, arg->ra, true); } \
+ static bool trans_##NAME##i(DisasContext *dc, arg_typeb_bc *arg) \
+ { return do_bcc(dc, 0, arg->imm, COND, arg->ra, false); } \
+ static bool trans_##NAME##id(DisasContext *dc, arg_typeb_bc *arg) \
+ { return do_bcc(dc, 0, arg->imm, COND, arg->ra, true); }
+
+DO_BCC(beq, TCG_COND_EQ)
+DO_BCC(bge, TCG_COND_GE)
+DO_BCC(bgt, TCG_COND_GT)
+DO_BCC(ble, TCG_COND_LE)
+DO_BCC(blt, TCG_COND_LT)
+DO_BCC(bne, TCG_COND_NE)
+
static bool trans_brk(DisasContext *dc, arg_typea_br *arg)
{
if (trap_userspace(dc, true)) {
@@ -1445,52 +1497,6 @@ static void dec_msr(DisasContext *dc)
}
}
-static void dec_bcc(DisasContext *dc)
-{
- static const TCGCond mb_to_tcg_cc[] = {
- [CC_EQ] = TCG_COND_EQ,
- [CC_NE] = TCG_COND_NE,
- [CC_LT] = TCG_COND_LT,
- [CC_LE] = TCG_COND_LE,
- [CC_GE] = TCG_COND_GE,
- [CC_GT] = TCG_COND_GT,
- };
- unsigned int cc;
- unsigned int dslot;
- TCGv_i32 zero, next;
-
- cc = EXTRACT_FIELD(dc->ir, 21, 23);
- dslot = dc->ir & (1 << 25);
-
- if (dslot && setup_dslot(dc)) {
- return;
- }
-
- dc->jmp_cond = mb_to_tcg_cc[cc];
-
- /* Cache the condition register in cpu_bvalue across any delay slot. */
- tcg_gen_mov_i32(cpu_bvalue, cpu_R[dc->ra]);
-
- /* Store the branch taken destination into btarget. */
- if (dc->type_b) {
- dc->jmp_dest = dc->base.pc_next + dec_alu_typeb_imm(dc);
- tcg_gen_movi_i32(cpu_btarget, dc->jmp_dest);
- } else {
- dc->jmp_dest = -1;
- tcg_gen_addi_i32(cpu_btarget, reg_for_read(dc, dc->rb),
- dc->base.pc_next);
- }
-
- /* Compute the final destination into btarget. */
- zero = tcg_const_i32(0);
- next = tcg_const_i32(dc->base.pc_next + (dslot + 1) * 4);
- tcg_gen_movcond_i32(dc->jmp_cond, cpu_btarget,
- reg_for_read(dc, dc->ra), zero,
- cpu_btarget, next);
- tcg_temp_free_i32(zero);
- tcg_temp_free_i32(next);
-}
-
static inline void do_rti(DisasContext *dc)
{
TCGv_i32 t0, t1;
@@ -1623,7 +1629,6 @@ static struct decoder_info {
};
void (*dec)(DisasContext *dc);
} decinfo[] = {
- {DEC_BCC, dec_bcc},
{DEC_RTS, dec_rts},
{DEC_MSR, dec_msr},
{DEC_STREAM, dec_stream},
--
2.25.1
next prev parent reply other threads:[~2020-08-25 21:29 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-25 20:58 [PATCH 00/77] target/microblaze improvements Richard Henderson
2020-08-25 20:58 ` [PATCH 01/77] tests/tcg: Add microblaze to arches filter Richard Henderson
2020-08-26 16:20 ` Edgar E. Iglesias
2020-08-25 20:58 ` [PATCH 02/77] tests/tcg: Do not require FE_TOWARDZERO Richard Henderson
2020-08-26 16:20 ` Edgar E. Iglesias
2020-08-25 20:58 ` [PATCH 03/77] tests/tcg: Do not require FE_* exception bits Richard Henderson
2020-08-26 16:21 ` Edgar E. Iglesias
2020-08-25 20:58 ` [PATCH 04/77] target/microblaze: Tidy gdbstub Richard Henderson
2020-08-25 20:58 ` [PATCH 05/77] target/microblaze: Split out PC from env->sregs Richard Henderson
2020-08-25 20:58 ` [PATCH 06/77] target/microblaze: Split out MSR " Richard Henderson
2020-08-25 20:58 ` [PATCH 07/77] target/microblaze: Split out EAR " Richard Henderson
2020-08-25 20:58 ` [PATCH 08/77] target/microblaze: Split out ESR " Richard Henderson
2020-08-25 20:58 ` [PATCH 09/77] target/microblaze: Split out FSR " Richard Henderson
2020-08-25 20:58 ` [PATCH 10/77] target/microblaze: Split out BTR " Richard Henderson
2020-08-25 20:58 ` [PATCH 11/77] target/microblaze: Split out EDR " Richard Henderson
2020-08-25 20:58 ` [PATCH 12/77] target/microblaze: Split the cpu_SR array Richard Henderson
2020-08-25 20:58 ` [PATCH 13/77] target/microblaze: Fix width of PC and BTARGET Richard Henderson
2020-08-25 20:58 ` [PATCH 14/77] target/microblaze: Fix width of MSR Richard Henderson
2020-08-25 20:58 ` [PATCH 15/77] target/microblaze: Fix width of ESR Richard Henderson
2020-08-25 20:58 ` [PATCH 16/77] target/microblaze: Fix width of FSR Richard Henderson
2020-08-25 20:58 ` [PATCH 17/77] target/microblaze: Fix width of BTR Richard Henderson
2020-08-25 20:58 ` [PATCH 18/77] target/microblaze: Fix width of EDR Richard Henderson
2020-08-25 20:58 ` [PATCH 19/77] target/microblaze: Remove cpu_ear Richard Henderson
2020-08-25 20:58 ` [PATCH 20/77] target/microblaze: Tidy raising of exceptions Richard Henderson
2020-08-25 20:58 ` [PATCH 21/77] target/microblaze: Mark raise_exception as noreturn Richard Henderson
2020-08-25 20:58 ` [PATCH 22/77] target/microblaze: Remove helper_debug and env->debug Richard Henderson
2020-08-25 20:58 ` [PATCH 23/77] target/microblaze: Rename env_* tcg variables to cpu_* Richard Henderson
2020-08-25 20:58 ` [PATCH 24/77] target/microblaze: Tidy mb_tcg_init Richard Henderson
2020-08-25 20:58 ` [PATCH 25/77] target/microblaze: Split out MSR[C] to its own variable Richard Henderson
2020-08-25 20:58 ` [PATCH 26/77] target/microblaze: Use DISAS_NORETURN Richard Henderson
2020-08-25 20:59 ` [PATCH 27/77] target/microblaze: Check singlestep_enabled in gen_goto_tb Richard Henderson
2020-08-25 20:59 ` [PATCH 28/77] target/microblaze: Convert to DisasContextBase Richard Henderson
2020-08-25 20:59 ` [PATCH 29/77] target/microblaze: Convert to translator_loop Richard Henderson
2020-08-25 20:59 ` [PATCH 30/77] target/microblaze: Remove SIM_COMPAT Richard Henderson
2020-08-25 20:59 ` [PATCH 31/77] target/microblaze: Remove DISAS_GNU Richard Henderson
2020-08-25 20:59 ` [PATCH 32/77] target/microblaze: Remove empty D macros Richard Henderson
2020-08-25 20:59 ` [PATCH 33/77] target/microblaze: Remove LOG_DIS Richard Henderson
2020-08-25 20:59 ` [PATCH 34/77] target/microblaze: Ensure imm constant is always available Richard Henderson
2020-08-25 20:59 ` [PATCH 35/77] target/microblaze: Add decodetree infrastructure Richard Henderson
2020-08-25 20:59 ` [PATCH 36/77] target/microblaze: Convert dec_add to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 37/77] target/microblaze: Convert dec_sub " Richard Henderson
2020-08-25 20:59 ` [PATCH 38/77] target/microblaze: Implement cmp and cmpu inline Richard Henderson
2020-08-25 20:59 ` [PATCH 39/77] target/microblaze: Convert dec_pattern to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 40/77] target/microblaze: Convert dec_and, dec_or, dec_xor " Richard Henderson
2020-08-25 20:59 ` [PATCH 41/77] target/microblaze: Convert dec_mul " Richard Henderson
2020-08-25 20:59 ` [PATCH 42/77] target/microblaze: Convert dec_div " Richard Henderson
2020-08-25 20:59 ` [PATCH 43/77] target/microblaze: Unwind properly when raising divide-by-zero Richard Henderson
2020-08-25 20:59 ` [PATCH 44/77] target/microblaze: Convert dec_bit to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 45/77] target/microblaze: Convert dec_barrel " Richard Henderson
2020-08-25 20:59 ` [PATCH 46/77] target/microblaze: Convert dec_imm " Richard Henderson
2020-08-25 20:59 ` [PATCH 47/77] target/microblaze: Convert dec_fpu " Richard Henderson
2020-08-25 20:59 ` [PATCH 48/77] target/microblaze: Fix cpu unwind for fpu exceptions Richard Henderson
2020-08-25 20:59 ` [PATCH 49/77] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG Richard Henderson
2020-08-25 20:59 ` [PATCH 50/77] target/microblaze: Replace MSR_EE_FLAG with MSR_EE Richard Henderson
2020-08-25 20:59 ` [PATCH 51/77] target/microblaze: Cache mem_index in DisasContext Richard Henderson
2020-08-25 20:59 ` [PATCH 52/77] target/microblaze: Fix cpu unwind for stackprot Richard Henderson
2020-08-25 20:59 ` [PATCH 53/77] target/microblaze: Convert dec_load and dec_store to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 54/77] target/microblaze: Assert no overlap in flags making up tb_flags Richard Henderson
2020-08-25 20:59 ` [PATCH 55/77] target/microblaze: Move bimm to BIMM_FLAG Richard Henderson
2020-08-25 20:59 ` [PATCH 56/77] target/microblaze: Store "current" iflags in insn_start Richard Henderson
2020-08-25 20:59 ` [PATCH 57/77] tcg: Add tcg_get_insn_start_param Richard Henderson
2020-08-25 20:59 ` [PATCH 58/77] target/microblaze: Use cc->do_unaligned_access Richard Henderson
2020-08-25 20:59 ` [PATCH 59/77] target/microblaze: Replace clear_imm with tb_flags_to_set Richard Henderson
2020-08-25 20:59 ` [PATCH 60/77] target/microblaze: Replace delayed_branch " Richard Henderson
2020-08-25 20:59 ` [PATCH 61/77] target/microblaze: Tidy mb_cpu_dump_state Richard Henderson
2020-08-25 20:59 ` [PATCH 62/77] target/microblaze: Try to keep imm and delay slot together Richard Henderson
2020-08-27 19:17 ` Edgar E. Iglesias
2020-08-27 21:33 ` Richard Henderson
2020-08-29 15:27 ` Richard Henderson
2020-08-25 20:59 ` [PATCH 63/77] target/microblaze: Convert brk and brki to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 64/77] target/microblaze: Convert mbar " Richard Henderson
2020-08-27 9:24 ` Edgar E. Iglesias
2020-08-27 9:58 ` Richard Henderson
2020-08-27 10:08 ` Edgar E. Iglesias
2020-08-27 11:11 ` Richard Henderson
2020-08-25 20:59 ` [PATCH 65/77] target/microblaze: Reorganize branching Richard Henderson
2020-08-25 20:59 ` [PATCH 66/77] target/microblaze: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
2020-08-28 6:33 ` Edgar E. Iglesias
2020-08-28 13:32 ` Richard Henderson
2020-08-25 20:59 ` [PATCH 67/77] target/microblaze: Convert dec_br to decodetree Richard Henderson
2020-08-25 20:59 ` Richard Henderson [this message]
2020-08-25 20:59 ` [PATCH 69/77] target/microblaze: Convert dec_rts " Richard Henderson
2020-08-25 20:59 ` [PATCH 70/77] target/microblaze: Tidy do_rti, do_rtb, do_rte Richard Henderson
2020-08-25 20:59 ` [PATCH 71/77] target/microblaze: Convert msrclr, msrset to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 72/77] target/microblaze: Convert dec_msr " Richard Henderson
2020-08-25 20:59 ` [PATCH 73/77] target/microblaze: Convert dec_stream " Richard Henderson
2020-08-27 21:10 ` Edgar E. Iglesias
2020-08-27 21:12 ` Richard Henderson
2020-08-25 20:59 ` [PATCH 74/77] target/microblaze: Remove last of old decoder Richard Henderson
2020-08-25 20:59 ` [PATCH 75/77] target/microblaze: Remove cpu_R[0] Richard Henderson
2020-08-25 20:59 ` [PATCH 76/77] target/microblaze: Add flags markup to some helpers Richard Henderson
2020-08-25 20:59 ` [PATCH 77/77] target/microblaze: Reduce linux-user address space to 32-bit Richard Henderson
2020-08-26 15:27 ` [PATCH 00/77] target/microblaze improvements Edgar E. Iglesias
2020-08-26 18:07 ` Edgar E. Iglesias
2020-08-27 9:11 ` Edgar E. Iglesias
2020-08-27 10:01 ` Richard Henderson
2020-08-27 10:22 ` Edgar E. Iglesias
2020-08-27 11:19 ` Richard Henderson
2020-08-27 17:09 ` Edgar E. Iglesias
2020-08-28 13:36 ` Richard Henderson
2020-08-28 14:04 ` Edgar E. Iglesias
2020-08-28 13:19 ` Edgar E. Iglesias
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