From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/35] target/arm: Pass the entire mte descriptor to mte_check_fail
Date: Fri, 28 Aug 2020 10:23:45 +0100 [thread overview]
Message-ID: <20200828092413.22206-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200828092413.22206-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
We need more information than just the mmu_idx in order
to create the proper exception syndrome. Only change the
function signature so far.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200813200816.3037186-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/mte_helper.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 104752041f7..a40454588d2 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -514,9 +514,10 @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val)
}
/* Record a tag check failure. */
-static void mte_check_fail(CPUARMState *env, int mmu_idx,
+static void mte_check_fail(CPUARMState *env, uint32_t desc,
uint64_t dirty_ptr, uintptr_t ra)
{
+ int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx);
int el, reg_el, tcf, select;
uint64_t sctlr;
@@ -639,8 +640,7 @@ uint64_t mte_check1(CPUARMState *env, uint32_t desc,
}
if (unlikely(!mte_probe1_int(env, desc, ptr, ra, bit55))) {
- int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX);
- mte_check_fail(env, mmu_idx, ptr, ra);
+ mte_check_fail(env, desc, ptr, ra);
}
return useronly_clean_ptr(ptr);
@@ -810,7 +810,7 @@ uint64_t mte_checkN(CPUARMState *env, uint32_t desc,
fail_ofs = tag_first + n * TAG_GRANULE - ptr;
fail_ofs = ROUND_UP(fail_ofs, esize);
- mte_check_fail(env, mmu_idx, ptr + fail_ofs, ra);
+ mte_check_fail(env, desc, ptr + fail_ofs, ra);
}
done:
@@ -922,7 +922,7 @@ uint64_t HELPER(mte_check_zva)(CPUARMState *env, uint32_t desc, uint64_t ptr)
fail:
/* Locate the first nibble that differs. */
i = ctz64(mem_tag ^ ptr_tag) >> 4;
- mte_check_fail(env, mmu_idx, align_ptr + i * TAG_GRANULE, ra);
+ mte_check_fail(env, desc, align_ptr + i * TAG_GRANULE, ra);
done:
return useronly_clean_ptr(ptr);
--
2.20.1
next prev parent reply other threads:[~2020-08-28 9:28 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-28 9:23 [PULL 00/35] target-arm queue Peter Maydell
2020-08-28 9:23 ` [PULL 01/35] hw/arm/sbsa-ref: fix typo breaking PCIe IRQs Peter Maydell
2020-08-28 9:23 ` [PULL 02/35] hw/clock: Remove unused clock_init*() functions Peter Maydell
2020-08-28 9:23 ` [PULL 03/35] hw/clock: Let clock_set() return boolean value Peter Maydell
2020-08-28 9:23 ` [PULL 04/35] hw/clock: Only propagate clock changes if the clock is changed Peter Maydell
2020-08-28 9:23 ` [PULL 05/35] hw/arm/musicpal: Use AddressSpace for DMA transfers Peter Maydell
2020-08-28 9:23 ` [PULL 06/35] target/arm: Clarify HCR_EL2 ARMCPRegInfo type Peter Maydell
2020-08-28 9:23 ` Peter Maydell [this message]
2020-08-28 9:23 ` [PULL 08/35] target/arm: Fill in the WnR syndrome bit in mte_check_fail Peter Maydell
2020-08-28 9:23 ` [PULL 09/35] hw/sd/allwinner-sdhost: Use AddressSpace for DMA transfers Peter Maydell
2020-08-28 9:23 ` [PULL 10/35] hw/net/allwinner-sun8i-emac: " Peter Maydell
2020-08-28 9:23 ` [PULL 11/35] hw/arm/xilinx_zynq: Uninline cadence_uart_create() Peter Maydell
2020-08-28 9:23 ` [PULL 12/35] hw/arm/xilinx_zynq: Call qdev_connect_clock_in() before DeviceRealize Peter Maydell
2020-08-28 9:23 ` [PULL 13/35] hw/qdev-clock: Uninline qdev_connect_clock_in() Peter Maydell
2020-08-28 9:23 ` [PULL 14/35] hw/qdev-clock: Avoid calling qdev_connect_clock_in after DeviceRealize Peter Maydell
2020-08-28 9:23 ` [PULL 15/35] hw/misc/unimp: Display value after offset Peter Maydell
2020-08-28 9:23 ` [PULL 16/35] hw/misc/unimp: Display the value with width of the access size Peter Maydell
2020-08-28 9:23 ` [PULL 17/35] hw/misc/unimp: Display the offset with width of the region size Peter Maydell
2020-08-28 9:23 ` [PULL 18/35] armsse: Define ARMSSEClass correctly Peter Maydell
2020-08-28 9:23 ` [PULL 19/35] qemu/int128: Add int128_lshift Peter Maydell
2020-08-28 9:23 ` [PULL 20/35] target/arm: Split out gen_gvec_fn_zz Peter Maydell
2020-08-28 9:23 ` [PULL 21/35] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn Peter Maydell
2020-08-28 9:24 ` [PULL 22/35] target/arm: Rearrange {sve,fp}_check_access assert Peter Maydell
2020-08-28 9:24 ` [PULL 23/35] target/arm: Merge do_vector2_p into do_mov_p Peter Maydell
2020-08-28 9:24 ` [PULL 24/35] target/arm: Clean up 4-operand predicate expansion Peter Maydell
2020-08-28 9:24 ` [PULL 25/35] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp Peter Maydell
2020-08-28 9:24 ` [PULL 26/35] target/arm: Split out gen_gvec_ool_zzzp Peter Maydell
2020-08-28 9:24 ` [PULL 27/35] target/arm: Merge helper_sve_clr_* and helper_sve_movz_* Peter Maydell
2020-08-28 9:24 ` [PULL 28/35] target/arm: Split out gen_gvec_ool_zzp Peter Maydell
2020-08-28 9:24 ` [PULL 29/35] target/arm: Split out gen_gvec_ool_zzz Peter Maydell
2020-08-28 9:24 ` [PULL 30/35] target/arm: Split out gen_gvec_ool_zz Peter Maydell
2020-08-28 9:24 ` [PULL 31/35] target/arm: Tidy SVE tszimm shift formats Peter Maydell
2020-08-28 9:24 ` [PULL 32/35] target/arm: Generalize inl_qrdmlah_* helper functions Peter Maydell
2020-08-28 9:24 ` [PULL 33/35] target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd Peter Maydell
2020-08-28 9:24 ` [PULL 34/35] target/arm: Convert integer multiply-add " Peter Maydell
2020-08-28 9:24 ` [PULL 35/35] target/arm: Convert sq{, r}dmulh " Peter Maydell
2020-08-28 17:37 ` [PULL 00/35] target-arm queue Peter Maydell
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