From: Leif Lindholm <leif@nuviainc.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Alistair Francis" <alistair@alistair23.me>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
"Bin Meng" <bin.meng@windriver.com>,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Jason Wang" <jasowang@redhat.com>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
qemu-arm <qemu-arm@nongnu.org>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>
Subject: Re: [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support
Date: Mon, 31 Aug 2020 00:35:52 +0100 [thread overview]
Message-ID: <20200830233552.GG20124@vanye> (raw)
In-Reply-To: <CAEUhbmVYpSVE+C+KyEa2Ono5p-SLtC1vE=YwE_3FJK6POEJCCg@mail.gmail.com>
On Mon, Aug 31, 2020 at 06:15:52 +0800, Bin Meng wrote:
> Hi Leif,
>
> > > The following perepherals are emulated:
> > > - SiFive CLINT
> > > - SiFive PLIC
> > > - PolarFire SoC Multi-Mode UART
> > > - SiFive PDMA
> > > - Cadence eMMC/SDHCI controller
> > > - Cadence Gigabit Ethernet MAC
> > >
> > > The BIOS image used by this machine is hss.bin, aka Hart Software
> > > Services, which can be built from:
> > > https://github.com/polarfire-soc/hart-software-services
> >
> > Are there any version requirements, or additional qemu patches, that
> > need to be taken into account. Should I expect to see output on stdio?
>
> Thanks for trying!
>
> Did you apply the patch to skip the DDR memory initialization
> mentioned in this page?
> https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit
I did, but in honesty only after I sent the previous email :)
(Since it made no difference, I didn't bother following up.)
> > I tried to build hss 3faaaaf8ce0d, using
> > https://github.com/riscv/riscv-gnu-toolchain (7f1f4ab5b0e0), which
> > ends up being a gcc 10.1. That caused me to raise
> > https://github.com/polarfire-soc/hart-software-services/issues/2.
>
> Yes, GCC 10 does not build is a known issue. Currently I am using GCC
> 9 to build HSS.
Right, I can confirm that with commit 93f82dc18e1d riscv-gnu-toolchain
(the last before changing to gcc 10.1), I generate a 9.2.0 gcc that
builds a hss.bin that boots successfully with the minimal command line
qemu-system-riscv64 -M microchip-icicle-kit -smp 5 -bios hss.bin \
-display none -serial stdio
Thanks!
(I haven't looked any further than the hss.bin yet, but I'm now
unblocked to do so.)
Best Regards,
Leif
prev parent reply other threads:[~2020-08-30 23:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-29 15:17 [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-08-29 15:17 ` [PATCH v2 01/16] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-08-29 15:17 ` [PATCH v2 02/16] hw/riscv: hart: " Bin Meng
2020-08-29 15:17 ` [PATCH v2 03/16] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-08-29 15:17 ` [PATCH v2 04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-08-29 15:17 ` [PATCH v2 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-08-29 15:17 ` [PATCH v2 06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Bin Meng
2020-08-29 15:17 ` [PATCH v2 07/16] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-08-29 15:17 ` [PATCH v2 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-08-29 15:17 ` [PATCH v2 09/16] hw/dma: Add SiFive platform DMA controller emulation Bin Meng
2020-08-29 15:17 ` [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-08-29 15:17 ` [PATCH v2 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property Bin Meng
2020-08-29 15:17 ` [PATCH v2 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Bin Meng
2020-08-29 15:17 ` [PATCH v2 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-08-29 15:17 ` [PATCH v2 14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-08-29 15:17 ` [PATCH v2 15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-08-29 15:17 ` [PATCH v2 16/16] hw/riscv: sifive_u: Connect a DMA controller Bin Meng
2020-08-30 12:56 ` [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Leif Lindholm
2020-08-30 22:15 ` Bin Meng
2020-08-30 23:35 ` Leif Lindholm [this message]
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