From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
peter.maydell@linaro.org
Subject: [PULL 12/76] target/microblaze: Split the cpu_SR array
Date: Mon, 31 Aug 2020 09:04:57 -0700 [thread overview]
Message-ID: <20200831160601.833692-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org>
Similar to splitting the sregs array, this will allow further
fixes and cleanups.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/translate.c | 106 +++++++++++++++++++++-------------
1 file changed, 65 insertions(+), 41 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 7d307e6b48..19d7b8abfd 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -55,7 +55,13 @@
static TCGv_i32 env_debug;
static TCGv_i32 cpu_R[32];
-static TCGv_i64 cpu_SR[14];
+static TCGv_i64 cpu_pc;
+static TCGv_i64 cpu_msr;
+static TCGv_i64 cpu_ear;
+static TCGv_i64 cpu_esr;
+static TCGv_i64 cpu_fsr;
+static TCGv_i64 cpu_btr;
+static TCGv_i64 cpu_edr;
static TCGv_i32 env_imm;
static TCGv_i32 env_btaken;
static TCGv_i64 env_btarget;
@@ -117,7 +123,7 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
TCGv_i32 tmp = tcg_const_i32(index);
t_sync_flags(dc);
- tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
+ tcg_gen_movi_i64(cpu_pc, dc->pc);
gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
dc->is_jmp = DISAS_UPDATE;
@@ -136,17 +142,17 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
{
if (use_goto_tb(dc, dest)) {
tcg_gen_goto_tb(n);
- tcg_gen_movi_i64(cpu_SR[SR_PC], dest);
+ tcg_gen_movi_i64(cpu_pc, dest);
tcg_gen_exit_tb(dc->tb, n);
} else {
- tcg_gen_movi_i64(cpu_SR[SR_PC], dest);
+ tcg_gen_movi_i64(cpu_pc, dest);
tcg_gen_exit_tb(NULL, 0);
}
}
static void read_carry(DisasContext *dc, TCGv_i32 d)
{
- tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]);
+ tcg_gen_extrl_i64_i32(d, cpu_msr);
tcg_gen_shri_i32(d, d, 31);
}
@@ -159,8 +165,8 @@ static void write_carry(DisasContext *dc, TCGv_i32 v)
TCGv_i64 t0 = tcg_temp_new_i64();
tcg_gen_extu_i32_i64(t0, v);
/* Deposit bit 0 into MSR_C and the alias MSR_CC. */
- tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1);
- tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1);
+ tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 2, 1);
+ tcg_gen_deposit_i64(cpu_msr, cpu_msr, t0, 31, 1);
tcg_temp_free_i64(t0);
}
@@ -180,7 +186,7 @@ static bool trap_illegal(DisasContext *dc, bool cond)
{
if (cond && (dc->tb_flags & MSR_EE_FLAG)
&& dc->cpu->cfg.illegal_opcode_exception) {
- tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
+ tcg_gen_movi_i64(cpu_esr, ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
return cond;
@@ -196,7 +202,7 @@ static bool trap_userspace(DisasContext *dc, bool cond)
bool cond_user = cond && mem_index == MMU_USER_IDX;
if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) {
- tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_PRIVINSN);
+ tcg_gen_movi_i64(cpu_esr, ESR_EC_PRIVINSN);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
return cond_user;
@@ -431,7 +437,7 @@ static void dec_xor(DisasContext *dc)
static inline void msr_read(DisasContext *dc, TCGv_i32 d)
{
- tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]);
+ tcg_gen_extrl_i64_i32(d, cpu_msr);
}
static inline void msr_write(DisasContext *dc, TCGv_i32 v)
@@ -443,8 +449,8 @@ static inline void msr_write(DisasContext *dc, TCGv_i32 v)
/* PVR bit is not writable. */
tcg_gen_extu_i32_i64(t, v);
tcg_gen_andi_i64(t, t, ~MSR_PVR);
- tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR);
- tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t);
+ tcg_gen_andi_i64(cpu_msr, cpu_msr, MSR_PVR);
+ tcg_gen_or_i64(cpu_msr, cpu_msr, t);
tcg_temp_free_i64(t);
}
@@ -503,7 +509,7 @@ static void dec_msr(DisasContext *dc)
msr_write(dc, t0);
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
- tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4);
+ tcg_gen_movi_i64(cpu_pc, dc->pc + 4);
dc->is_jmp = DISAS_UPDATE;
return;
}
@@ -535,15 +541,25 @@ static void dec_msr(DisasContext *dc)
if (to) {
LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
switch (sr) {
- case 0:
+ case SR_PC:
break;
- case 1:
+ case SR_MSR:
msr_write(dc, cpu_R[dc->ra]);
break;
case SR_EAR:
+ tcg_gen_extu_i32_i64(cpu_ear, cpu_R[dc->ra]);
+ break;
case SR_ESR:
+ tcg_gen_extu_i32_i64(cpu_esr, cpu_R[dc->ra]);
+ break;
case SR_FSR:
- tcg_gen_extu_i32_i64(cpu_SR[sr], cpu_R[dc->ra]);
+ tcg_gen_extu_i32_i64(cpu_fsr, cpu_R[dc->ra]);
+ break;
+ case SR_BTR:
+ tcg_gen_extu_i32_i64(cpu_btr, cpu_R[dc->ra]);
+ break;
+ case SR_EDR:
+ tcg_gen_extu_i32_i64(cpu_edr, cpu_R[dc->ra]);
break;
case 0x800:
tcg_gen_st_i32(cpu_R[dc->ra],
@@ -561,22 +577,30 @@ static void dec_msr(DisasContext *dc)
LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
switch (sr) {
- case 0:
+ case SR_PC:
tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc);
break;
- case 1:
+ case SR_MSR:
msr_read(dc, cpu_R[dc->rd]);
break;
case SR_EAR:
if (extended) {
- tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_SR[sr]);
- break;
+ tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_ear);
+ } else {
+ tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_ear);
}
+ break;
case SR_ESR:
+ tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_esr);
+ break;
case SR_FSR:
+ tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_fsr);
+ break;
case SR_BTR:
+ tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_btr);
+ break;
case SR_EDR:
- tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]);
+ tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_edr);
break;
case 0x800:
tcg_gen_ld_i32(cpu_R[dc->rd],
@@ -749,7 +773,7 @@ static void dec_bit(DisasContext *dc)
t0 = tcg_temp_new_i32();
LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
- tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]);
+ tcg_gen_extrl_i64_i32(t0, cpu_msr);
tcg_gen_andi_i32(t0, t0, MSR_CC);
write_carry(dc, cpu_R[dc->ra]);
if (dc->rd) {
@@ -995,7 +1019,7 @@ static void dec_load(DisasContext *dc)
TCGv_i32 treg = tcg_const_i32(dc->rd);
TCGv_i32 tsize = tcg_const_i32(size - 1);
- tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
+ tcg_gen_movi_i64(cpu_pc, dc->pc);
gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
tcg_temp_free_i32(t0);
@@ -1115,7 +1139,7 @@ static void dec_store(DisasContext *dc)
TCGv_i32 treg = tcg_const_i32(dc->rd);
TCGv_i32 tsize = tcg_const_i32(size - 1);
- tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
+ tcg_gen_movi_i64(cpu_pc, dc->pc);
/* FIXME: if the alignment is wrong, we should restore the value
* in memory. One possible way to achieve this is to probe
* the MMU prior to the memaccess, thay way we could put
@@ -1169,7 +1193,7 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64 pc_false)
TCGv_i64 tmp_zero = tcg_const_i64(0);
tcg_gen_extu_i32_i64(tmp_btaken, env_btaken);
- tcg_gen_movcond_i64(TCG_COND_NE, cpu_SR[SR_PC],
+ tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc,
tmp_btaken, tmp_zero,
pc_true, pc_false);
@@ -1253,7 +1277,7 @@ static void dec_br(DisasContext *dc)
tcg_gen_st_i32(tmp_1, cpu_env,
-offsetof(MicroBlazeCPU, env)
+offsetof(CPUState, halted));
- tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4);
+ tcg_gen_movi_i64(cpu_pc, dc->pc + 4);
gen_helper_raise_exception(cpu_env, tmp_hlt);
tcg_temp_free_i32(tmp_hlt);
tcg_temp_free_i32(tmp_1);
@@ -1309,7 +1333,7 @@ static inline void do_rti(DisasContext *dc)
TCGv_i32 t0, t1;
t0 = tcg_temp_new_i32();
t1 = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]);
+ tcg_gen_extrl_i64_i32(t1, cpu_msr);
tcg_gen_shri_i32(t0, t1, 1);
tcg_gen_ori_i32(t1, t1, MSR_IE);
tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM));
@@ -1327,7 +1351,7 @@ static inline void do_rtb(DisasContext *dc)
TCGv_i32 t0, t1;
t0 = tcg_temp_new_i32();
t1 = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]);
+ tcg_gen_extrl_i64_i32(t1, cpu_msr);
tcg_gen_andi_i32(t1, t1, ~MSR_BIP);
tcg_gen_shri_i32(t0, t1, 1);
tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM));
@@ -1346,7 +1370,7 @@ static inline void do_rte(DisasContext *dc)
t0 = tcg_temp_new_i32();
t1 = tcg_temp_new_i32();
- tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]);
+ tcg_gen_extrl_i64_i32(t1, cpu_msr);
tcg_gen_ori_i32(t1, t1, MSR_EE);
tcg_gen_andi_i32(t1, t1, ~MSR_EIP);
tcg_gen_shri_i32(t0, t1, 1);
@@ -1401,7 +1425,7 @@ static void dec_rts(DisasContext *dc)
static int dec_check_fpuv2(DisasContext *dc)
{
if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
- tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_FPU);
+ tcg_gen_movi_i64(cpu_esr, ESR_EC_FPU);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0;
@@ -1652,7 +1676,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
#if SIM_COMPAT
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
- tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc);
+ tcg_gen_movi_i64(cpu_pc, dc->pc);
gen_helper_debug();
}
#endif
@@ -1730,7 +1754,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
if (dc->tb_flags & D_FLAG) {
dc->is_jmp = DISAS_UPDATE;
- tcg_gen_movi_i64(cpu_SR[SR_PC], npc);
+ tcg_gen_movi_i64(cpu_pc, npc);
sync_jmpstate(dc);
} else
npc = dc->jmp_pc;
@@ -1740,7 +1764,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
if (dc->is_jmp == DISAS_NEXT
&& (dc->cpustate_changed || org_flags != dc->tb_flags)) {
dc->is_jmp = DISAS_UPDATE;
- tcg_gen_movi_i64(cpu_SR[SR_PC], npc);
+ tcg_gen_movi_i64(cpu_pc, npc);
}
t_sync_flags(dc);
@@ -1748,7 +1772,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
if (dc->is_jmp != DISAS_JUMP) {
- tcg_gen_movi_i64(cpu_SR[SR_PC], npc);
+ tcg_gen_movi_i64(cpu_pc, npc);
}
gen_helper_raise_exception(cpu_env, tmp);
tcg_temp_free_i32(tmp);
@@ -1863,19 +1887,19 @@ void mb_tcg_init(void)
regnames[i]);
}
- cpu_SR[SR_PC] =
+ cpu_pc =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc");
- cpu_SR[SR_MSR] =
+ cpu_msr =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, msr), "rmsr");
- cpu_SR[SR_EAR] =
+ cpu_ear =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), "rear");
- cpu_SR[SR_ESR] =
+ cpu_esr =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr");
- cpu_SR[SR_FSR] =
+ cpu_fsr =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr");
- cpu_SR[SR_BTR] =
+ cpu_btr =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr");
- cpu_SR[SR_EDR] =
+ cpu_edr =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr");
}
--
2.25.1
next prev parent reply other threads:[~2020-08-31 16:07 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-31 16:04 [PULL 00/76] target/microblaze improvements Richard Henderson
2020-08-31 16:04 ` [PULL 01/76] tests/tcg: Add microblaze to arches filter Richard Henderson
2020-08-31 16:04 ` [PULL 02/76] tests/tcg: Do not require FE_TOWARDZERO Richard Henderson
2020-08-31 16:04 ` [PULL 03/76] tests/tcg: Do not require FE_* exception bits Richard Henderson
2020-08-31 16:04 ` [PULL 04/76] target/microblaze: Tidy gdbstub Richard Henderson
2020-08-31 16:04 ` [PULL 05/76] target/microblaze: Split out PC from env->sregs Richard Henderson
2020-08-31 16:04 ` [PULL 06/76] target/microblaze: Split out MSR " Richard Henderson
2020-08-31 16:04 ` [PULL 07/76] target/microblaze: Split out EAR " Richard Henderson
2020-08-31 16:04 ` [PULL 08/76] target/microblaze: Split out ESR " Richard Henderson
2020-08-31 16:04 ` [PULL 09/76] target/microblaze: Split out FSR " Richard Henderson
2020-08-31 16:04 ` [PULL 10/76] target/microblaze: Split out BTR " Richard Henderson
2020-08-31 16:04 ` [PULL 11/76] target/microblaze: Split out EDR " Richard Henderson
2020-08-31 16:04 ` Richard Henderson [this message]
2020-08-31 16:04 ` [PULL 13/76] target/microblaze: Fix width of PC and BTARGET Richard Henderson
2020-08-31 16:04 ` [PULL 14/76] target/microblaze: Fix width of MSR Richard Henderson
2020-08-31 16:05 ` [PULL 15/76] target/microblaze: Fix width of ESR Richard Henderson
2020-08-31 16:05 ` [PULL 16/76] target/microblaze: Fix width of FSR Richard Henderson
2020-08-31 16:05 ` [PULL 17/76] target/microblaze: Fix width of BTR Richard Henderson
2020-08-31 16:05 ` [PULL 18/76] target/microblaze: Fix width of EDR Richard Henderson
2020-08-31 16:05 ` [PULL 19/76] target/microblaze: Remove cpu_ear Richard Henderson
2020-08-31 16:05 ` [PULL 20/76] target/microblaze: Tidy raising of exceptions Richard Henderson
2020-08-31 16:05 ` [PULL 21/76] target/microblaze: Mark raise_exception as noreturn Richard Henderson
2020-08-31 16:05 ` [PULL 22/76] target/microblaze: Remove helper_debug and env->debug Richard Henderson
2020-08-31 16:05 ` [PULL 23/76] target/microblaze: Rename env_* tcg variables to cpu_* Richard Henderson
2020-08-31 16:05 ` [PULL 24/76] target/microblaze: Tidy mb_tcg_init Richard Henderson
2020-08-31 16:05 ` [PULL 25/76] target/microblaze: Split out MSR[C] to its own variable Richard Henderson
2020-08-31 16:05 ` [PULL 26/76] target/microblaze: Use DISAS_NORETURN Richard Henderson
2020-08-31 16:05 ` [PULL 27/76] target/microblaze: Check singlestep_enabled in gen_goto_tb Richard Henderson
2020-08-31 16:05 ` [PULL 28/76] target/microblaze: Convert to DisasContextBase Richard Henderson
2020-08-31 16:05 ` [PULL 29/76] target/microblaze: Convert to translator_loop Richard Henderson
2020-08-31 16:05 ` [PULL 30/76] target/microblaze: Remove SIM_COMPAT Richard Henderson
2020-08-31 16:05 ` [PULL 31/76] target/microblaze: Remove DISAS_GNU Richard Henderson
2020-08-31 16:05 ` [PULL 32/76] target/microblaze: Remove empty D macros Richard Henderson
2020-08-31 16:05 ` [PULL 33/76] target/microblaze: Remove LOG_DIS Richard Henderson
2020-08-31 16:05 ` [PULL 34/76] target/microblaze: Ensure imm constant is always available Richard Henderson
2020-08-31 16:05 ` [PULL 35/76] target/microblaze: Add decodetree infrastructure Richard Henderson
2020-08-31 16:05 ` [PULL 36/76] target/microblaze: Convert dec_add to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 37/76] target/microblaze: Convert dec_sub " Richard Henderson
2020-08-31 16:05 ` [PULL 38/76] target/microblaze: Implement cmp and cmpu inline Richard Henderson
2020-08-31 16:05 ` [PULL 39/76] target/microblaze: Convert dec_pattern to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 40/76] target/microblaze: Convert dec_and, dec_or, dec_xor " Richard Henderson
2020-08-31 16:05 ` [PULL 41/76] target/microblaze: Convert dec_mul " Richard Henderson
2020-08-31 16:05 ` [PULL 42/76] target/microblaze: Convert dec_div " Richard Henderson
2020-08-31 16:05 ` [PULL 43/76] target/microblaze: Unwind properly when raising divide-by-zero Richard Henderson
2020-08-31 16:05 ` [PULL 44/76] target/microblaze: Convert dec_bit to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 45/76] target/microblaze: Convert dec_barrel " Richard Henderson
2020-08-31 16:05 ` [PULL 46/76] target/microblaze: Convert dec_imm " Richard Henderson
2020-08-31 16:05 ` [PULL 47/76] target/microblaze: Convert dec_fpu " Richard Henderson
2020-08-31 16:05 ` [PULL 48/76] target/microblaze: Fix cpu unwind for fpu exceptions Richard Henderson
2020-08-31 16:05 ` [PULL 49/76] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG Richard Henderson
2020-08-31 16:05 ` [PULL 50/76] target/microblaze: Replace MSR_EE_FLAG with MSR_EE Richard Henderson
2020-08-31 16:05 ` [PULL 51/76] target/microblaze: Cache mem_index in DisasContext Richard Henderson
2020-08-31 16:05 ` [PULL 52/76] target/microblaze: Fix cpu unwind for stackprot Richard Henderson
2020-08-31 16:05 ` [PULL 53/76] target/microblaze: Convert dec_load and dec_store to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 54/76] target/microblaze: Assert no overlap in flags making up tb_flags Richard Henderson
2020-08-31 16:05 ` [PULL 55/76] target/microblaze: Move bimm to BIMM_FLAG Richard Henderson
2020-08-31 16:05 ` [PULL 56/76] target/microblaze: Fix no-op mb_cpu_transaction_failed Richard Henderson
2020-08-31 16:05 ` [PULL 57/76] target/microblaze: Store "current" iflags in insn_start Richard Henderson
2020-08-31 16:05 ` [PULL 58/76] tcg: Add tcg_get_insn_start_param Richard Henderson
2020-08-31 16:05 ` [PULL 59/76] target/microblaze: Use cc->do_unaligned_access Richard Henderson
2020-08-31 16:05 ` [PULL 60/76] target/microblaze: Replace clear_imm with tb_flags_to_set Richard Henderson
2020-08-31 16:05 ` [PULL 61/76] target/microblaze: Replace delayed_branch " Richard Henderson
2020-08-31 16:05 ` [PULL 62/76] target/microblaze: Tidy mb_cpu_dump_state Richard Henderson
2020-08-31 16:05 ` [PULL 63/76] target/microblaze: Convert brk and brki to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 64/76] target/microblaze: Convert mbar " Richard Henderson
2020-08-31 16:05 ` [PULL 65/76] target/microblaze: Reorganize branching Richard Henderson
2020-08-31 16:05 ` [PULL 66/76] target/microblaze: Convert dec_br to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 67/76] target/microblaze: Convert dec_bcc " Richard Henderson
2020-08-31 16:05 ` [PULL 68/76] target/microblaze: Convert dec_rts " Richard Henderson
2020-08-31 16:05 ` [PULL 69/76] target/microblaze: Tidy do_rti, do_rtb, do_rte Richard Henderson
2020-08-31 16:05 ` [PULL 70/76] target/microblaze: Convert msrclr, msrset to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 71/76] target/microblaze: Convert dec_msr " Richard Henderson
2020-08-31 16:05 ` [PULL 72/76] target/microblaze: Convert dec_stream " Richard Henderson
2020-08-31 16:05 ` [PULL 73/76] target/microblaze: Remove last of old decoder Richard Henderson
2020-08-31 16:05 ` [PULL 74/76] target/microblaze: Remove cpu_R[0] Richard Henderson
2020-08-31 16:06 ` [PULL 75/76] target/microblaze: Add flags markup to some helpers Richard Henderson
2020-08-31 16:06 ` [PULL 76/76] target/microblaze: Reduce linux-user address space to 32-bit Richard Henderson
2020-09-01 0:21 ` [PULL 00/76] target/microblaze improvements no-reply
2020-09-01 0:32 ` no-reply
2020-09-01 12:17 ` Peter Maydell
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