From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Edgar E . Iglesias" <edgar.iglesias@xilinx.com>,
peter.maydell@linaro.org
Subject: [PULL 23/76] target/microblaze: Rename env_* tcg variables to cpu_*
Date: Mon, 31 Aug 2020 09:05:08 -0700 [thread overview]
Message-ID: <20200831160601.833692-24-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200831160601.833692-1-richard.henderson@linaro.org>
This is cpu_imm, cpu_btaken, cpu_iflags, cpu_res_addr and cpu_res_val.
It is standard for these file-scope globals to begin with cpu_*.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/translate.c | 54 +++++++++++++++++------------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index ecfa6b86a4..9aa63ddcc5 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -56,12 +56,12 @@
static TCGv_i32 cpu_R[32];
static TCGv_i32 cpu_pc;
static TCGv_i32 cpu_msr;
-static TCGv_i32 env_imm;
-static TCGv_i32 env_btaken;
+static TCGv_i32 cpu_imm;
+static TCGv_i32 cpu_btaken;
static TCGv_i32 cpu_btarget;
-static TCGv_i32 env_iflags;
-static TCGv env_res_addr;
-static TCGv_i32 env_res_val;
+static TCGv_i32 cpu_iflags;
+static TCGv cpu_res_addr;
+static TCGv_i32 cpu_res_val;
#include "exec/gen-icount.h"
@@ -107,7 +107,7 @@ static inline void t_sync_flags(DisasContext *dc)
{
/* Synch the tb dependent flags between translator and runtime. */
if (dc->tb_flags != dc->synced_flags) {
- tcg_gen_movi_i32(env_iflags, dc->tb_flags);
+ tcg_gen_movi_i32(cpu_iflags, dc->tb_flags);
dc->synced_flags = dc->tb_flags;
}
}
@@ -222,10 +222,10 @@ static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc)
{
if (dc->type_b) {
if (dc->tb_flags & IMM_FLAG)
- tcg_gen_ori_i32(env_imm, env_imm, dc->imm);
+ tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm);
else
- tcg_gen_movi_i32(env_imm, (int32_t)((int16_t)dc->imm));
- return &env_imm;
+ tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm));
+ return &cpu_imm;
} else
return &cpu_R[dc->rb];
}
@@ -859,7 +859,7 @@ static inline void sync_jmpstate(DisasContext *dc)
{
if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
if (dc->jmp == JMP_DIRECT) {
- tcg_gen_movi_i32(env_btaken, 1);
+ tcg_gen_movi_i32(cpu_btaken, 1);
}
dc->jmp = JMP_INDIRECT;
tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc);
@@ -869,7 +869,7 @@ static inline void sync_jmpstate(DisasContext *dc)
static void dec_imm(DisasContext *dc)
{
LOG_DIS("imm %x\n", dc->imm << 16);
- tcg_gen_movi_i32(env_imm, (dc->imm << 16));
+ tcg_gen_movi_i32(cpu_imm, (dc->imm << 16));
dc->tb_flags |= IMM_FLAG;
dc->clear_imm = 0;
}
@@ -1040,8 +1040,8 @@ static void dec_load(DisasContext *dc)
}
if (ex) {
- tcg_gen_mov_tl(env_res_addr, addr);
- tcg_gen_mov_i32(env_res_val, v);
+ tcg_gen_mov_tl(cpu_res_addr, addr);
+ tcg_gen_mov_i32(cpu_res_val, v);
}
if (dc->rd) {
tcg_gen_mov_i32(cpu_R[dc->rd], v);
@@ -1103,7 +1103,7 @@ static void dec_store(DisasContext *dc)
write_carryi(dc, 1);
swx_skip = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, addr, swx_skip);
+ tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip);
/*
* Compare the value loaded at lwx with current contents of
@@ -1111,11 +1111,11 @@ static void dec_store(DisasContext *dc)
*/
tval = tcg_temp_new_i32();
- tcg_gen_atomic_cmpxchg_i32(tval, addr, env_res_val,
+ tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val,
cpu_R[dc->rd], mem_index,
mop);
- tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip);
+ tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip);
write_carryi(dc, 0);
tcg_temp_free_i32(tval);
}
@@ -1204,7 +1204,7 @@ static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false)
TCGv_i32 zero = tcg_const_i32(0);
tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc,
- env_btaken, zero,
+ cpu_btaken, zero,
pc_true, pc_false);
tcg_temp_free_i32(zero);
@@ -1245,7 +1245,7 @@ static void dec_bcc(DisasContext *dc)
dc->jmp = JMP_INDIRECT;
tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc);
}
- eval_cc(dc, cc, env_btaken, cpu_R[dc->ra]);
+ eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]);
}
static void dec_br(DisasContext *dc)
@@ -1311,7 +1311,7 @@ static void dec_br(DisasContext *dc)
dc->jmp = JMP_INDIRECT;
if (abs) {
- tcg_gen_movi_i32(env_btaken, 1);
+ tcg_gen_movi_i32(cpu_btaken, 1);
tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc)));
if (link && !dslot) {
if (!(dc->tb_flags & IMM_FLAG) &&
@@ -1330,7 +1330,7 @@ static void dec_br(DisasContext *dc)
dc->jmp = JMP_DIRECT;
dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
} else {
- tcg_gen_movi_i32(env_btaken, 1);
+ tcg_gen_movi_i32(cpu_btaken, 1);
tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc);
}
}
@@ -1419,7 +1419,7 @@ static void dec_rts(DisasContext *dc)
LOG_DIS("rts ir=%x\n", dc->ir);
dc->jmp = JMP_INDIRECT;
- tcg_gen_movi_i32(env_btaken, 1);
+ tcg_gen_movi_i32(cpu_btaken, 1);
tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc));
}
@@ -1722,7 +1722,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
TCGLabel *l1 = gen_new_label();
t_sync_flags(dc);
/* Conditional jmp. */
- tcg_gen_brcondi_i32(TCG_COND_NE, env_btaken, 0, l1);
+ tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1);
gen_goto_tb(dc, 1, dc->pc);
gen_set_label(l1);
gen_goto_tb(dc, 0, dc->jmp_pc);
@@ -1848,22 +1848,22 @@ void mb_tcg_init(void)
{
int i;
- env_iflags = tcg_global_mem_new_i32(cpu_env,
+ cpu_iflags = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMBState, iflags),
"iflags");
- env_imm = tcg_global_mem_new_i32(cpu_env,
+ cpu_imm = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMBState, imm),
"imm");
cpu_btarget = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMBState, btarget),
"btarget");
- env_btaken = tcg_global_mem_new_i32(cpu_env,
+ cpu_btaken = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMBState, btaken),
"btaken");
- env_res_addr = tcg_global_mem_new(cpu_env,
+ cpu_res_addr = tcg_global_mem_new(cpu_env,
offsetof(CPUMBState, res_addr),
"res_addr");
- env_res_val = tcg_global_mem_new_i32(cpu_env,
+ cpu_res_val = tcg_global_mem_new_i32(cpu_env,
offsetof(CPUMBState, res_val),
"res_val");
for (i = 0; i < ARRAY_SIZE(cpu_R); i++) {
--
2.25.1
next prev parent reply other threads:[~2020-08-31 16:16 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-31 16:04 [PULL 00/76] target/microblaze improvements Richard Henderson
2020-08-31 16:04 ` [PULL 01/76] tests/tcg: Add microblaze to arches filter Richard Henderson
2020-08-31 16:04 ` [PULL 02/76] tests/tcg: Do not require FE_TOWARDZERO Richard Henderson
2020-08-31 16:04 ` [PULL 03/76] tests/tcg: Do not require FE_* exception bits Richard Henderson
2020-08-31 16:04 ` [PULL 04/76] target/microblaze: Tidy gdbstub Richard Henderson
2020-08-31 16:04 ` [PULL 05/76] target/microblaze: Split out PC from env->sregs Richard Henderson
2020-08-31 16:04 ` [PULL 06/76] target/microblaze: Split out MSR " Richard Henderson
2020-08-31 16:04 ` [PULL 07/76] target/microblaze: Split out EAR " Richard Henderson
2020-08-31 16:04 ` [PULL 08/76] target/microblaze: Split out ESR " Richard Henderson
2020-08-31 16:04 ` [PULL 09/76] target/microblaze: Split out FSR " Richard Henderson
2020-08-31 16:04 ` [PULL 10/76] target/microblaze: Split out BTR " Richard Henderson
2020-08-31 16:04 ` [PULL 11/76] target/microblaze: Split out EDR " Richard Henderson
2020-08-31 16:04 ` [PULL 12/76] target/microblaze: Split the cpu_SR array Richard Henderson
2020-08-31 16:04 ` [PULL 13/76] target/microblaze: Fix width of PC and BTARGET Richard Henderson
2020-08-31 16:04 ` [PULL 14/76] target/microblaze: Fix width of MSR Richard Henderson
2020-08-31 16:05 ` [PULL 15/76] target/microblaze: Fix width of ESR Richard Henderson
2020-08-31 16:05 ` [PULL 16/76] target/microblaze: Fix width of FSR Richard Henderson
2020-08-31 16:05 ` [PULL 17/76] target/microblaze: Fix width of BTR Richard Henderson
2020-08-31 16:05 ` [PULL 18/76] target/microblaze: Fix width of EDR Richard Henderson
2020-08-31 16:05 ` [PULL 19/76] target/microblaze: Remove cpu_ear Richard Henderson
2020-08-31 16:05 ` [PULL 20/76] target/microblaze: Tidy raising of exceptions Richard Henderson
2020-08-31 16:05 ` [PULL 21/76] target/microblaze: Mark raise_exception as noreturn Richard Henderson
2020-08-31 16:05 ` [PULL 22/76] target/microblaze: Remove helper_debug and env->debug Richard Henderson
2020-08-31 16:05 ` Richard Henderson [this message]
2020-08-31 16:05 ` [PULL 24/76] target/microblaze: Tidy mb_tcg_init Richard Henderson
2020-08-31 16:05 ` [PULL 25/76] target/microblaze: Split out MSR[C] to its own variable Richard Henderson
2020-08-31 16:05 ` [PULL 26/76] target/microblaze: Use DISAS_NORETURN Richard Henderson
2020-08-31 16:05 ` [PULL 27/76] target/microblaze: Check singlestep_enabled in gen_goto_tb Richard Henderson
2020-08-31 16:05 ` [PULL 28/76] target/microblaze: Convert to DisasContextBase Richard Henderson
2020-08-31 16:05 ` [PULL 29/76] target/microblaze: Convert to translator_loop Richard Henderson
2020-08-31 16:05 ` [PULL 30/76] target/microblaze: Remove SIM_COMPAT Richard Henderson
2020-08-31 16:05 ` [PULL 31/76] target/microblaze: Remove DISAS_GNU Richard Henderson
2020-08-31 16:05 ` [PULL 32/76] target/microblaze: Remove empty D macros Richard Henderson
2020-08-31 16:05 ` [PULL 33/76] target/microblaze: Remove LOG_DIS Richard Henderson
2020-08-31 16:05 ` [PULL 34/76] target/microblaze: Ensure imm constant is always available Richard Henderson
2020-08-31 16:05 ` [PULL 35/76] target/microblaze: Add decodetree infrastructure Richard Henderson
2020-08-31 16:05 ` [PULL 36/76] target/microblaze: Convert dec_add to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 37/76] target/microblaze: Convert dec_sub " Richard Henderson
2020-08-31 16:05 ` [PULL 38/76] target/microblaze: Implement cmp and cmpu inline Richard Henderson
2020-08-31 16:05 ` [PULL 39/76] target/microblaze: Convert dec_pattern to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 40/76] target/microblaze: Convert dec_and, dec_or, dec_xor " Richard Henderson
2020-08-31 16:05 ` [PULL 41/76] target/microblaze: Convert dec_mul " Richard Henderson
2020-08-31 16:05 ` [PULL 42/76] target/microblaze: Convert dec_div " Richard Henderson
2020-08-31 16:05 ` [PULL 43/76] target/microblaze: Unwind properly when raising divide-by-zero Richard Henderson
2020-08-31 16:05 ` [PULL 44/76] target/microblaze: Convert dec_bit to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 45/76] target/microblaze: Convert dec_barrel " Richard Henderson
2020-08-31 16:05 ` [PULL 46/76] target/microblaze: Convert dec_imm " Richard Henderson
2020-08-31 16:05 ` [PULL 47/76] target/microblaze: Convert dec_fpu " Richard Henderson
2020-08-31 16:05 ` [PULL 48/76] target/microblaze: Fix cpu unwind for fpu exceptions Richard Henderson
2020-08-31 16:05 ` [PULL 49/76] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG Richard Henderson
2020-08-31 16:05 ` [PULL 50/76] target/microblaze: Replace MSR_EE_FLAG with MSR_EE Richard Henderson
2020-08-31 16:05 ` [PULL 51/76] target/microblaze: Cache mem_index in DisasContext Richard Henderson
2020-08-31 16:05 ` [PULL 52/76] target/microblaze: Fix cpu unwind for stackprot Richard Henderson
2020-08-31 16:05 ` [PULL 53/76] target/microblaze: Convert dec_load and dec_store to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 54/76] target/microblaze: Assert no overlap in flags making up tb_flags Richard Henderson
2020-08-31 16:05 ` [PULL 55/76] target/microblaze: Move bimm to BIMM_FLAG Richard Henderson
2020-08-31 16:05 ` [PULL 56/76] target/microblaze: Fix no-op mb_cpu_transaction_failed Richard Henderson
2020-08-31 16:05 ` [PULL 57/76] target/microblaze: Store "current" iflags in insn_start Richard Henderson
2020-08-31 16:05 ` [PULL 58/76] tcg: Add tcg_get_insn_start_param Richard Henderson
2020-08-31 16:05 ` [PULL 59/76] target/microblaze: Use cc->do_unaligned_access Richard Henderson
2020-08-31 16:05 ` [PULL 60/76] target/microblaze: Replace clear_imm with tb_flags_to_set Richard Henderson
2020-08-31 16:05 ` [PULL 61/76] target/microblaze: Replace delayed_branch " Richard Henderson
2020-08-31 16:05 ` [PULL 62/76] target/microblaze: Tidy mb_cpu_dump_state Richard Henderson
2020-08-31 16:05 ` [PULL 63/76] target/microblaze: Convert brk and brki to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 64/76] target/microblaze: Convert mbar " Richard Henderson
2020-08-31 16:05 ` [PULL 65/76] target/microblaze: Reorganize branching Richard Henderson
2020-08-31 16:05 ` [PULL 66/76] target/microblaze: Convert dec_br to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 67/76] target/microblaze: Convert dec_bcc " Richard Henderson
2020-08-31 16:05 ` [PULL 68/76] target/microblaze: Convert dec_rts " Richard Henderson
2020-08-31 16:05 ` [PULL 69/76] target/microblaze: Tidy do_rti, do_rtb, do_rte Richard Henderson
2020-08-31 16:05 ` [PULL 70/76] target/microblaze: Convert msrclr, msrset to decodetree Richard Henderson
2020-08-31 16:05 ` [PULL 71/76] target/microblaze: Convert dec_msr " Richard Henderson
2020-08-31 16:05 ` [PULL 72/76] target/microblaze: Convert dec_stream " Richard Henderson
2020-08-31 16:05 ` [PULL 73/76] target/microblaze: Remove last of old decoder Richard Henderson
2020-08-31 16:05 ` [PULL 74/76] target/microblaze: Remove cpu_R[0] Richard Henderson
2020-08-31 16:06 ` [PULL 75/76] target/microblaze: Add flags markup to some helpers Richard Henderson
2020-08-31 16:06 ` [PULL 76/76] target/microblaze: Reduce linux-user address space to 32-bit Richard Henderson
2020-09-01 0:21 ` [PULL 00/76] target/microblaze improvements no-reply
2020-09-01 0:32 ` no-reply
2020-09-01 12:17 ` Peter Maydell
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