From: "Michael S. Tsirkin" <mst@redhat.com>
To: Nathan Chancellor <natechancellor@gmail.com>
Cc: qemu-riscv@nongnu.org,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
qemu-devel@nongnu.org, qemu-stable@nongnu.org,
Alistair Francis <Alistair.Francis@wdc.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH] riscv: sifive_test: Allow 16-bit writes to memory region
Date: Tue, 1 Sep 2020 07:49:34 -0400 [thread overview]
Message-ID: <20200901074918-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20200901065406-mutt-send-email-mst@kernel.org>
On Tue, Sep 01, 2020 at 07:08:34AM -0400, Michael S. Tsirkin wrote:
> On Mon, Aug 31, 2020 at 10:58:23PM -0700, Nathan Chancellor wrote:
> > When shutting down the machine running a mainline Linux kernel, the
> > following error happens:
> >
> > $ build/riscv64-softmmu/qemu-system-riscv64 -bios default -M virt \
> > -display none -initrd rootfs.cpio -kernel Image -m 512m \
> > -nodefaults -serial mon:stdio
> > ...
> > Requesting system poweroff
> > [ 4.999630] reboot: Power down
> > sbi_trap_error: hart0: trap handler failed (error -2)
> > sbi_trap_error: hart0: mcause=0x0000000000000007 mtval=0x0000000000100000
> > sbi_trap_error: hart0: mepc=0x000000008000d4cc mstatus=0x0000000000001822
> > sbi_trap_error: hart0: ra=0x000000008000999e sp=0x0000000080015c78
> > sbi_trap_error: hart0: gp=0xffffffe000e76610 tp=0xffffffe0081b89c0
> > sbi_trap_error: hart0: s0=0x0000000080015c88 s1=0x0000000000000040
> > sbi_trap_error: hart0: a0=0x0000000000000000 a1=0x0000000080004024
> > sbi_trap_error: hart0: a2=0x0000000080004024 a3=0x0000000080004024
> > sbi_trap_error: hart0: a4=0x0000000000100000 a5=0x0000000000005555
> > sbi_trap_error: hart0: a6=0x0000000000004024 a7=0x0000000080011158
> > sbi_trap_error: hart0: s2=0x0000000000000000 s3=0x0000000080016000
> > sbi_trap_error: hart0: s4=0x0000000000000000 s5=0x0000000000000000
> > sbi_trap_error: hart0: s6=0x0000000000000001 s7=0x0000000000000000
> > sbi_trap_error: hart0: s8=0x0000000000000000 s9=0x0000000000000000
> > sbi_trap_error: hart0: s10=0x0000000000000000 s11=0x0000000000000008
> > sbi_trap_error: hart0: t0=0x0000000000000000 t1=0x0000000000000000
> > sbi_trap_error: hart0: t2=0x0000000000000000 t3=0x0000000000000000
> > sbi_trap_error: hart0: t4=0x0000000000000000 t5=0x0000000000000000
> > sbi_trap_error: hart0: t6=0x0000000000000000
> >
> > The kernel does a 16-bit write when powering off the machine, which
> > was allowed before commit 5d971f9e67 ("memory: Revert "memory: accept
> > mismatching sizes in memory_region_access_valid""). Make min_access_size
> > match reality so that the machine can shut down properly now.
> >
> > Cc: qemu-stable@nongnu.org
> > Fixes: 88a07990fa ("SiFive RISC-V Test Finisher")
> > Fixes: 5d971f9e67 ("memory: Revert "memory: accept mismatching sizes in memory_region_access_valid"")
> > Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
> > ---
> >
> > Please let me know if the tags are wrong or inappropriate, this is my
> > first QEMU patch.
> >
> > hw/riscv/sifive_test.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
> > index 0c78fb2c93..8c70dd69df 100644
> > --- a/hw/riscv/sifive_test.c
> > +++ b/hw/riscv/sifive_test.c
> > @@ -59,7 +59,7 @@ static const MemoryRegionOps sifive_test_ops = {
> > .write = sifive_test_write,
> > .endianness = DEVICE_NATIVE_ENDIAN,
>
>
> Apropos, why is this native endian?
> The write handler seems to ignore target endian-ness,
> looks like a bug ...
patch itself looks fine
Acked-by: Michael S. Tsirkin <mst@redhat.com>
> > .valid = {
> > - .min_access_size = 4,
> > + .min_access_size = 2,
> > .max_access_size = 4
> > }
> > };
> >
> > base-commit: 2f4c51c0f384d7888a04b4815861e6d5fd244d75
> > --
> > 2.28.0
next prev parent reply other threads:[~2020-09-01 11:50 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-01 5:58 [PATCH] riscv: sifive_test: Allow 16-bit writes to memory region Nathan Chancellor
2020-09-01 11:08 ` Michael S. Tsirkin
2020-09-01 11:49 ` Michael S. Tsirkin [this message]
2020-09-01 23:17 ` Alistair Francis
2020-09-01 23:59 ` Alistair Francis
2020-09-03 21:05 ` Michael Roth
2020-09-10 18:10 ` Alistair Francis
2020-09-11 12:26 ` Michael Roth
2020-09-14 16:07 ` Alistair Francis
2020-09-14 21:09 ` Michael Roth
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