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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id d17sm245811ljl.133.2020.09.01.05.30.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Sep 2020 05:30:32 -0700 (PDT) Date: Tue, 1 Sep 2020 14:30:30 +0200 From: "Edgar E. Iglesias" To: Sai Pavan Boddu Subject: Re: [PATCH] target/arm: Configure number of pmu counters Message-ID: <20200901123030.GV2954729@toto> References: <1598874522-5186-1-git-send-email-sai.pavan.boddu@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1598874522-5186-1-git-send-email-sai.pavan.boddu@xilinx.com> Received-SPF: pass client-ip=2a00:1450:4864:20::242; envelope-from=edgar.iglesias@gmail.com; helo=mail-lj1-x242.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_FAKE=2.346, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "'Edgar E . Iglesias'" , Peter Maydell , Andrew Jones , 'Philippe =?iso-8859-1?Q?Mathieu-Daud=E9'?= , Richard Henderson , qemu-devel@nongnu.org, Eric Auger , qemu-arm@nongnu.org, Paolo Bonzini , 'Alex =?iso-8859-1?Q?Benn=E9e'?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Aug 31, 2020 at 05:18:42PM +0530, Sai Pavan Boddu wrote: > Default the pmu counters to 4 and configure it a 6 for a53 cores. Your commit message looks like it needs a little rewording. I would probably split this into two patches, one that adds pmcrn and another that modifies the A53. > > Signed-off-by: Sai Pavan Boddu > --- > target/arm/cpu.c | 3 +++ > target/arm/cpu.h | 3 +++ > target/arm/cpu64.c | 1 + > target/arm/helper.c | 2 +- > 4 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 6b382fc..805a692 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1051,6 +1051,9 @@ static void arm_cpu_initfn(Object *obj) > cpu->psci_version = 1; /* By default assume PSCI v0.1 */ > cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE; > > + /* set number of pmu counters to 4 */ /* Set default number of PMU counters */ That way if the default changes you don't need to edit both code and comment. With those changes: Reviewed-by: Edgar E. Iglesias > + cpu->pmcrn = 4; > + > if (tcg_enabled()) { > cpu->psci_version = 2; /* TCG implements PSCI 0.2 */ > } > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index ac857bd..3b47ba8 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -879,6 +879,9 @@ struct ARMCPU { > */ > int32_t core_count; > > + /* Number of pmu counters */ > + uint8_t pmcrn; > + > /* The instance init functions for implementation-specific subclasses > * set these fields to specify the implementation-dependent values of > * various constant registers and reset values of non-constant > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index dd69618..76c879a 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -190,6 +190,7 @@ static void aarch64_a53_initfn(Object *obj) > cpu->gic_vpribits = 5; > cpu->gic_vprebits = 5; > define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); > + cpu->pmcrn = 6; > } > > static void aarch64_a72_initfn(Object *obj) > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 44d6666..4afbefb 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6534,7 +6534,7 @@ static void define_pmu_regs(ARMCPU *cpu) > * field as main ID register, and we implement four counters in > * addition to the cycle count register. > */ > - unsigned int i, pmcrn = 4; > + unsigned int i, pmcrn = cpu->pmcrn; > ARMCPRegInfo pmcr = { > .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0, > .access = PL0_RW, > -- > 2.7.4 > >