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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/47] target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp()
Date: Tue,  1 Sep 2020 16:17:43 +0100	[thread overview]
Message-ID: <20200901151823.29785-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200901151823.29785-1-peter.maydell@linaro.org>

Macroify the uses of do_vfp_2op_sp() and do_vfp_2op_dp(); this will
make it easier to add the halfprec support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-8-peter.maydell@linaro.org
---
 target/arm/translate-vfp.c.inc | 49 ++++++++++------------------------
 1 file changed, 14 insertions(+), 35 deletions(-)

diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index b5eb9d66b3d..f891d860bb9 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -2234,55 +2234,34 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
     return true;
 }
 
-static bool trans_VMOV_reg_sp(DisasContext *s, arg_VMOV_reg_sp *a)
-{
-    return do_vfp_2op_sp(s, tcg_gen_mov_i32, a->vd, a->vm);
-}
+#define DO_VFP_2OP(INSN, PREC, FN)                              \
+    static bool trans_##INSN##_##PREC(DisasContext *s,          \
+                                      arg_##INSN##_##PREC *a)   \
+    {                                                           \
+        return do_vfp_2op_##PREC(s, FN, a->vd, a->vm);          \
+    }
 
-static bool trans_VMOV_reg_dp(DisasContext *s, arg_VMOV_reg_dp *a)
-{
-    return do_vfp_2op_dp(s, tcg_gen_mov_i64, a->vd, a->vm);
-}
+DO_VFP_2OP(VMOV_reg, sp, tcg_gen_mov_i32)
+DO_VFP_2OP(VMOV_reg, dp, tcg_gen_mov_i64)
 
-static bool trans_VABS_sp(DisasContext *s, arg_VABS_sp *a)
-{
-    return do_vfp_2op_sp(s, gen_helper_vfp_abss, a->vd, a->vm);
-}
+DO_VFP_2OP(VABS, sp, gen_helper_vfp_abss)
+DO_VFP_2OP(VABS, dp, gen_helper_vfp_absd)
 
-static bool trans_VABS_dp(DisasContext *s, arg_VABS_dp *a)
-{
-    return do_vfp_2op_dp(s, gen_helper_vfp_absd, a->vd, a->vm);
-}
-
-static bool trans_VNEG_sp(DisasContext *s, arg_VNEG_sp *a)
-{
-    return do_vfp_2op_sp(s, gen_helper_vfp_negs, a->vd, a->vm);
-}
-
-static bool trans_VNEG_dp(DisasContext *s, arg_VNEG_dp *a)
-{
-    return do_vfp_2op_dp(s, gen_helper_vfp_negd, a->vd, a->vm);
-}
+DO_VFP_2OP(VNEG, sp, gen_helper_vfp_negs)
+DO_VFP_2OP(VNEG, dp, gen_helper_vfp_negd)
 
 static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
 {
     gen_helper_vfp_sqrts(vd, vm, cpu_env);
 }
 
-static bool trans_VSQRT_sp(DisasContext *s, arg_VSQRT_sp *a)
-{
-    return do_vfp_2op_sp(s, gen_VSQRT_sp, a->vd, a->vm);
-}
-
 static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
 {
     gen_helper_vfp_sqrtd(vd, vm, cpu_env);
 }
 
-static bool trans_VSQRT_dp(DisasContext *s, arg_VSQRT_dp *a)
-{
-    return do_vfp_2op_dp(s, gen_VSQRT_dp, a->vd, a->vm);
-}
+DO_VFP_2OP(VSQRT, sp, gen_VSQRT_sp)
+DO_VFP_2OP(VSQRT, dp, gen_VSQRT_dp)
 
 static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
 {
-- 
2.20.1



  parent reply	other threads:[~2020-09-01 15:25 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-01 15:17 [PULL 00/47] target-arm queue Peter Maydell
2020-09-01 15:17 ` [PULL 01/47] target/arm: Remove local definitions of float constants Peter Maydell
2020-09-01 15:17 ` [PULL 02/47] target/arm: Use correct ID register check for aa32_fp16_arith Peter Maydell
2020-09-01 15:17 ` [PULL 03/47] target/arm: Implement VFP fp16 for VFP_BINOP operations Peter Maydell
2020-09-01 15:17 ` [PULL 04/47] target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL Peter Maydell
2020-09-01 15:17 ` [PULL 05/47] target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS Peter Maydell
2020-09-01 15:17 ` [PULL 06/47] target/arm: Implement VFP fp16 for fused-multiply-add Peter Maydell
2020-09-01 15:17 ` Peter Maydell [this message]
2020-09-01 15:17 ` [PULL 08/47] target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT Peter Maydell
2020-09-01 15:17 ` [PULL 09/47] target/arm: Implement VFP fp16 for VMOV immediate Peter Maydell
2020-09-01 15:17 ` [PULL 10/47] target/arm: Implement VFP fp16 VCMP Peter Maydell
2020-09-01 15:17 ` [PULL 11/47] target/arm: Implement VFP fp16 VLDR and VSTR Peter Maydell
2020-09-01 15:17 ` [PULL 12/47] target/arm: Implement VFP fp16 VCVT between float and integer Peter Maydell
2020-09-01 15:17 ` [PULL 13/47] target/arm: Make VFP_CONV_FIX macros take separate float type and float size Peter Maydell
2020-09-01 15:17 ` [PULL 14/47] target/arm: Use macros instead of open-coding fp16 conversion helpers Peter Maydell
2020-09-01 15:17 ` [PULL 15/47] target/arm: Implement VFP fp16 VCVT between float and fixed-point Peter Maydell
2020-09-01 15:17 ` [PULL 16/47] target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode Peter Maydell
2020-09-01 15:17 ` [PULL 17/47] target/arm: Implement VFP fp16 VSEL Peter Maydell
2020-09-01 15:17 ` [PULL 18/47] target/arm: Implement VFP fp16 VRINT* Peter Maydell
2020-09-01 15:17 ` [PULL 19/47] target/arm: Implement new VFP fp16 insn VINS Peter Maydell
2020-09-01 15:17 ` [PULL 20/47] target/arm: Implement new VFP fp16 insn VMOVX Peter Maydell
2020-09-01 15:17 ` [PULL 21/47] target/arm: Implement VFP fp16 VMOV between gp and halfprec registers Peter Maydell
2020-09-01 15:17 ` [PULL 22/47] target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL Peter Maydell
2020-09-01 15:17 ` [PULL 23/47] target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec Peter Maydell
2020-09-01 15:18 ` [PULL 24/47] target/arm: Implement fp16 for Neon VABS, VNEG of floats Peter Maydell
2020-09-01 15:18 ` [PULL 25/47] target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons Peter Maydell
2020-09-01 15:18 ` [PULL 26/47] target/arm: Implement fp16 for VACGE, VACGT Peter Maydell
2020-09-01 15:18 ` [PULL 27/47] target/arm: Implement fp16 for Neon VMAX, VMIN Peter Maydell
2020-09-01 15:18 ` [PULL 28/47] target/arm: Implement fp16 for Neon VMAXNM, VMINNM Peter Maydell
2020-09-01 15:18 ` [PULL 29/47] target/arm: Implement fp16 for Neon VMLA, VMLS operations Peter Maydell
2020-09-01 15:18 ` [PULL 30/47] target/arm: Implement fp16 for Neon VFMA, VMFS Peter Maydell
2020-09-01 15:18 ` [PULL 31/47] target/arm: Implement fp16 for Neon fp compare-vs-0 Peter Maydell
2020-09-01 15:18 ` [PULL 32/47] target/arm: Implement fp16 for Neon VRECPS Peter Maydell
2020-09-01 15:18 ` [PULL 33/47] target/arm: Implement fp16 for Neon VRSQRTS Peter Maydell
2020-09-01 15:18 ` [PULL 34/47] target/arm: Implement fp16 for Neon pairwise fp ops Peter Maydell
2020-09-01 15:18 ` [PULL 35/47] target/arm: Implement fp16 for Neon float-integer VCVT Peter Maydell
2020-09-01 15:18 ` [PULL 36/47] target/arm: Convert Neon VCVT fixed-point to gvec Peter Maydell
2020-09-01 15:18 ` [PULL 37/47] target/arm: Implement fp16 for Neon VCVT fixed-point Peter Maydell
2020-09-01 15:18 ` [PULL 38/47] target/arm: Implement fp16 for Neon VCVT with rounding modes Peter Maydell
2020-09-01 15:18 ` [PULL 39/47] target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode Peter Maydell
2020-09-01 15:18 ` [PULL 40/47] target/arm: Implement fp16 for Neon VRINTX Peter Maydell
2020-09-01 15:18 ` [PULL 41/47] target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations Peter Maydell
2020-09-01 15:18 ` [PULL 42/47] target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations Peter Maydell
2020-09-01 15:18 ` [PULL 43/47] target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS Peter Maydell
2020-09-01 15:18 ` [PULL 44/47] target/arm: Enable FP16 in '-cpu max' Peter Maydell
2020-09-01 15:18 ` [PULL 45/47] hw/arm/sbsa-ref: add "reg" property to DT cpu nodes Peter Maydell
2020-09-01 15:18 ` [PULL 46/47] hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref Peter Maydell
2020-09-01 15:18 ` [PULL 47/47] hw/arm/sbsa-ref : Add embedded controller in secure memory Peter Maydell
2020-09-01 21:47 ` [PULL 00/47] target-arm queue Peter Maydell
2020-09-02 10:16 ` no-reply

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