From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: edgar.iglesias@xilinx.com, f4bug@amsat.org
Subject: [PATCH v3 04/19] target/microblaze: Rename mmu structs
Date: Fri, 4 Sep 2020 12:08:27 -0700 [thread overview]
Message-ID: <20200904190842.2282109-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200904190842.2282109-1-richard.henderson@linaro.org>
Introduce typedefs and follow CODING_STYLE for naming.
Rename struct microblaze_mmu to MicroBlazeMMU.
Rename struct microblaze_mmu_lookup to MicroBlazeMMULookup.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/cpu.h | 2 +-
target/microblaze/mmu.h | 15 ++++++---------
target/microblaze/helper.c | 4 ++--
target/microblaze/mmu.c | 11 +++++------
4 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 32811f773d..20c2979396 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -278,7 +278,7 @@ struct CPUMBState {
#if !defined(CONFIG_USER_ONLY)
/* Unified MMU. */
- struct microblaze_mmu mmu;
+ MicroBlazeMMU mmu;
#endif
/* Fields up to this point are cleared by a CPU reset */
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h
index 75e5301c79..c1feb811b9 100644
--- a/target/microblaze/mmu.h
+++ b/target/microblaze/mmu.h
@@ -63,8 +63,7 @@
#define TLB_ENTRIES 64
-struct microblaze_mmu
-{
+typedef struct {
/* Data and tag brams. */
uint64_t rams[2][TLB_ENTRIES];
/* We keep a separate ram for the tids to avoid the 48 bit tag width. */
@@ -76,10 +75,9 @@ struct microblaze_mmu
int c_mmu_tlb_access;
int c_mmu_zones;
uint64_t c_addr_mask; /* Mask to apply to physical addresses. */
-};
+} MicroBlazeMMU;
-struct microblaze_mmu_lookup
-{
+typedef struct {
uint32_t paddr;
uint32_t vaddr;
unsigned int size;
@@ -88,13 +86,12 @@ struct microblaze_mmu_lookup
enum {
ERR_PROT, ERR_MISS, ERR_HIT
} err;
-};
+} MicroBlazeMMULookup;
-unsigned int mmu_translate(struct microblaze_mmu *mmu,
- struct microblaze_mmu_lookup *lu,
+unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx);
uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn);
void mmu_write(CPUMBState *env, bool ea, uint32_t rn, uint32_t v);
-void mmu_init(struct microblaze_mmu *mmu);
+void mmu_init(MicroBlazeMMU *mmu);
#endif
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c
index 27a24bb99a..3c2fd388fb 100644
--- a/target/microblaze/helper.c
+++ b/target/microblaze/helper.c
@@ -52,7 +52,7 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUMBState *env = &cpu->env;
- struct microblaze_mmu_lookup lu;
+ MicroBlazeMMULookup lu;
unsigned int hit;
int prot;
@@ -235,7 +235,7 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUMBState *env = &cpu->env;
target_ulong vaddr, paddr = 0;
- struct microblaze_mmu_lookup lu;
+ MicroBlazeMMULookup lu;
int mmu_idx = cpu_mmu_index(env, false);
unsigned int hit;
diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
index 6e583d78d9..0546cfd0bc 100644
--- a/target/microblaze/mmu.c
+++ b/target/microblaze/mmu.c
@@ -35,7 +35,7 @@ static unsigned int tlb_decode_size(unsigned int f)
static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
CPUState *cs = env_cpu(env);
- struct microblaze_mmu *mmu = &env->mmu;
+ MicroBlazeMMU *mmu = &env->mmu;
unsigned int tlb_size;
uint32_t tlb_tag, end, t;
@@ -55,7 +55,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
{
- struct microblaze_mmu *mmu = &env->mmu;
+ MicroBlazeMMU *mmu = &env->mmu;
unsigned int i;
uint32_t t;
@@ -73,8 +73,7 @@ static void mmu_change_pid(CPUMBState *env, unsigned int newpid)
}
/* rw - 0 = read, 1 = write, 2 = fetch. */
-unsigned int mmu_translate(struct microblaze_mmu *mmu,
- struct microblaze_mmu_lookup *lu,
+unsigned int mmu_translate(MicroBlazeMMU *mmu, MicroBlazeMMULookup *lu,
target_ulong vaddr, int rw, int mmu_idx)
{
unsigned int i, hit = 0;
@@ -290,7 +289,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
break;
case MMU_R_TLBSX:
{
- struct microblaze_mmu_lookup lu;
+ MicroBlazeMMULookup lu;
int hit;
if (env->mmu.c_mmu_tlb_access <= 1) {
@@ -314,7 +313,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
}
}
-void mmu_init(struct microblaze_mmu *mmu)
+void mmu_init(MicroBlazeMMU *mmu)
{
int i;
for (i = 0; i < ARRAY_SIZE(mmu->regs); i++) {
--
2.25.1
next prev parent reply other threads:[~2020-09-04 19:12 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-04 19:08 [PATCH v3 00/19] target/microblaze improvements Richard Henderson
2020-09-04 19:08 ` [PATCH v3 01/19] target/microblaze: Collected fixes for env->iflags Richard Henderson
2020-09-04 19:08 ` [PATCH v3 02/19] target/microblaze: Renumber D_FLAG Richard Henderson
2020-09-04 19:08 ` [PATCH v3 03/19] target/microblaze: Cleanup mb_cpu_do_interrupt Richard Henderson
2020-09-04 19:08 ` Richard Henderson [this message]
2020-09-04 19:08 ` [PATCH v3 05/19] target/microblaze: Rename DISAS_UPDATE to DISAS_EXIT Richard Henderson
2020-09-04 19:08 ` [PATCH v3 06/19] target/microblaze: Introduce DISAS_EXIT_NEXT, DISAS_EXIT_JUMP Richard Henderson
2020-09-04 19:08 ` [PATCH v3 07/19] target/microblaze: Replace cpustate_changed with DISAS_EXIT_NEXT Richard Henderson
2020-09-04 19:08 ` [PATCH v3 08/19] target/microblaze: Handle DISAS_EXIT_NEXT in delay slot Richard Henderson
2020-09-04 19:08 ` [PATCH v3 09/19] target/microblaze: Force rtid, rted, rtbd to exit Richard Henderson
2020-09-04 19:08 ` [PATCH v3 10/19] target/microblaze: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
2020-09-04 19:08 ` [PATCH v3 11/19] target/microblaze: Diagnose invalid insns in delay slots Richard Henderson
2020-09-04 19:08 ` [PATCH v3 12/19] target/microblaze: Split out MicroBlazeCPUConfig Richard Henderson
2020-09-05 21:35 ` Philippe Mathieu-Daudé
2020-09-04 19:08 ` [PATCH v3 13/19] target/microblaze: Reorg MicroBlazeCPUConfig to minimize holes Richard Henderson
2020-09-05 21:36 ` Philippe Mathieu-Daudé
2020-09-04 19:08 ` [PATCH v3 14/19] target/microblaze: Move pvr regs to MicroBlazeCPUConfig Richard Henderson
2020-09-05 21:39 ` Philippe Mathieu-Daudé
2020-09-04 19:08 ` [PATCH v3 15/19] target/microblaze: Treat pvr_regs as constant Richard Henderson
2020-09-04 19:08 ` [PATCH v3 16/19] target/microblaze: Move mmu parameters to MicroBlazeCPUConfig Richard Henderson
2020-09-05 21:41 ` Philippe Mathieu-Daudé
2020-09-04 19:08 ` [PATCH v3 17/19] target/microblaze: Fill in VMStateDescription for cpu Richard Henderson
2020-09-04 19:08 ` [PATCH v3 18/19] target/microblaze: Put MicroBlazeCPUConfig into DisasContext Richard Henderson
2020-09-05 21:42 ` Philippe Mathieu-Daudé
2020-09-04 19:08 ` [PATCH v3 19/19] configure: Do not set TARGET_ABI32 for microblaze Richard Henderson
2020-09-07 9:20 ` [PATCH v3 00/19] target/microblaze improvements Edgar E. Iglesias
2020-09-07 17:43 ` Richard Henderson
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