From: Leif Lindholm <leif@nuviainc.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Alistair Francis" <alistair@alistair23.me>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
"Bin Meng" <bin.meng@windriver.com>,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Jason Wang" <jasowang@redhat.com>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"Marc-André Lureau" <marcandre.lureau@redhat.com>,
qemu-arm <qemu-arm@nongnu.org>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>
Subject: Re: [PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support
Date: Mon, 7 Sep 2020 18:27:12 +0100 [thread overview]
Message-ID: <20200907172712.GB5623@vanye> (raw)
In-Reply-To: <CAEUhbmVfSPwO5CHO2G5Vd5fA6NA4dRCp-e_KGJhSO7nYAPmi1w@mail.gmail.com>
On Mon, Sep 07, 2020 at 18:24:06 +0800, Bin Meng wrote:
> Hi Leif,
>
>
> On Sun, Sep 6, 2020 at 9:08 AM Leif Lindholm <leif@nuviainc.com> wrote:
> >
> > On Tue, Sep 01, 2020 at 09:38:55 +0800, Bin Meng wrote:
> > > From: Bin Meng <bin.meng@windriver.com>
> > >
> > > This adds support for Microchip PolarFire SoC Icicle Kit board.
> > > The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
> > > E51 plus four U54 cores and many on-chip peripherals and an FPGA.
> > >
> > > For more details about Microchip PolarFire SoC, please see:
> > > https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga
> > >
> > > The Icicle Kit board information can be found here:
> > > https://www.microsemi.com/existing-parts/parts/152514
> > >
> > > Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000.
> > > The RISC-V CPU and HART codes has been updated to set the core's
> > > reset vector based on a configurable property from machine codes.
> > >
> > > The following perepherals are created as an unimplemented device:
> > >
> > > - Bus Error Uint 0/1/2/3/4
> > > - L2 cache controller
> > > - SYSREG
> > > - MPUCFG
> > > - IOSCBCFG
> > > - GPIO
> > >
> > > The following perepherals are emulated:
> > > - SiFive CLINT
> > > - SiFive PLIC
> > > - PolarFire SoC Multi-Mode UART
> > > - SiFive PDMA
> > > - Cadence eMMC/SDHCI controller
> > > - Cadence Gigabit Ethernet MAC
> > >
> > > The BIOS image used by this machine is hss.bin, aka Hart Software
> > > Services, which can be built from:
> > > https://github.com/polarfire-soc/hart-software-services
> > >
> > > To launch this machine:
> > > $ qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \
> > > -bios path/to/hss.bin -sd path/to/sdcard.img \
> > > -nic tap,ifname=tap,script=no,model=cadence_gem \
> > > -display none -serial stdio \
> > > -chardev socket,id=serial1,path=serial1.sock,server,wait \
> > > -serial chardev:serial1
> >
> > I finally got around to building the sd image from
> > https://github.com/polarfire-soc/polarfire-soc-buildroot-sdk,
> > and I can successfully boot to prompt using that, and the (hacked)
> > hss.bin I verified previously - also with this v3.
> >
>
> Good to know!
>
> > However, unless I add the "-nic user,model=cadence_gem \" shown in
> > https://wiki.qemu.org/Documentation/Platforms/RISCV#Microchip_PolarFire_SoC_Icicle_Kit
> > but not here, I do not have functioning networking. (It is not obvious
> > to me why this is needed.)
> >
>
> Sorry I don't understand what the issue is?
The instructions in this cover letter does not contain the line
"-nic user,model=cadence_gem \"
The instruction in the wiki does.
The instruction in the wiki works, the instruction in the cover letter
does not.
It is not clear to me why both lines are needed.
> > > The memory is set to 1 GiB by default to match the hardware.
> >
> > Which hardware is this?
> > https://www.crowdsupply.com/microchip/polarfire-soc-icicle-kit lists
> > 2GiB.
>
> It's this same board. But I believe the crowdsupply webpage has the
> wrong information. The board I got only has 1GB memory.
The diagram on https://www.microsemi.com/existing-parts/parts/152514
also says 2GB. Do you have any channel to Microchip to clarify this?
> > > A sanity check on ram size is performed in the machine init routine
> > > to prompt user to increase the RAM size to > 1 GiB when less than
> > > 1 GiB ram is detected.
> >
> > There is currently no visible effect in firmware from setting memory size to >
> > 1GiB (hss says 1GB, u-boot says 1GB, Linux sees 1GB).
> > Are there any plans to address this in future versions?
>
> HSS is using hardcoded 1GB memory size and that's why in QEMU the
> minimum required memory size is 1GB. Setting less than 1GB size blocks
> HSS to load the 2nd stage bootloader U-Boot into the memory. Both
> U-Boot and Linux DTS files set the memory size to 1GB, so that's why
> both of them see only 1GB. Setting memory >1G does not affect U-Boot
> and Linux though. You can however manually edit the U-Boot and Linux
> DTS files to have a large RAM size to match QEMU -m option.
Understood, thanks.
Best Regards,
Leif
next prev parent reply other threads:[~2020-09-07 17:28 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-01 1:38 [PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-09-01 1:38 ` [PATCH v3 01/16] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-09-01 9:36 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 02/16] hw/riscv: hart: " Bin Meng
2020-09-01 9:37 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 03/16] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-09-01 9:37 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-09-01 1:39 ` [PATCH v3 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-09-04 17:47 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Bin Meng
2020-09-01 1:39 ` [PATCH v3 07/16] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-09-04 19:30 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-09-01 9:42 ` Philippe Mathieu-Daudé
2020-09-01 10:27 ` Bin Meng
2020-09-01 17:56 ` Philippe Mathieu-Daudé
2020-09-04 19:08 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 09/16] hw/dma: Add SiFive platform DMA controller emulation Bin Meng
2020-09-04 20:25 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-09-04 19:33 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property Bin Meng
2020-09-01 9:43 ` Philippe Mathieu-Daudé
2020-09-02 10:45 ` Edgar E. Iglesias
2020-09-04 19:34 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Bin Meng
2020-09-01 9:45 ` Philippe Mathieu-Daudé
2020-09-02 0:16 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-09-01 9:46 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-09-01 9:47 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-09-01 9:49 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 16/16] hw/riscv: sifive_u: Connect a DMA controller Bin Meng
2020-09-04 19:36 ` Alistair Francis
2020-09-04 20:29 ` [PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Alistair Francis
2020-09-06 1:08 ` Leif Lindholm
2020-09-07 10:24 ` Bin Meng
2020-09-07 17:27 ` Leif Lindholm [this message]
2020-09-08 1:15 ` Bin Meng
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