* [PATCH 00/43] tcg patch queue
@ 2020-09-09 0:16 Richard Henderson
2020-09-09 0:16 ` [PATCH 01/43] tcg: Adjust simd_desc size encoding Richard Henderson
` (42 more replies)
0 siblings, 43 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
This patch collection contains:
* A couple of fixes for i386 host vector support.
* Some random cleanups cherry-picked from some inactive branches.
* A reposting (with fix) of my "better handling of constants" set:
https://lists.nongnu.org/archive/html/qemu-devel/2020-05/msg02152.html
* A couple patches that centralizes the set of host constraints.
This, I believe is slightly cleaner than the current state of
afairs, even before the ultimtate goal of pre-validating the
contents as well.
r~
Richard Henderson (43):
tcg: Adjust simd_desc size encoding
tcg: Drop union from TCGArgConstraint
tcg: Move sorted_args into TCGArgConstraint.sort_index
tcg: Remove TCG_CT_REG
tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
tcg: Remove TCGOpDef.used
tcg/i386: Fix dupi for avx2 32-bit hosts
tcg: Fix generation of dupi_vec for 32-bit host
tcg/optimize: Fold dup2_vec
tcg: Remove TCG_TARGET_HAS_cmp_vec
tcg: Use tcg_out_dupi_vec from temp_load
tcg: Increase tcg_out_dupi_vec immediate to int64_t
tcg: Consolidate 3 bits into enum TCGTempKind
tcg: Add temp_readonly
tcg: Expand TCGTemp.val to 64-bits
tcg: Rename struct tcg_temp_info to TempOptInfo
tcg: Expand TempOptInfo to 64-bits
tcg: Introduce TYPE_CONST temporaries
tcg/optimize: Improve find_better_copy
tcg/optimize: Adjust TempOptInfo allocation
tcg/optimize: Use tcg_constant_internal with constant folding
tcg: Convert tcg_gen_dupi_vec to TCG_CONST
tcg: Use tcg_constant_i32 with icount expander
tcg: Use tcg_constant_{i32,i64} with tcg int expanders
tcg: Use tcg_constant_{i32,i64} with tcg plugins
tcg: Use tcg_constant_{i32,i64,vec} with gvec expanders
tcg/tci: Add special tci_movi_{i32,i64} opcodes
tcg: Remove movi and dupi opcodes
tcg: Add tcg_reg_alloc_dup2
tcg/i386: Use tcg_constant_vec with tcg vec expanders
tcg: Remove tcg_gen_dup{8,16,32,64}i_vec
tcg/ppc: Use tcg_constant_vec with tcg vec expanders
tcg/aarch64: Use tcg_constant_vec with tcg vec expanders
tcg: Add tcg-constr.c.inc
tcg/i386: Convert to tcg-constr.c.inc
tcg/aarch64: Convert to tcg-constr.c.inc
tcg/arm: Convert to tcg-constr.c.inc
tcg/mips: Convert to tcg-constr.c.inc
tcg/ppc: Convert to tcg-constr.c.inc
tcg/riscv: Convert to tcg-constr.c.inc
tcg/s390: Convert to tcg-constr.c.inc
tcg/sparc: Convert to tcg-constr.c.inc
tcg/tci: Convert to tcg-constr.c.inc
include/exec/gen-icount.h | 25 +-
include/tcg/tcg-gvec-desc.h | 38 ++-
include/tcg/tcg-op.h | 17 +-
include/tcg/tcg-opc.h | 11 +-
include/tcg/tcg.h | 72 +++--
tcg/aarch64/tcg-target-constr.h | 31 ++
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target-constr.h | 30 ++
tcg/i386/tcg-target-constr.h | 55 ++++
tcg/i386/tcg-target.h | 1 -
tcg/mips/tcg-target-constr.h | 31 ++
tcg/ppc/tcg-target-constr.h | 37 +++
tcg/ppc/tcg-target.h | 1 -
tcg/riscv/tcg-target-constr.h | 25 ++
tcg/s390/tcg-target-constr.h | 24 ++
tcg/sparc/tcg-target-constr.h | 27 ++
tcg/tci/tcg-target-constr.h | 28 ++
accel/tcg/plugin-gen.c | 49 ++-
tcg/optimize.c | 254 ++++++++-------
tcg/tcg-op-gvec.c | 160 +++++-----
tcg/tcg-op-vec.c | 48 +--
tcg/tcg-op.c | 227 +++++++------
tcg/tcg.c | 549 +++++++++++++++++++++++---------
tcg/tci.c | 4 +-
tcg/aarch64/tcg-target.c.inc | 134 +++-----
tcg/arm/tcg-target.c.inc | 123 +++----
tcg/i386/tcg-target.c.inc | 336 +++++++++----------
tcg/mips/tcg-target.c.inc | 118 +++----
tcg/ppc/tcg-target.c.inc | 254 +++++++--------
tcg/riscv/tcg-target.c.inc | 100 ++----
tcg/s390/tcg-target.c.inc | 143 ++++-----
tcg/sparc/tcg-target.c.inc | 97 ++----
tcg/tcg-constr.c.inc | 108 +++++++
tcg/tci/tcg-target.c.inc | 369 ++++++++-------------
34 files changed, 1893 insertions(+), 1634 deletions(-)
create mode 100644 tcg/aarch64/tcg-target-constr.h
create mode 100644 tcg/arm/tcg-target-constr.h
create mode 100644 tcg/i386/tcg-target-constr.h
create mode 100644 tcg/mips/tcg-target-constr.h
create mode 100644 tcg/ppc/tcg-target-constr.h
create mode 100644 tcg/riscv/tcg-target-constr.h
create mode 100644 tcg/s390/tcg-target-constr.h
create mode 100644 tcg/sparc/tcg-target-constr.h
create mode 100644 tcg/tci/tcg-target-constr.h
create mode 100644 tcg/tcg-constr.c.inc
--
2.25.1
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 01/43] tcg: Adjust simd_desc size encoding
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 02/43] tcg: Drop union from TCGArgConstraint Richard Henderson
` (41 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
With larger vector sizes, it turns out oprsz == maxsz, and we only
need to represent mismatch for oprsz <= 32. We do, however, need
to represent larger oprsz and do so without reducing SIMD_DATA_BITS.
Reduce the size of the oprsz field and increase the maxsz field.
Steal the oprsz value of 24 to indicate equality with maxsz.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-gvec-desc.h | 38 ++++++++++++++++++++++++-------------
tcg/tcg-op-gvec.c | 35 ++++++++++++++++++++++++++--------
2 files changed, 52 insertions(+), 21 deletions(-)
diff --git a/include/tcg/tcg-gvec-desc.h b/include/tcg/tcg-gvec-desc.h
index 0224ac3e78..704bd86454 100644
--- a/include/tcg/tcg-gvec-desc.h
+++ b/include/tcg/tcg-gvec-desc.h
@@ -20,29 +20,41 @@
#ifndef TCG_TCG_GVEC_DESC_H
#define TCG_TCG_GVEC_DESC_H
-/* ??? These bit widths are set for ARM SVE, maxing out at 256 byte vectors. */
-#define SIMD_OPRSZ_SHIFT 0
-#define SIMD_OPRSZ_BITS 5
+/*
+ * This configuration allows MAXSZ to represent 2048 bytes, and
+ * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32.
+ *
+ * Encode this with:
+ * 0, 1, 3 -> 8, 16, 32
+ * 2 -> maxsz
+ *
+ * This steals the input that would otherwise map to 24 to match maxsz.
+ */
+#define SIMD_MAXSZ_SHIFT 0
+#define SIMD_MAXSZ_BITS 8
-#define SIMD_MAXSZ_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
-#define SIMD_MAXSZ_BITS 5
+#define SIMD_OPRSZ_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+#define SIMD_OPRSZ_BITS 2
-#define SIMD_DATA_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS)
+#define SIMD_DATA_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS)
#define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT)
/* Create a descriptor from components. */
uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
-/* Extract the operation size from a descriptor. */
-static inline intptr_t simd_oprsz(uint32_t desc)
-{
- return (extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS) + 1) * 8;
-}
-
/* Extract the max vector size from a descriptor. */
static inline intptr_t simd_maxsz(uint32_t desc)
{
- return (extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) + 1) * 8;
+ return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8;
+}
+
+/* Extract the operation size from a descriptor. */
+static inline intptr_t simd_oprsz(uint32_t desc)
+{
+ uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS);
+ intptr_t o = f * 8 + 8;
+ intptr_t m = simd_maxsz(desc);
+ return f == 2 ? m : o;
}
/* Extract the operation-specific data from a descriptor. */
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 7ebd9e8298..ddbe06b71a 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -37,11 +37,21 @@ static const TCGOpcode vecop_list_empty[1] = { 0 };
of the operand offsets so that we can check them all at once. */
static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
{
- uint32_t opr_align = oprsz >= 16 ? 15 : 7;
- uint32_t max_align = maxsz >= 16 || oprsz >= 16 ? 15 : 7;
- tcg_debug_assert(oprsz > 0);
- tcg_debug_assert(oprsz <= maxsz);
- tcg_debug_assert((oprsz & opr_align) == 0);
+ uint32_t max_align;
+
+ switch (oprsz) {
+ case 8:
+ case 16:
+ case 32:
+ tcg_debug_assert(oprsz <= maxsz);
+ break;
+ default:
+ tcg_debug_assert(oprsz == maxsz);
+ break;
+ }
+ tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS));
+
+ max_align = maxsz >= 16 ? 15 : 7;
tcg_debug_assert((maxsz & max_align) == 0);
tcg_debug_assert((ofs & max_align) == 0);
}
@@ -77,12 +87,21 @@ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
{
uint32_t desc = 0;
- assert(oprsz % 8 == 0 && oprsz <= (8 << SIMD_OPRSZ_BITS));
- assert(maxsz % 8 == 0 && maxsz <= (8 << SIMD_MAXSZ_BITS));
- assert(data == sextract32(data, 0, SIMD_DATA_BITS));
+ check_size_align(oprsz, maxsz, 0);
+ tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));
oprsz = (oprsz / 8) - 1;
maxsz = (maxsz / 8) - 1;
+
+ /*
+ * We have just asserted in check_size_align that either
+ * oprsz is {8,16,32} or matches maxsz. Encode the final
+ * case with '2', as that would otherwise map to 24.
+ */
+ if (oprsz == maxsz) {
+ oprsz = 2;
+ }
+
desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 02/43] tcg: Drop union from TCGArgConstraint
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
2020-09-09 0:16 ` [PATCH 01/43] tcg: Adjust simd_desc size encoding Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 17:43 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 03/43] tcg: Move sorted_args into TCGArgConstraint.sort_index Richard Henderson
` (40 subsequent siblings)
42 siblings, 1 reply; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
The union is unused; let "regs" appear in the main structure
without the "u.regs" wrapping.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 4 +---
tcg/tcg.c | 22 +++++++++++-----------
tcg/aarch64/tcg-target.c.inc | 14 +++++++-------
tcg/arm/tcg-target.c.inc | 26 +++++++++++++-------------
tcg/i386/tcg-target.c.inc | 26 +++++++++++++-------------
tcg/mips/tcg-target.c.inc | 18 +++++++++---------
tcg/ppc/tcg-target.c.inc | 24 ++++++++++++------------
tcg/riscv/tcg-target.c.inc | 14 +++++++-------
tcg/s390/tcg-target.c.inc | 18 +++++++++---------
tcg/sparc/tcg-target.c.inc | 16 ++++++++--------
tcg/tci/tcg-target.c.inc | 2 +-
11 files changed, 91 insertions(+), 93 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 53ce94c2c5..a5a0ea4ada 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -985,9 +985,7 @@ void tcg_dump_op_count(void);
typedef struct TCGArgConstraint {
uint16_t ct;
uint8_t alias_index;
- union {
- TCGRegSet regs;
- } u;
+ TCGRegSet regs;
} TCGArgConstraint;
#define TCG_MAX_OP_ARGS 16
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 62f299e36e..dcb38bf1e0 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2210,7 +2210,7 @@ static int get_constraint_priority(const TCGOpDef *def, int k)
return 0;
n = 0;
for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
- if (tcg_regset_test_reg(arg_ct->u.regs, i))
+ if (tcg_regset_test_reg(arg_ct->regs, i))
n++;
}
}
@@ -2268,7 +2268,7 @@ static void process_op_defs(TCGContext *s)
/* Incomplete TCGTargetOpDef entry. */
tcg_debug_assert(ct_str != NULL);
- def->args_ct[i].u.regs = 0;
+ def->args_ct[i].regs = 0;
def->args_ct[i].ct = 0;
while (*ct_str != '\0') {
switch(*ct_str) {
@@ -2855,13 +2855,13 @@ static void liveness_pass_1(TCGContext *s)
pset = la_temp_pref(ts);
set = *pset;
- set &= ct->u.regs;
+ set &= ct->regs;
if (ct->ct & TCG_CT_IALIAS) {
set &= op->output_pref[ct->alias_index];
}
/* If the combination is not possible, restart. */
if (set == 0) {
- set = ct->u.regs;
+ set = ct->regs;
}
*pset = set;
}
@@ -3551,8 +3551,8 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
return;
}
- dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs;
- dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs;
+ dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
+ dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
/* Allocate the output register now. */
if (ots->val_type != TEMP_VAL_REG) {
@@ -3706,10 +3706,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
}
- temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs);
+ temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
reg = ts->reg;
- if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
+ if (tcg_regset_test_reg(arg_ct->regs, reg)) {
/* nothing to do : the constraint is satisfied */
} else {
allocate_in_reg:
@@ -3717,7 +3717,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
and move the temporary register into it */
temp_load(s, ts, tcg_target_available_regs[ts->type],
i_allocated_regs, 0);
- reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs,
+ reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
o_preferred_regs, ts->indirect_base);
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
/*
@@ -3772,11 +3772,11 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
&& !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index];
} else if (arg_ct->ct & TCG_CT_NEWREG) {
- reg = tcg_reg_alloc(s, arg_ct->u.regs,
+ reg = tcg_reg_alloc(s, arg_ct->regs,
i_allocated_regs | o_allocated_regs,
op->output_pref[k], ts->indirect_base);
} else {
- reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs,
+ reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs,
op->output_pref[k], ts->indirect_base);
}
tcg_regset_set_reg(o_allocated_regs, reg);
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 948c35d825..d4b7cb4867 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -129,22 +129,22 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'r': /* general registers */
ct->ct |= TCG_CT_REG;
- ct->u.regs |= 0xffffffffu;
+ ct->regs |= 0xffffffffu;
break;
case 'w': /* advsimd registers */
ct->ct |= TCG_CT_REG;
- ct->u.regs |= 0xffffffff00000000ull;
+ ct->regs |= 0xffffffff00000000ull;
break;
case 'l': /* qemu_ld / qemu_st address, data_reg */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffffu;
+ ct->regs = 0xffffffffu;
#ifdef CONFIG_SOFTMMU
/* x0 and x1 will be overwritten when reading the tlb entry,
and x2, and x3 for helper args, better to avoid using them. */
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
#endif
break;
case 'A': /* Valid for arithmetic immediate (positive or negative). */
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index bc1e1b5a71..978eb1dd70 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -254,40 +254,40 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'r':
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffff;
+ ct->regs = 0xffff;
break;
/* qemu_ld address */
case 'l':
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffff;
+ ct->regs = 0xffff;
#ifdef CONFIG_SOFTMMU
/* r0-r2,lr will be overwritten when reading the tlb entry,
so don't use these. */
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
#endif
break;
/* qemu_st address & data */
case 's':
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffff;
+ ct->regs = 0xffff;
/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
and r0-r1 doing the byte swapping, so don't use these. */
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
#if defined(CONFIG_SOFTMMU)
/* Avoid clashes with registers being used for helper args */
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
#if TARGET_LONG_BITS == 64
/* Avoid clashes with registers being used for helper args */
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#endif
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
#endif
break;
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 0155c0691c..8661ec3393 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -209,42 +209,42 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch(*ct_str++) {
case 'a':
ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX);
+ tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
break;
case 'b':
ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX);
+ tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
break;
case 'c':
ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX);
+ tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
break;
case 'd':
ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX);
+ tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
break;
case 'S':
ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI);
+ tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
break;
case 'D':
ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI);
+ tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
break;
case 'q':
/* A register that can be used as a byte operand. */
ct->ct |= TCG_CT_REG;
- ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
+ ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
break;
case 'Q':
/* A register with an addressable second byte (e.g. %ah). */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xf;
+ ct->regs = 0xf;
break;
case 'r':
/* A general register. */
ct->ct |= TCG_CT_REG;
- ct->u.regs |= ALL_GENERAL_REGS;
+ ct->regs |= ALL_GENERAL_REGS;
break;
case 'W':
/* With TZCNT/LZCNT, we can have operand-size as an input. */
@@ -253,15 +253,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'x':
/* A vector register. */
ct->ct |= TCG_CT_REG;
- ct->u.regs |= ALL_VECTOR_REGS;
+ ct->regs |= ALL_VECTOR_REGS;
break;
/* qemu_ld/st address constraint */
case 'L':
ct->ct |= TCG_CT_REG;
- ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1);
+ ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
+ tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
break;
case 'e':
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index bd5b8e09a0..d49a02bb03 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -196,28 +196,28 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch(*ct_str++) {
case 'r':
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
+ ct->regs = 0xffffffff;
break;
case 'L': /* qemu_ld input arg constraint */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
+ ct->regs = 0xffffffff;
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
}
#endif
break;
case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0);
+ ct->regs = 0xffffffff;
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
} else {
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
}
#endif
break;
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 393c4b30e0..450b555522 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -225,33 +225,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'A': case 'B': case 'C': case 'D':
ct->ct |= TCG_CT_REG;
- tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
+ tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
break;
case 'r':
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
+ ct->regs = 0xffffffff;
break;
case 'v':
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff00000000ull;
+ ct->regs = 0xffffffff00000000ull;
break;
case 'L': /* qemu_ld constraint */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+ ct->regs = 0xffffffff;
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
#endif
break;
case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+ ct->regs = 0xffffffff;
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
#endif
break;
case 'I':
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 2dfb07e247..0a69839adb 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -138,19 +138,19 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'r':
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
+ ct->regs = 0xffffffff;
break;
case 'L':
/* qemu_ld/qemu_st constraint */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
+ ct->regs = 0xffffffff;
/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
#if defined(CONFIG_SOFTMMU)
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
- tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
+ tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
#endif
break;
case 'I':
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 985115acfb..9cd266a2d0 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -409,24 +409,24 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'r': /* all registers */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffff;
+ ct->regs = 0xffff;
break;
case 'L': /* qemu_ld/st constraint */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffff;
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
+ ct->regs = 0xffff;
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
break;
case 'a': /* force R2 for division */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_R2);
+ ct->regs = 0;
+ tcg_regset_set_reg(ct->regs, TCG_REG_R2);
break;
case 'b': /* force R3 for division */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0;
- tcg_regset_set_reg(ct->u.regs, TCG_REG_R3);
+ ct->regs = 0;
+ tcg_regset_set_reg(ct->regs, TCG_REG_R3);
break;
case 'A':
ct->ct |= TCG_CT_CONST_S33;
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index 0f1d91fc21..c662293fc7 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -326,27 +326,27 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'r':
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
+ ct->regs = 0xffffffff;
break;
case 'R':
ct->ct |= TCG_CT_REG;
- ct->u.regs = ALL_64;
+ ct->regs = ALL_64;
break;
case 'A': /* qemu_ld/st address constraint */
ct->ct |= TCG_CT_REG;
- ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
+ ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
reserve_helpers:
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1);
- tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
+ tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
break;
case 's': /* qemu_st data 32-bit constraint */
ct->ct |= TCG_CT_REG;
- ct->u.regs = 0xffffffff;
+ ct->regs = 0xffffffff;
goto reserve_helpers;
case 'S': /* qemu_st data 64-bit constraint */
ct->ct |= TCG_CT_REG;
- ct->u.regs = ALL_64;
+ ct->regs = ALL_64;
goto reserve_helpers;
case 'I':
ct->ct |= TCG_CT_CONST_S11;
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 992d50cb1e..a7215f346f 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -393,7 +393,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'L': /* qemu_ld constraint */
case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG;
- ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
+ ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
break;
default:
return NULL;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 03/43] tcg: Move sorted_args into TCGArgConstraint.sort_index
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
2020-09-09 0:16 ` [PATCH 01/43] tcg: Adjust simd_desc size encoding Richard Henderson
2020-09-09 0:16 ` [PATCH 02/43] tcg: Drop union from TCGArgConstraint Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 04/43] tcg: Remove TCG_CT_REG Richard Henderson
` (39 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
This uses an existing hole in the TCGArgConstraint structure
and will be convenient for keeping the data in one place.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 2 +-
tcg/tcg.c | 35 +++++++++++++++++------------------
2 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index a5a0ea4ada..63955ac85b 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -985,6 +985,7 @@ void tcg_dump_op_count(void);
typedef struct TCGArgConstraint {
uint16_t ct;
uint8_t alias_index;
+ uint8_t sort_index;
TCGRegSet regs;
} TCGArgConstraint;
@@ -1015,7 +1016,6 @@ typedef struct TCGOpDef {
uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
uint8_t flags;
TCGArgConstraint *args_ct;
- int *sorted_args;
#if defined(CONFIG_DEBUG_TCG)
int used;
#endif
diff --git a/tcg/tcg.c b/tcg/tcg.c
index dcb38bf1e0..0a04b6cbd9 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -944,7 +944,6 @@ void tcg_context_init(TCGContext *s)
int op, total_args, n, i;
TCGOpDef *def;
TCGArgConstraint *args_ct;
- int *sorted_args;
TCGTemp *ts;
memset(s, 0, sizeof(*s));
@@ -960,14 +959,11 @@ void tcg_context_init(TCGContext *s)
}
args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
- sorted_args = g_malloc(sizeof(int) * total_args);
for(op = 0; op < NB_OPS; op++) {
def = &tcg_op_defs[op];
def->args_ct = args_ct;
- def->sorted_args = sorted_args;
n = def->nb_iargs + def->nb_oargs;
- sorted_args += n;
args_ct += n;
}
@@ -2220,20 +2216,23 @@ static int get_constraint_priority(const TCGOpDef *def, int k)
/* sort from highest priority to lowest */
static void sort_constraints(TCGOpDef *def, int start, int n)
{
- int i, j, p1, p2, tmp;
+ int i, j;
+ TCGArgConstraint *a = def->args_ct;
- for(i = 0; i < n; i++)
- def->sorted_args[start + i] = start + i;
- if (n <= 1)
+ for (i = 0; i < n; i++) {
+ a[start + i].sort_index = start + i;
+ }
+ if (n <= 1) {
return;
- for(i = 0; i < n - 1; i++) {
- for(j = i + 1; j < n; j++) {
- p1 = get_constraint_priority(def, def->sorted_args[start + i]);
- p2 = get_constraint_priority(def, def->sorted_args[start + j]);
+ }
+ for (i = 0; i < n - 1; i++) {
+ for (j = i + 1; j < n; j++) {
+ int p1 = get_constraint_priority(def, a[start + i].sort_index);
+ int p2 = get_constraint_priority(def, a[start + j].sort_index);
if (p1 < p2) {
- tmp = def->sorted_args[start + i];
- def->sorted_args[start + i] = def->sorted_args[start + j];
- def->sorted_args[start + j] = tmp;
+ int tmp = a[start + i].sort_index;
+ a[start + i].sort_index = a[start + j].sort_index;
+ a[start + j].sort_index = tmp;
}
}
}
@@ -3659,7 +3658,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
for (k = 0; k < nb_iargs; k++) {
TCGRegSet i_preferred_regs, o_preferred_regs;
- i = def->sorted_args[nb_oargs + k];
+ i = def->args_ct[nb_oargs + k].sort_index;
arg = op->args[i];
arg_ct = &def->args_ct[i];
ts = arg_temp(arg);
@@ -3695,7 +3694,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
int k2, i2;
reg = ts->reg;
for (k2 = 0 ; k2 < k ; k2++) {
- i2 = def->sorted_args[nb_oargs + k2];
+ i2 = def->args_ct[nb_oargs + k2].sort_index;
if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
reg == new_args[i2]) {
goto allocate_in_reg;
@@ -3760,7 +3759,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
/* satisfy the output constraints */
for(k = 0; k < nb_oargs; k++) {
- i = def->sorted_args[k];
+ i = def->args_ct[k].sort_index;
arg = op->args[i];
arg_ct = &def->args_ct[i];
ts = arg_temp(arg);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 04/43] tcg: Remove TCG_CT_REG
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 03/43] tcg: Move sorted_args into TCGArgConstraint.sort_index Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 05/43] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields Richard Henderson
` (38 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
This wasn't actually used for anything, really. All variable
operands must accept registers, and which are indicated by the
set in TCGArgConstraint.regs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 1 -
tcg/tcg.c | 15 ++++-----------
tcg/aarch64/tcg-target.c.inc | 3 ---
tcg/arm/tcg-target.c.inc | 3 ---
tcg/i386/tcg-target.c.inc | 11 -----------
tcg/mips/tcg-target.c.inc | 3 ---
tcg/ppc/tcg-target.c.inc | 5 -----
tcg/riscv/tcg-target.c.inc | 2 --
tcg/s390/tcg-target.c.inc | 4 ----
tcg/sparc/tcg-target.c.inc | 5 -----
tcg/tci/tcg-target.c.inc | 1 -
11 files changed, 4 insertions(+), 49 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 63955ac85b..3168315bb8 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -979,7 +979,6 @@ void tcg_dump_op_count(void);
#define TCG_CT_ALIAS 0x80
#define TCG_CT_IALIAS 0x40
#define TCG_CT_NEWREG 0x20 /* output requires a new register */
-#define TCG_CT_REG 0x01
#define TCG_CT_CONST 0x02 /* any constant of register size */
typedef struct TCGArgConstraint {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 0a04b6cbd9..a618497c94 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2194,21 +2194,14 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
/* we give more priority to constraints with less registers */
static int get_constraint_priority(const TCGOpDef *def, int k)
{
- const TCGArgConstraint *arg_ct;
+ const TCGArgConstraint *arg_ct = &def->args_ct[k];
+ int n;
- int i, n;
- arg_ct = &def->args_ct[k];
if (arg_ct->ct & TCG_CT_ALIAS) {
/* an alias is equivalent to a single register */
n = 1;
} else {
- if (!(arg_ct->ct & TCG_CT_REG))
- return 0;
- n = 0;
- for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
- if (tcg_regset_test_reg(arg_ct->regs, i))
- n++;
- }
+ n = ctpop64(arg_ct->regs);
}
return TCG_TARGET_NB_REGS - n + 1;
}
@@ -2276,7 +2269,7 @@ static void process_op_defs(TCGContext *s)
int oarg = *ct_str - '0';
tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
tcg_debug_assert(oarg < def->nb_oargs);
- tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_REG);
+ tcg_debug_assert(def->args_ct[oarg].regs != 0);
/* TCG_CT_ALIAS is for the output arguments.
The input is tagged with TCG_CT_IALIAS. */
def->args_ct[i] = def->args_ct[oarg];
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index d4b7cb4867..479a9d26be 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -128,15 +128,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch (*ct_str++) {
case 'r': /* general registers */
- ct->ct |= TCG_CT_REG;
ct->regs |= 0xffffffffu;
break;
case 'w': /* advsimd registers */
- ct->ct |= TCG_CT_REG;
ct->regs |= 0xffffffff00000000ull;
break;
case 'l': /* qemu_ld / qemu_st address, data_reg */
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffffu;
#ifdef CONFIG_SOFTMMU
/* x0 and x1 will be overwritten when reading the tlb entry,
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 978eb1dd70..62c37a954b 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -253,13 +253,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break;
case 'r':
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffff;
break;
/* qemu_ld address */
case 'l':
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffff;
#ifdef CONFIG_SOFTMMU
/* r0-r2,lr will be overwritten when reading the tlb entry,
@@ -274,7 +272,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
/* qemu_st address & data */
case 's':
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffff;
/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
and r0-r1 doing the byte swapping, so don't use these. */
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 8661ec3393..2f696074ab 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -208,42 +208,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch(*ct_str++) {
case 'a':
- ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
break;
case 'b':
- ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
break;
case 'c':
- ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
break;
case 'd':
- ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
break;
case 'S':
- ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
break;
case 'D':
- ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
break;
case 'q':
/* A register that can be used as a byte operand. */
- ct->ct |= TCG_CT_REG;
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
break;
case 'Q':
/* A register with an addressable second byte (e.g. %ah). */
- ct->ct |= TCG_CT_REG;
ct->regs = 0xf;
break;
case 'r':
/* A general register. */
- ct->ct |= TCG_CT_REG;
ct->regs |= ALL_GENERAL_REGS;
break;
case 'W':
@@ -252,13 +243,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
break;
case 'x':
/* A vector register. */
- ct->ct |= TCG_CT_REG;
ct->regs |= ALL_VECTOR_REGS;
break;
/* qemu_ld/st address constraint */
case 'L':
- ct->ct |= TCG_CT_REG;
ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index d49a02bb03..98c6a41caf 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -195,11 +195,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch(*ct_str++) {
case 'r':
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
break;
case 'L': /* qemu_ld input arg constraint */
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
@@ -209,7 +207,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
#endif
break;
case 'S': /* qemu_st constraint */
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 450b555522..7a5760bb23 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -224,19 +224,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch (*ct_str++) {
case 'A': case 'B': case 'C': case 'D':
- ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
break;
case 'r':
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
break;
case 'v':
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff00000000ull;
break;
case 'L': /* qemu_ld constraint */
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
@@ -245,7 +241,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
#endif
break;
case 'S': /* qemu_st constraint */
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 0a69839adb..d536f3ccc1 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -137,12 +137,10 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch (*ct_str++) {
case 'r':
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
break;
case 'L':
/* qemu_ld/qemu_st constraint */
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
#if defined(CONFIG_SOFTMMU)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 9cd266a2d0..c5e096449b 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -408,23 +408,19 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch (*ct_str++) {
case 'r': /* all registers */
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffff;
break;
case 'L': /* qemu_ld/st constraint */
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
break;
case 'a': /* force R2 for division */
- ct->ct |= TCG_CT_REG;
ct->regs = 0;
tcg_regset_set_reg(ct->regs, TCG_REG_R2);
break;
case 'b': /* force R3 for division */
- ct->ct |= TCG_CT_REG;
ct->regs = 0;
tcg_regset_set_reg(ct->regs, TCG_REG_R3);
break;
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index c662293fc7..44373d742b 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -325,15 +325,12 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
{
switch (*ct_str++) {
case 'r':
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
break;
case 'R':
- ct->ct |= TCG_CT_REG;
ct->regs = ALL_64;
break;
case 'A': /* qemu_ld/st address constraint */
- ct->ct |= TCG_CT_REG;
ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
reserve_helpers:
tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
@@ -341,11 +338,9 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
break;
case 's': /* qemu_st data 32-bit constraint */
- ct->ct |= TCG_CT_REG;
ct->regs = 0xffffffff;
goto reserve_helpers;
case 'S': /* qemu_st data 64-bit constraint */
- ct->ct |= TCG_CT_REG;
ct->regs = ALL_64;
goto reserve_helpers;
case 'I':
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index a7215f346f..231b9b1775 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -392,7 +392,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'r':
case 'L': /* qemu_ld constraint */
case 'S': /* qemu_st constraint */
- ct->ct |= TCG_CT_REG;
ct->regs = BIT(TCG_TARGET_NB_REGS) - 1;
break;
default:
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 05/43] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (3 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 04/43] tcg: Remove TCG_CT_REG Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 06/43] tcg: Remove TCGOpDef.used Richard Henderson
` (37 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
These are easier to set and test when they have their own fields.
Reduce the size of alias_index and sort_index to 4 bits, which is
sufficient for TCG_MAX_OP_ARGS. This leaves only the bits indicating
constants within the ct field.
Move all initialization to allocation time, rather than init
individual fields in process_op_defs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 14 +++++++-------
tcg/tcg.c | 28 ++++++++++++----------------
2 files changed, 19 insertions(+), 23 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 3168315bb8..e8629b58c8 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -976,15 +976,15 @@ int64_t tcg_cpu_exec_time(void);
void tcg_dump_info(void);
void tcg_dump_op_count(void);
-#define TCG_CT_ALIAS 0x80
-#define TCG_CT_IALIAS 0x40
-#define TCG_CT_NEWREG 0x20 /* output requires a new register */
-#define TCG_CT_CONST 0x02 /* any constant of register size */
+#define TCG_CT_CONST 1 /* any constant of register size */
typedef struct TCGArgConstraint {
- uint16_t ct;
- uint8_t alias_index;
- uint8_t sort_index;
+ unsigned ct : 16;
+ unsigned alias_index : 4;
+ unsigned sort_index : 4;
+ bool oalias : 1;
+ bool ialias : 1;
+ bool newreg : 1;
TCGRegSet regs;
} TCGArgConstraint;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index a618497c94..ad4b7fb90f 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -958,7 +958,7 @@ void tcg_context_init(TCGContext *s)
total_args += n;
}
- args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
+ args_ct = g_new0(TCGArgConstraint, total_args);
for(op = 0; op < NB_OPS; op++) {
def = &tcg_op_defs[op];
@@ -2197,7 +2197,7 @@ static int get_constraint_priority(const TCGOpDef *def, int k)
const TCGArgConstraint *arg_ct = &def->args_ct[k];
int n;
- if (arg_ct->ct & TCG_CT_ALIAS) {
+ if (arg_ct->oalias) {
/* an alias is equivalent to a single register */
n = 1;
} else {
@@ -2260,8 +2260,6 @@ static void process_op_defs(TCGContext *s)
/* Incomplete TCGTargetOpDef entry. */
tcg_debug_assert(ct_str != NULL);
- def->args_ct[i].regs = 0;
- def->args_ct[i].ct = 0;
while (*ct_str != '\0') {
switch(*ct_str) {
case '0' ... '9':
@@ -2270,18 +2268,18 @@ static void process_op_defs(TCGContext *s)
tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
tcg_debug_assert(oarg < def->nb_oargs);
tcg_debug_assert(def->args_ct[oarg].regs != 0);
- /* TCG_CT_ALIAS is for the output arguments.
- The input is tagged with TCG_CT_IALIAS. */
def->args_ct[i] = def->args_ct[oarg];
- def->args_ct[oarg].ct |= TCG_CT_ALIAS;
+ /* The output sets oalias. */
+ def->args_ct[oarg].oalias = true;
def->args_ct[oarg].alias_index = i;
- def->args_ct[i].ct |= TCG_CT_IALIAS;
+ /* The input sets ialias. */
+ def->args_ct[i].ialias = true;
def->args_ct[i].alias_index = oarg;
}
ct_str++;
break;
case '&':
- def->args_ct[i].ct |= TCG_CT_NEWREG;
+ def->args_ct[i].newreg = true;
ct_str++;
break;
case 'i':
@@ -2848,7 +2846,7 @@ static void liveness_pass_1(TCGContext *s)
set = *pset;
set &= ct->regs;
- if (ct->ct & TCG_CT_IALIAS) {
+ if (ct->ialias) {
set &= op->output_pref[ct->alias_index];
}
/* If the combination is not possible, restart. */
@@ -3665,7 +3663,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
i_preferred_regs = o_preferred_regs = 0;
- if (arg_ct->ct & TCG_CT_IALIAS) {
+ if (arg_ct->ialias) {
o_preferred_regs = op->output_pref[arg_ct->alias_index];
if (ts->fixed_reg) {
/* if fixed register, we must allocate a new register
@@ -3688,8 +3686,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
reg = ts->reg;
for (k2 = 0 ; k2 < k ; k2++) {
i2 = def->args_ct[nb_oargs + k2].sort_index;
- if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
- reg == new_args[i2]) {
+ if (def->args_ct[i2].ialias && reg == new_args[i2]) {
goto allocate_in_reg;
}
}
@@ -3760,10 +3757,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
/* ENV should not be modified. */
tcg_debug_assert(!ts->fixed_reg);
- if ((arg_ct->ct & TCG_CT_ALIAS)
- && !const_args[arg_ct->alias_index]) {
+ if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index];
- } else if (arg_ct->ct & TCG_CT_NEWREG) {
+ } else if (arg_ct->newreg) {
reg = tcg_reg_alloc(s, arg_ct->regs,
i_allocated_regs | o_allocated_regs,
op->output_pref[k], ts->indirect_base);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 06/43] tcg: Remove TCGOpDef.used
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (4 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 05/43] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 17:45 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 07/43] tcg/i386: Fix dupi for avx2 32-bit hosts Richard Henderson
` (36 subsequent siblings)
42 siblings, 1 reply; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
The last user of this field disappeared in f69d277ece4.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index e8629b58c8..8804a8c4a2 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -1015,9 +1015,6 @@ typedef struct TCGOpDef {
uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
uint8_t flags;
TCGArgConstraint *args_ct;
-#if defined(CONFIG_DEBUG_TCG)
- int used;
-#endif
} TCGOpDef;
extern TCGOpDef tcg_op_defs[];
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 07/43] tcg/i386: Fix dupi for avx2 32-bit hosts
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (5 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 06/43] tcg: Remove TCGOpDef.used Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 08/43] tcg: Fix generation of dupi_vec for 32-bit host Richard Henderson
` (35 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-stable
The previous change wrongly stated that 32-bit avx2 should have
used VPBROADCASTW. But that's a 16-bit broadcast and we want a
32-bit broadcast.
Fixes: 7b60ef3264e
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 2f696074ab..d8797ed398 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -958,7 +958,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
} else {
if (have_avx2) {
- tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTW + vex_l, ret);
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
} else {
tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 08/43] tcg: Fix generation of dupi_vec for 32-bit host
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (6 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 07/43] tcg/i386: Fix dupi for avx2 32-bit hosts Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 09/43] tcg/optimize: Fold dup2_vec Richard Henderson
` (34 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-stable
The definition of INDEX_op_dupi_vec is that it operates on
units of tcg_target_ulong -- in this case 32 bits. It does
not work to use this for a uint64_t value that happens to be
small enough to fit in tcg_target_ulong.
Fixes: d2fd745fe8b
Fixes: db432672dc5
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op-vec.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index ed6fb55fe1..cdbf11c573 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -252,10 +252,10 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
{
- if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
- do_dupi_vec(r, MO_32, a);
- } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
+ if (TCG_TARGET_REG_BITS == 64) {
do_dupi_vec(r, MO_64, a);
+ } else if (a == dup_const(MO_32, a)) {
+ do_dupi_vec(r, MO_32, a);
} else {
TCGv_i64 c = tcg_const_i64(a);
tcg_gen_dup_i64_vec(MO_64, r, c);
@@ -280,7 +280,11 @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
{
- do_dupi_vec(r, MO_REG, dup_const(vece, a));
+ if (vece == MO_64) {
+ tcg_gen_dup64i_vec(r, a);
+ } else {
+ do_dupi_vec(r, MO_REG, dup_const(vece, a));
+ }
}
void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 09/43] tcg/optimize: Fold dup2_vec
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (7 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 08/43] tcg: Fix generation of dupi_vec for 32-bit host Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec Richard Henderson
` (33 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
When the two arguments are identical, this can be reduced to
dup_vec or to mov_vec from a tcg_constant_vec.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 53aa8e5329..220f4601d5 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1109,6 +1109,21 @@ void tcg_optimize(TCGContext *s)
}
goto do_default;
+ case INDEX_op_dup2_vec:
+ assert(TCG_TARGET_REG_BITS == 32);
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
+ tmp = arg_info(op->args[1])->val;
+ if (tmp == arg_info(op->args[2])->val) {
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ break;
+ }
+ } else if (args_are_copies(op->args[1], op->args[2])) {
+ op->opc = INDEX_op_dup_vec;
+ TCGOP_VECE(op) = MO_32;
+ nb_iargs = 1;
+ }
+ goto do_default;
+
CASE_OP_32_64(not):
CASE_OP_32_64(neg):
CASE_OP_32_64(ext8s):
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (8 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 09/43] tcg/optimize: Fold dup2_vec Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 17:47 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 11/43] tcg: Use tcg_out_dupi_vec from temp_load Richard Henderson
` (32 subsequent siblings)
42 siblings, 1 reply; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
The cmp_vec opcode is mandatory; this symbol is unused.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 1 -
tcg/i386/tcg-target.h | 1 -
tcg/ppc/tcg-target.h | 1 -
3 files changed, 3 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 9bc2a5ecbe..663dd0b95e 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -139,7 +139,6 @@ typedef enum {
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1
-#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 99ac1e3958..1f6dd8f45d 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -189,7 +189,6 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec have_avx2
-#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index aee38157a2..be10363956 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -169,7 +169,6 @@ extern bool have_vsx;
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1
-#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 11/43] tcg: Use tcg_out_dupi_vec from temp_load
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (9 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 12/43] tcg: Increase tcg_out_dupi_vec immediate to int64_t Richard Henderson
` (31 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
Having dupi pass though movi is confusing and arguably wrong.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 6 +++-
tcg/aarch64/tcg-target.c.inc | 7 ----
tcg/i386/tcg-target.c.inc | 63 ++++++++++++++++++++++++------------
tcg/ppc/tcg-target.c.inc | 6 ----
4 files changed, 47 insertions(+), 35 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index ad4b7fb90f..84bdcc6537 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3305,7 +3305,11 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs,
case TEMP_VAL_CONST:
reg = tcg_reg_alloc(s, desired_regs, allocated_regs,
preferred_regs, ts->indirect_base);
- tcg_out_movi(s, ts->type, reg, ts->val);
+ if (ts->type <= TCG_TYPE_I64) {
+ tcg_out_movi(s, ts->type, reg, ts->val);
+ } else {
+ tcg_out_dupi_vec(s, ts->type, reg, ts->val);
+ }
ts->mem_coherent = 0;
break;
case TEMP_VAL_MEM:
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 479a9d26be..72c4d25fdb 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -1007,13 +1007,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
case TCG_TYPE_I64:
tcg_debug_assert(rd < 32);
break;
-
- case TCG_TYPE_V64:
- case TCG_TYPE_V128:
- tcg_debug_assert(rd >= 32);
- tcg_out_dupi_vec(s, type, rd, value);
- return;
-
default:
g_assert_not_reached();
}
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index d8797ed398..e2852cbb09 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -966,30 +966,32 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
}
}
-static void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
+static void tcg_out_movi_vec(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
+{
+ if (arg == 0) {
+ tcg_out_vex_modrm(s, OPC_PXOR, ret, ret, ret);
+ return;
+ }
+ if (arg == -1) {
+ tcg_out_vex_modrm(s, OPC_PCMPEQB, ret, ret, ret);
+ return;
+ }
+
+ int rexw = (type == TCG_TYPE_I32 ? 0 : P_REXW);
+ tcg_out_vex_modrm_pool(s, OPC_MOVD_VyEy + rexw, ret);
+ if (TCG_TARGET_REG_BITS == 64) {
+ new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
+ } else {
+ new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
+ }
+}
+
+static void tcg_out_movi_int(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
{
tcg_target_long diff;
- switch (type) {
- case TCG_TYPE_I32:
-#if TCG_TARGET_REG_BITS == 64
- case TCG_TYPE_I64:
-#endif
- if (ret < 16) {
- break;
- }
- /* fallthru */
- case TCG_TYPE_V64:
- case TCG_TYPE_V128:
- case TCG_TYPE_V256:
- tcg_debug_assert(ret >= 16);
- tcg_out_dupi_vec(s, type, ret, arg);
- return;
- default:
- g_assert_not_reached();
- }
-
if (arg == 0) {
tgen_arithr(s, ARITH_XOR, ret, ret);
return;
@@ -1018,6 +1020,25 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
tcg_out64(s, arg);
}
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
+{
+ switch (type) {
+ case TCG_TYPE_I32:
+#if TCG_TARGET_REG_BITS == 64
+ case TCG_TYPE_I64:
+#endif
+ if (ret < 16) {
+ tcg_out_movi_int(s, type, ret, arg);
+ } else {
+ tcg_out_movi_vec(s, type, ret, arg);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)
{
if (val == (int8_t)val) {
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 7a5760bb23..bc6fb09adb 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -983,12 +983,6 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
tcg_out_movi_int(s, type, ret, arg, false);
break;
- case TCG_TYPE_V64:
- case TCG_TYPE_V128:
- tcg_debug_assert(ret >= TCG_REG_V0);
- tcg_out_dupi_vec(s, type, ret, arg);
- break;
-
default:
g_assert_not_reached();
}
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 12/43] tcg: Increase tcg_out_dupi_vec immediate to int64_t
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (10 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 11/43] tcg: Use tcg_out_dupi_vec from temp_load Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 13/43] tcg: Consolidate 3 bits into enum TCGTempKind Richard Henderson
` (30 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
While we don't store more than tcg_target_long in TCGTemp,
we shouldn't be limited to that for code generation. We will
be able to use this for INDEX_op_dup2_vec with 2 constants.
Also pass along the minimal vece that may be said to apply
to the constant. This allows some simplification in the
various backends.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 31 +++++++++++++++++++++++++-----
tcg/aarch64/tcg-target.c.inc | 12 ++++++------
tcg/i386/tcg-target.c.inc | 22 ++++++++++++---------
tcg/ppc/tcg-target.c.inc | 37 +++++++++++++++++++++++-------------
4 files changed, 69 insertions(+), 33 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 84bdcc6537..6474a695f2 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -116,8 +116,8 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg dst, TCGReg src);
static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg dst, TCGReg base, intptr_t offset);
-static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
- TCGReg dst, tcg_target_long arg);
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg dst, int64_t arg);
static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, unsigned vecl,
unsigned vece, const TCGArg *args,
const int *const_args);
@@ -132,8 +132,8 @@ static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
{
g_assert_not_reached();
}
-static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type,
- TCGReg dst, tcg_target_long arg)
+static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg dst, int64_t arg)
{
g_assert_not_reached();
}
@@ -3308,7 +3308,28 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs,
if (ts->type <= TCG_TYPE_I64) {
tcg_out_movi(s, ts->type, reg, ts->val);
} else {
- tcg_out_dupi_vec(s, ts->type, reg, ts->val);
+ uint64_t val = ts->val;
+ MemOp vece = MO_64;
+
+ /*
+ * Find the minimal vector element that matches the constant.
+ * The targets will, in general, have to do this search anyway,
+ * do this generically.
+ */
+ if (TCG_TARGET_REG_BITS == 32) {
+ val = dup_const(MO_32, val);
+ vece = MO_32;
+ }
+ if (val == dup_const(MO_8, val)) {
+ vece = MO_8;
+ } else if (val == dup_const(MO_16, val)) {
+ vece = MO_16;
+ } else if (TCG_TARGET_REG_BITS == 64 &&
+ val == dup_const(MO_32, val)) {
+ vece = MO_32;
+ }
+
+ tcg_out_dupi_vec(s, ts->type, vece, reg, ts->val);
}
ts->mem_coherent = 0;
break;
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 72c4d25fdb..5692607087 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -853,14 +853,14 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
}
-static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
- TCGReg rd, tcg_target_long v64)
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg rd, int64_t v64)
{
bool q = type == TCG_TYPE_V128;
int cmode, imm8, i;
/* Test all bytes equal first. */
- if (v64 == dup_const(MO_8, v64)) {
+ if (vece == MO_8) {
imm8 = (uint8_t)v64;
tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0xe, imm8);
return;
@@ -887,7 +887,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
* cannot find an expansion there's no point checking a larger
* width because we already know by replication it cannot match.
*/
- if (v64 == dup_const(MO_16, v64)) {
+ if (vece == MO_16) {
uint16_t v16 = v64;
if (is_shimm16(v16, &cmode, &imm8)) {
@@ -906,7 +906,7 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
tcg_out_insn(s, 3606, MOVI, q, rd, 0, 0x8, v16 & 0xff);
tcg_out_insn(s, 3606, ORR, q, rd, 0, 0xa, v16 >> 8);
return;
- } else if (v64 == dup_const(MO_32, v64)) {
+ } else if (vece == MO_32) {
uint32_t v32 = v64;
uint32_t n32 = ~v32;
@@ -2430,7 +2430,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_insn_3617(s, insn, is_q, vece, a0, a1);
break;
}
- tcg_out_dupi_vec(s, type, TCG_VEC_TMP, 0);
+ tcg_out_dupi_vec(s, type, MO_8, TCG_VEC_TMP, 0);
a2 = TCG_VEC_TMP;
}
insn = cmp_insn[cond];
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index e2852cbb09..6b7cbaa47a 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -933,8 +933,8 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
return true;
}
-static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
- TCGReg ret, tcg_target_long arg)
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg ret, int64_t arg)
{
int vex_l = (type == TCG_TYPE_V256 ? P_VEXL : 0);
@@ -947,7 +947,14 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
return;
}
- if (TCG_TARGET_REG_BITS == 64) {
+ if (TCG_TARGET_REG_BITS == 32 && vece < MO_64) {
+ if (have_avx2) {
+ tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
+ } else {
+ tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
+ }
+ new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
+ } else {
if (type == TCG_TYPE_V64) {
tcg_out_vex_modrm_pool(s, OPC_MOVQ_VqWq, ret);
} else if (have_avx2) {
@@ -955,14 +962,11 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type,
} else {
tcg_out_vex_modrm_pool(s, OPC_MOVDDUP, ret);
}
- new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
- } else {
- if (have_avx2) {
- tcg_out_vex_modrm_pool(s, OPC_VPBROADCASTD + vex_l, ret);
+ if (TCG_TARGET_REG_BITS == 64) {
+ new_pool_label(s, arg, R_386_PC32, s->code_ptr - 4, -4);
} else {
- tcg_out_vex_modrm_pool(s, OPC_VBROADCASTSS, ret);
+ new_pool_l2(s, R_386_32, s->code_ptr - 4, 0, arg, arg >> 32);
}
- new_pool_label(s, arg, R_386_32, s->code_ptr - 4, 0);
}
}
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index bc6fb09adb..ff56f1971f 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -908,31 +908,41 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
}
}
-static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
- tcg_target_long val)
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg ret, int64_t val)
{
uint32_t load_insn;
int rel, low;
intptr_t add;
- low = (int8_t)val;
- if (low >= -16 && low < 16) {
- if (val == (tcg_target_long)dup_const(MO_8, low)) {
+ switch (vece) {
+ case MO_8:
+ low = (int8_t)val;
+ if (low >= -16 && low < 16) {
tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16));
return;
}
- if (val == (tcg_target_long)dup_const(MO_16, low)) {
+ if (have_isa_3_00) {
+ tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11));
+ return;
+ }
+ break;
+
+ case MO_16:
+ low = (int16_t)val;
+ if (low >= -16 && low < 16) {
tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16));
return;
}
- if (val == (tcg_target_long)dup_const(MO_32, low)) {
+ break;
+
+ case MO_32:
+ low = (int32_t)val;
+ if (low >= -16 && low < 16) {
tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16));
return;
}
- }
- if (have_isa_3_00 && val == (tcg_target_long)dup_const(MO_8, val)) {
- tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11));
- return;
+ break;
}
/*
@@ -952,14 +962,15 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
if (TCG_TARGET_REG_BITS == 64) {
new_pool_label(s, val, rel, s->code_ptr, add);
} else {
- new_pool_l2(s, rel, s->code_ptr, add, val, val);
+ new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val);
}
} else {
load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
if (TCG_TARGET_REG_BITS == 64) {
new_pool_l2(s, rel, s->code_ptr, add, val, val);
} else {
- new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
+ new_pool_l4(s, rel, s->code_ptr, add,
+ val >> 32, val, val >> 32, val);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 13/43] tcg: Consolidate 3 bits into enum TCGTempKind
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (11 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 12/43] tcg: Increase tcg_out_dupi_vec immediate to int64_t Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 17:52 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 14/43] tcg: Add temp_readonly Richard Henderson
` (29 subsequent siblings)
42 siblings, 1 reply; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
The temp_fixed, temp_global, temp_local bits are all related.
Combine them into a single enumeration.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 20 +++++---
tcg/optimize.c | 8 +--
tcg/tcg.c | 122 ++++++++++++++++++++++++++++------------------
3 files changed, 90 insertions(+), 60 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 8804a8c4a2..f157092b51 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -483,23 +483,27 @@ typedef enum TCGTempVal {
TEMP_VAL_CONST,
} TCGTempVal;
+typedef enum TCGTempKind {
+ /* Temp is dead at the end of all basic blocks. */
+ TEMP_NORMAL,
+ /* Temp is saved across basic blocks but dead at the end of TBs. */
+ TEMP_LOCAL,
+ /* Temp is saved across both basic blocks and translation blocks. */
+ TEMP_GLOBAL,
+ /* Temp is in a fixed register. */
+ TEMP_FIXED,
+} TCGTempKind;
+
typedef struct TCGTemp {
TCGReg reg:8;
TCGTempVal val_type:8;
TCGType base_type:8;
TCGType type:8;
- unsigned int fixed_reg:1;
+ TCGTempKind kind:3;
unsigned int indirect_reg:1;
unsigned int indirect_base:1;
unsigned int mem_coherent:1;
unsigned int mem_allocated:1;
- /* If true, the temp is saved across both basic blocks and
- translation blocks. */
- unsigned int temp_global:1;
- /* If true, the temp is saved across basic blocks but dead
- at the end of translation blocks. If false, the temp is
- dead at the end of basic blocks. */
- unsigned int temp_local:1;
unsigned int temp_allocated:1;
tcg_target_long val;
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 220f4601d5..3cffd941bd 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -116,21 +116,21 @@ static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
TCGTemp *i;
/* If this is already a global, we can't do better. */
- if (ts->temp_global) {
+ if (ts->kind >= TEMP_GLOBAL) {
return ts;
}
/* Search for a global first. */
for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
- if (i->temp_global) {
+ if (i->kind >= TEMP_GLOBAL) {
return i;
}
}
/* If it is a temp, search for a temp local. */
- if (!ts->temp_local) {
+ if (ts->kind == TEMP_NORMAL) {
for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
- if (ts->temp_local) {
+ if (i->kind >= TEMP_LOCAL) {
return i;
}
}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 6474a695f2..67e122527b 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1160,7 +1160,7 @@ static inline TCGTemp *tcg_global_alloc(TCGContext *s)
tcg_debug_assert(s->nb_globals == s->nb_temps);
s->nb_globals++;
ts = tcg_temp_alloc(s);
- ts->temp_global = 1;
+ ts->kind = TEMP_GLOBAL;
return ts;
}
@@ -1177,7 +1177,7 @@ static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type,
ts = tcg_global_alloc(s);
ts->base_type = type;
ts->type = type;
- ts->fixed_reg = 1;
+ ts->kind = TEMP_FIXED;
ts->reg = reg;
ts->name = name;
tcg_regset_set_reg(s->reserved_regs, reg);
@@ -1204,7 +1204,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
bigendian = 1;
#endif
- if (!base_ts->fixed_reg) {
+ if (base_ts->kind != TEMP_FIXED) {
/* We do not support double-indirect registers. */
tcg_debug_assert(!base_ts->indirect_reg);
base_ts->indirect_base = 1;
@@ -1252,6 +1252,7 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local)
{
TCGContext *s = tcg_ctx;
+ TCGTempKind kind = temp_local ? TEMP_LOCAL : TEMP_NORMAL;
TCGTemp *ts;
int idx, k;
@@ -1264,7 +1265,7 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local)
ts = &s->temps[idx];
ts->temp_allocated = 1;
tcg_debug_assert(ts->base_type == type);
- tcg_debug_assert(ts->temp_local == temp_local);
+ tcg_debug_assert(ts->kind == kind);
} else {
ts = tcg_temp_alloc(s);
if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) {
@@ -1273,18 +1274,18 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local)
ts->base_type = type;
ts->type = TCG_TYPE_I32;
ts->temp_allocated = 1;
- ts->temp_local = temp_local;
+ ts->kind = kind;
tcg_debug_assert(ts2 == ts + 1);
ts2->base_type = TCG_TYPE_I64;
ts2->type = TCG_TYPE_I32;
ts2->temp_allocated = 1;
- ts2->temp_local = temp_local;
+ ts2->kind = kind;
} else {
ts->base_type = type;
ts->type = type;
ts->temp_allocated = 1;
- ts->temp_local = temp_local;
+ ts->kind = kind;
}
}
@@ -1341,12 +1342,12 @@ void tcg_temp_free_internal(TCGTemp *ts)
}
#endif
- tcg_debug_assert(ts->temp_global == 0);
+ tcg_debug_assert(ts->kind < TEMP_GLOBAL);
tcg_debug_assert(ts->temp_allocated != 0);
ts->temp_allocated = 0;
idx = temp_idx(ts);
- k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0);
+ k = ts->base_type + (ts->kind == TEMP_NORMAL ? 0 : TCG_TYPE_COUNT);
set_bit(idx, s->free_temps[k].l);
}
@@ -1876,17 +1877,27 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args)
static void tcg_reg_alloc_start(TCGContext *s)
{
int i, n;
- TCGTemp *ts;
- for (i = 0, n = s->nb_globals; i < n; i++) {
- ts = &s->temps[i];
- ts->val_type = (ts->fixed_reg ? TEMP_VAL_REG : TEMP_VAL_MEM);
- }
- for (n = s->nb_temps; i < n; i++) {
- ts = &s->temps[i];
- ts->val_type = (ts->temp_local ? TEMP_VAL_MEM : TEMP_VAL_DEAD);
- ts->mem_allocated = 0;
- ts->fixed_reg = 0;
+ for (i = 0, n = s->nb_temps; i < n; i++) {
+ TCGTemp *ts = &s->temps[i];
+ TCGTempVal val = TEMP_VAL_MEM;
+
+ switch (ts->kind) {
+ case TEMP_FIXED:
+ val = TEMP_VAL_REG;
+ break;
+ case TEMP_GLOBAL:
+ break;
+ case TEMP_NORMAL:
+ val = TEMP_VAL_DEAD;
+ /* fall through */
+ case TEMP_LOCAL:
+ ts->mem_allocated = 0;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ ts->val_type = val;
}
memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp));
@@ -1897,12 +1908,17 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size,
{
int idx = temp_idx(ts);
- if (ts->temp_global) {
+ switch (ts->kind) {
+ case TEMP_FIXED:
+ case TEMP_GLOBAL:
pstrcpy(buf, buf_size, ts->name);
- } else if (ts->temp_local) {
+ break;
+ case TEMP_LOCAL:
snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
- } else {
+ break;
+ case TEMP_NORMAL:
snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
+ break;
}
return buf;
}
@@ -2492,15 +2508,24 @@ static void la_bb_end(TCGContext *s, int ng, int nt)
{
int i;
- for (i = 0; i < ng; ++i) {
- s->temps[i].state = TS_DEAD | TS_MEM;
- la_reset_pref(&s->temps[i]);
- }
- for (i = ng; i < nt; ++i) {
- s->temps[i].state = (s->temps[i].temp_local
- ? TS_DEAD | TS_MEM
- : TS_DEAD);
- la_reset_pref(&s->temps[i]);
+ for (i = 0; i < nt; ++i) {
+ TCGTemp *ts = &s->temps[i];
+ int state;
+
+ switch (ts->kind) {
+ case TEMP_FIXED:
+ case TEMP_GLOBAL:
+ case TEMP_LOCAL:
+ state = TS_DEAD | TS_MEM;
+ break;
+ case TEMP_NORMAL:
+ state = TS_DEAD;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ ts->state = state;
+ la_reset_pref(ts);
}
}
@@ -3109,7 +3134,8 @@ static void check_regs(TCGContext *s)
}
for (k = 0; k < s->nb_temps; k++) {
ts = &s->temps[k];
- if (ts->val_type == TEMP_VAL_REG && !ts->fixed_reg
+ if (ts->val_type == TEMP_VAL_REG
+ && ts->kind != TEMP_FIXED
&& s->reg_to_temp[ts->reg] != ts) {
printf("Inconsistency for temp %s:\n",
tcg_get_arg_str_ptr(s, buf, sizeof(buf), ts));
@@ -3146,15 +3172,14 @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet);
mark it free; otherwise mark it dead. */
static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead)
{
- if (ts->fixed_reg) {
+ if (ts->kind == TEMP_FIXED) {
return;
}
if (ts->val_type == TEMP_VAL_REG) {
s->reg_to_temp[ts->reg] = NULL;
}
ts->val_type = (free_or_dead < 0
- || ts->temp_local
- || ts->temp_global
+ || ts->kind != TEMP_NORMAL
? TEMP_VAL_MEM : TEMP_VAL_DEAD);
}
@@ -3171,7 +3196,7 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts)
static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs,
TCGRegSet preferred_regs, int free_or_dead)
{
- if (ts->fixed_reg) {
+ if (ts->kind == TEMP_FIXED) {
return;
}
if (!ts->mem_coherent) {
@@ -3354,7 +3379,8 @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs)
{
/* The liveness analysis already ensures that globals are back
in memory. Keep an tcg_debug_assert for safety. */
- tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || ts->fixed_reg);
+ tcg_debug_assert(ts->val_type == TEMP_VAL_MEM
+ || ts->kind == TEMP_FIXED);
}
/* save globals to their canonical location and assume they can be
@@ -3379,7 +3405,7 @@ static void sync_globals(TCGContext *s, TCGRegSet allocated_regs)
for (i = 0, n = s->nb_globals; i < n; i++) {
TCGTemp *ts = &s->temps[i];
tcg_debug_assert(ts->val_type != TEMP_VAL_REG
- || ts->fixed_reg
+ || ts->kind == TEMP_FIXED
|| ts->mem_coherent);
}
}
@@ -3392,7 +3418,7 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
for (i = s->nb_globals; i < s->nb_temps; i++) {
TCGTemp *ts = &s->temps[i];
- if (ts->temp_local) {
+ if (ts->kind == TEMP_LOCAL) {
temp_save(s, ts, allocated_regs);
} else {
/* The liveness analysis already ensures that temps are dead.
@@ -3412,7 +3438,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
TCGRegSet preferred_regs)
{
/* ENV should not be modified. */
- tcg_debug_assert(!ots->fixed_reg);
+ tcg_debug_assert(ots->kind != TEMP_FIXED);
/* The movi is not explicitly generated here. */
if (ots->val_type == TEMP_VAL_REG) {
@@ -3452,7 +3478,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
ts = arg_temp(op->args[1]);
/* ENV should not be modified. */
- tcg_debug_assert(!ots->fixed_reg);
+ tcg_debug_assert(ots->kind != TEMP_FIXED);
/* Note that otype != itype for no-op truncation. */
otype = ots->type;
@@ -3491,7 +3517,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
}
temp_dead(s, ots);
} else {
- if (IS_DEAD_ARG(1) && !ts->fixed_reg) {
+ if (IS_DEAD_ARG(1) && ts->kind != TEMP_FIXED) {
/* the mov can be suppressed */
if (ots->val_type == TEMP_VAL_REG) {
s->reg_to_temp[ots->reg] = NULL;
@@ -3513,7 +3539,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
* Store the source register into the destination slot
* and leave the destination temp as TEMP_VAL_MEM.
*/
- assert(!ots->fixed_reg);
+ assert(ots->kind != TEMP_FIXED);
if (!ts->mem_allocated) {
temp_allocate_frame(s, ots);
}
@@ -3550,7 +3576,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
its = arg_temp(op->args[1]);
/* ENV should not be modified. */
- tcg_debug_assert(!ots->fixed_reg);
+ tcg_debug_assert(ots->kind != TEMP_FIXED);
itype = its->type;
vece = TCGOP_VECE(op);
@@ -3690,7 +3716,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
i_preferred_regs = o_preferred_regs = 0;
if (arg_ct->ialias) {
o_preferred_regs = op->output_pref[arg_ct->alias_index];
- if (ts->fixed_reg) {
+ if (ts->kind == TEMP_FIXED) {
/* if fixed register, we must allocate a new register
if the alias is not the same register */
if (arg != op->args[arg_ct->alias_index]) {
@@ -3780,7 +3806,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
ts = arg_temp(arg);
/* ENV should not be modified. */
- tcg_debug_assert(!ts->fixed_reg);
+ tcg_debug_assert(ts->kind != TEMP_FIXED);
if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index];
@@ -3821,7 +3847,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
ts = arg_temp(op->args[i]);
/* ENV should not be modified. */
- tcg_debug_assert(!ts->fixed_reg);
+ tcg_debug_assert(ts->kind != TEMP_FIXED);
if (NEED_SYNC_ARG(i)) {
temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i));
@@ -3953,7 +3979,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
ts = arg_temp(arg);
/* ENV should not be modified. */
- tcg_debug_assert(!ts->fixed_reg);
+ tcg_debug_assert(ts->kind != TEMP_FIXED);
reg = tcg_target_call_oarg_regs[i];
tcg_debug_assert(s->reg_to_temp[reg] == NULL);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 14/43] tcg: Add temp_readonly
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (12 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 13/43] tcg: Consolidate 3 bits into enum TCGTempKind Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 15/43] tcg: Expand TCGTemp.val to 64-bits Richard Henderson
` (28 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée, Philippe Mathieu-Daudé
In most, but not all, places that we check for TEMP_FIXED,
we are really testing that we do not modify the temporary.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 5 +++++
tcg/tcg.c | 21 ++++++++++-----------
2 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index f157092b51..44ca8845cf 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -681,6 +681,11 @@ struct TCGContext {
target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
};
+static inline bool temp_readonly(TCGTemp *ts)
+{
+ return ts->kind == TEMP_FIXED;
+}
+
extern TCGContext tcg_init_ctx;
extern __thread TCGContext *tcg_ctx;
extern TCGv_env cpu_env;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 67e122527b..577bfec202 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3172,7 +3172,7 @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet);
mark it free; otherwise mark it dead. */
static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead)
{
- if (ts->kind == TEMP_FIXED) {
+ if (temp_readonly(ts)) {
return;
}
if (ts->val_type == TEMP_VAL_REG) {
@@ -3196,7 +3196,7 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts)
static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs,
TCGRegSet preferred_regs, int free_or_dead)
{
- if (ts->kind == TEMP_FIXED) {
+ if (temp_readonly(ts)) {
return;
}
if (!ts->mem_coherent) {
@@ -3379,8 +3379,7 @@ static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs)
{
/* The liveness analysis already ensures that globals are back
in memory. Keep an tcg_debug_assert for safety. */
- tcg_debug_assert(ts->val_type == TEMP_VAL_MEM
- || ts->kind == TEMP_FIXED);
+ tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || temp_readonly(ts));
}
/* save globals to their canonical location and assume they can be
@@ -3438,7 +3437,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
TCGRegSet preferred_regs)
{
/* ENV should not be modified. */
- tcg_debug_assert(ots->kind != TEMP_FIXED);
+ tcg_debug_assert(!temp_readonly(ots));
/* The movi is not explicitly generated here. */
if (ots->val_type == TEMP_VAL_REG) {
@@ -3478,7 +3477,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
ts = arg_temp(op->args[1]);
/* ENV should not be modified. */
- tcg_debug_assert(ots->kind != TEMP_FIXED);
+ tcg_debug_assert(!temp_readonly(ots));
/* Note that otype != itype for no-op truncation. */
otype = ots->type;
@@ -3539,7 +3538,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op)
* Store the source register into the destination slot
* and leave the destination temp as TEMP_VAL_MEM.
*/
- assert(ots->kind != TEMP_FIXED);
+ assert(!temp_readonly(ots));
if (!ts->mem_allocated) {
temp_allocate_frame(s, ots);
}
@@ -3576,7 +3575,7 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
its = arg_temp(op->args[1]);
/* ENV should not be modified. */
- tcg_debug_assert(ots->kind != TEMP_FIXED);
+ tcg_debug_assert(!temp_readonly(ots));
itype = its->type;
vece = TCGOP_VECE(op);
@@ -3806,7 +3805,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
ts = arg_temp(arg);
/* ENV should not be modified. */
- tcg_debug_assert(ts->kind != TEMP_FIXED);
+ tcg_debug_assert(!temp_readonly(ts));
if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index];
@@ -3847,7 +3846,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
ts = arg_temp(op->args[i]);
/* ENV should not be modified. */
- tcg_debug_assert(ts->kind != TEMP_FIXED);
+ tcg_debug_assert(!temp_readonly(ts));
if (NEED_SYNC_ARG(i)) {
temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i));
@@ -3979,7 +3978,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
ts = arg_temp(arg);
/* ENV should not be modified. */
- tcg_debug_assert(ts->kind != TEMP_FIXED);
+ tcg_debug_assert(!temp_readonly(ts));
reg = tcg_target_call_oarg_regs[i];
tcg_debug_assert(s->reg_to_temp[reg] == NULL);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 15/43] tcg: Expand TCGTemp.val to 64-bits
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (13 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 14/43] tcg: Add temp_readonly Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 16/43] tcg: Rename struct tcg_temp_info to TempOptInfo Richard Henderson
` (27 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
This will reduce the differences between 32-bit and 64-bit hosts,
allowing full 64-bit constants to be created with the same interface.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 2 +-
tcg/tcg.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 44ca8845cf..f3eca6feb0 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -506,7 +506,7 @@ typedef struct TCGTemp {
unsigned int mem_allocated:1;
unsigned int temp_allocated:1;
- tcg_target_long val;
+ int64_t val;
struct TCGTemp *mem_base;
intptr_t mem_offset;
const char *name;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 577bfec202..1650c5a9db 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3094,7 +3094,7 @@ static void dump_regs(TCGContext *s)
tcg_target_reg_names[ts->mem_base->reg]);
break;
case TEMP_VAL_CONST:
- printf("$0x%" TCG_PRIlx, ts->val);
+ printf("$0x%" PRIx64, ts->val);
break;
case TEMP_VAL_DEAD:
printf("D");
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 16/43] tcg: Rename struct tcg_temp_info to TempOptInfo
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (14 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 15/43] tcg: Expand TCGTemp.val to 64-bits Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 17/43] tcg: Expand TempOptInfo to 64-bits Richard Henderson
` (26 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée, Philippe Mathieu-Daudé
Fix this name vs our coding style.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 3cffd941bd..81faf7cf10 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -35,20 +35,20 @@
glue(glue(case INDEX_op_, x), _i64): \
glue(glue(case INDEX_op_, x), _vec)
-struct tcg_temp_info {
+typedef struct TempOptInfo {
bool is_const;
TCGTemp *prev_copy;
TCGTemp *next_copy;
tcg_target_ulong val;
tcg_target_ulong mask;
-};
+} TempOptInfo;
-static inline struct tcg_temp_info *ts_info(TCGTemp *ts)
+static inline TempOptInfo *ts_info(TCGTemp *ts)
{
return ts->state_ptr;
}
-static inline struct tcg_temp_info *arg_info(TCGArg arg)
+static inline TempOptInfo *arg_info(TCGArg arg)
{
return ts_info(arg_temp(arg));
}
@@ -71,9 +71,9 @@ static inline bool ts_is_copy(TCGTemp *ts)
/* Reset TEMP's state, possibly removing the temp for the list of copies. */
static void reset_ts(TCGTemp *ts)
{
- struct tcg_temp_info *ti = ts_info(ts);
- struct tcg_temp_info *pi = ts_info(ti->prev_copy);
- struct tcg_temp_info *ni = ts_info(ti->next_copy);
+ TempOptInfo *ti = ts_info(ts);
+ TempOptInfo *pi = ts_info(ti->prev_copy);
+ TempOptInfo *ni = ts_info(ti->next_copy);
ni->prev_copy = ti->prev_copy;
pi->next_copy = ti->next_copy;
@@ -89,12 +89,12 @@ static void reset_temp(TCGArg arg)
}
/* Initialize and activate a temporary. */
-static void init_ts_info(struct tcg_temp_info *infos,
+static void init_ts_info(TempOptInfo *infos,
TCGTempSet *temps_used, TCGTemp *ts)
{
size_t idx = temp_idx(ts);
if (!test_bit(idx, temps_used->l)) {
- struct tcg_temp_info *ti = &infos[idx];
+ TempOptInfo *ti = &infos[idx];
ts->state_ptr = ti;
ti->next_copy = ts;
@@ -105,7 +105,7 @@ static void init_ts_info(struct tcg_temp_info *infos,
}
}
-static void init_arg_info(struct tcg_temp_info *infos,
+static void init_arg_info(TempOptInfo *infos,
TCGTempSet *temps_used, TCGArg arg)
{
init_ts_info(infos, temps_used, arg_temp(arg));
@@ -171,7 +171,7 @@ static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val)
const TCGOpDef *def;
TCGOpcode new_op;
tcg_target_ulong mask;
- struct tcg_temp_info *di = arg_info(dst);
+ TempOptInfo *di = arg_info(dst);
def = &tcg_op_defs[op->opc];
if (def->flags & TCG_OPF_VECTOR) {
@@ -202,8 +202,8 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
TCGTemp *dst_ts = arg_temp(dst);
TCGTemp *src_ts = arg_temp(src);
const TCGOpDef *def;
- struct tcg_temp_info *di;
- struct tcg_temp_info *si;
+ TempOptInfo *di;
+ TempOptInfo *si;
tcg_target_ulong mask;
TCGOpcode new_op;
@@ -236,7 +236,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
di->mask = mask;
if (src_ts->type == dst_ts->type) {
- struct tcg_temp_info *ni = ts_info(si->next_copy);
+ TempOptInfo *ni = ts_info(si->next_copy);
di->next_copy = si->next_copy;
di->prev_copy = src_ts;
@@ -599,7 +599,7 @@ void tcg_optimize(TCGContext *s)
{
int nb_temps, nb_globals;
TCGOp *op, *op_next, *prev_mb = NULL;
- struct tcg_temp_info *infos;
+ TempOptInfo *infos;
TCGTempSet temps_used;
/* Array VALS has an element for each temp.
@@ -610,7 +610,7 @@ void tcg_optimize(TCGContext *s)
nb_temps = s->nb_temps;
nb_globals = s->nb_globals;
bitmap_zero(temps_used.l, nb_temps);
- infos = tcg_malloc(sizeof(struct tcg_temp_info) * nb_temps);
+ infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps);
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
tcg_target_ulong mask, partmask, affected;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 17/43] tcg: Expand TempOptInfo to 64-bits
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (15 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 16/43] tcg: Rename struct tcg_temp_info to TempOptInfo Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 18/43] tcg: Introduce TYPE_CONST temporaries Richard Henderson
` (25 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
This propagates the extended value of TCGTemp.val that we did before.
In addition, it will be required for vector constants.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 40 +++++++++++++++++++++-------------------
1 file changed, 21 insertions(+), 19 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 81faf7cf10..33d1fc8f87 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -39,8 +39,8 @@ typedef struct TempOptInfo {
bool is_const;
TCGTemp *prev_copy;
TCGTemp *next_copy;
- tcg_target_ulong val;
- tcg_target_ulong mask;
+ uint64_t val;
+ uint64_t mask;
} TempOptInfo;
static inline TempOptInfo *ts_info(TCGTemp *ts)
@@ -166,11 +166,11 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2)
return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
}
-static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg val)
+static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, uint64_t val)
{
const TCGOpDef *def;
TCGOpcode new_op;
- tcg_target_ulong mask;
+ uint64_t mask;
TempOptInfo *di = arg_info(dst);
def = &tcg_op_defs[op->opc];
@@ -204,7 +204,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
const TCGOpDef *def;
TempOptInfo *di;
TempOptInfo *si;
- tcg_target_ulong mask;
+ uint64_t mask;
TCGOpcode new_op;
if (ts_are_copies(dst_ts, src_ts)) {
@@ -247,7 +247,7 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
}
}
-static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
+static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
{
uint64_t l64, h64;
@@ -410,10 +410,10 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y)
}
}
-static TCGArg do_constant_folding(TCGOpcode op, TCGArg x, TCGArg y)
+static uint64_t do_constant_folding(TCGOpcode op, uint64_t x, uint64_t y)
{
const TCGOpDef *def = &tcg_op_defs[op];
- TCGArg res = do_constant_folding_2(op, x, y);
+ uint64_t res = do_constant_folding_2(op, x, y);
if (!(def->flags & TCG_OPF_64BIT)) {
res = (int32_t)res;
}
@@ -501,8 +501,9 @@ static bool do_constant_folding_cond_eq(TCGCond c)
static TCGArg do_constant_folding_cond(TCGOpcode op, TCGArg x,
TCGArg y, TCGCond c)
{
- tcg_target_ulong xv = arg_info(x)->val;
- tcg_target_ulong yv = arg_info(y)->val;
+ uint64_t xv = arg_info(x)->val;
+ uint64_t yv = arg_info(y)->val;
+
if (arg_is_const(x) && arg_is_const(y)) {
const TCGOpDef *def = &tcg_op_defs[op];
tcg_debug_assert(!(def->flags & TCG_OPF_VECTOR));
@@ -613,9 +614,8 @@ void tcg_optimize(TCGContext *s)
infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps);
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
- tcg_target_ulong mask, partmask, affected;
+ uint64_t mask, partmask, affected, tmp;
int nb_oargs, nb_iargs, i;
- TCGArg tmp;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
@@ -1221,14 +1221,15 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(extract2):
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
- TCGArg v1 = arg_info(op->args[1])->val;
- TCGArg v2 = arg_info(op->args[2])->val;
+ uint64_t v1 = arg_info(op->args[1])->val;
+ uint64_t v2 = arg_info(op->args[2])->val;
+ int shr = op->args[3];
if (opc == INDEX_op_extract2_i64) {
- tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));
+ tmp = (v1 >> shr) | (v2 << (64 - shr));
} else {
- tmp = (int32_t)(((uint32_t)v1 >> op->args[3]) |
- ((uint32_t)v2 << (32 - op->args[3])));
+ tmp = (int32_t)(((uint32_t)v1 >> shr) |
+ ((uint32_t)v2 << (32 - shr)));
}
tcg_opt_gen_movi(s, op, op->args[0], tmp);
break;
@@ -1267,9 +1268,10 @@ void tcg_optimize(TCGContext *s)
break;
}
if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) {
- tcg_target_ulong tv = arg_info(op->args[3])->val;
- tcg_target_ulong fv = arg_info(op->args[4])->val;
+ uint64_t tv = arg_info(op->args[3])->val;
+ uint64_t fv = arg_info(op->args[4])->val;
TCGCond cond = op->args[5];
+
if (fv == 1 && tv == 0) {
cond = tcg_invert_cond(cond);
} else if (!(tv == 1 && fv == 0)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 18/43] tcg: Introduce TYPE_CONST temporaries
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (16 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 17/43] tcg: Expand TempOptInfo to 64-bits Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 19/43] tcg/optimize: Improve find_better_copy Richard Henderson
` (24 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
These will hold a single constant for the duration of the TB.
They are hashed, so that each value has one temp across the TB.
Not used yet, this is all infrastructure.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 24 +++++-
tcg/optimize.c | 13 +++-
tcg/tcg.c | 195 ++++++++++++++++++++++++++++++++++++----------
3 files changed, 188 insertions(+), 44 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index f3eca6feb0..aa7b0ba163 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -492,6 +492,8 @@ typedef enum TCGTempKind {
TEMP_GLOBAL,
/* Temp is in a fixed register. */
TEMP_FIXED,
+ /* Temp is a fixed constant. */
+ TEMP_CONST,
} TCGTempKind;
typedef struct TCGTemp {
@@ -667,6 +669,7 @@ struct TCGContext {
QSIMPLEQ_HEAD(, TCGOp) plugin_ops;
#endif
+ GHashTable *const_table[TCG_TYPE_COUNT];
TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
@@ -683,7 +686,7 @@ struct TCGContext {
static inline bool temp_readonly(TCGTemp *ts)
{
- return ts->kind == TEMP_FIXED;
+ return ts->kind >= TEMP_FIXED;
}
extern TCGContext tcg_init_ctx;
@@ -1051,6 +1054,7 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc);
void tcg_optimize(TCGContext *s);
+/* Allocate a new temporary and initialize it with a constant. */
TCGv_i32 tcg_const_i32(int32_t val);
TCGv_i64 tcg_const_i64(int64_t val);
TCGv_i32 tcg_const_local_i32(int32_t val);
@@ -1060,6 +1064,24 @@ TCGv_vec tcg_const_ones_vec(TCGType);
TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
+/*
+ * Locate or create a read-only temporary that is a constant.
+ * This kind of temporary need not and should not be freed.
+ */
+TCGTemp *tcg_constant_internal(TCGType type, int64_t val);
+
+static inline TCGv_i32 tcg_constant_i32(int32_t val)
+{
+ return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val));
+}
+
+static inline TCGv_i64 tcg_constant_i64(int64_t val)
+{
+ return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val));
+}
+
+TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
+
#if UINTPTR_MAX == UINT32_MAX
# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
# define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 33d1fc8f87..c0fd65d2e4 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -99,8 +99,17 @@ static void init_ts_info(TempOptInfo *infos,
ts->state_ptr = ti;
ti->next_copy = ts;
ti->prev_copy = ts;
- ti->is_const = false;
- ti->mask = -1;
+ if (ts->kind == TEMP_CONST) {
+ ti->is_const = true;
+ ti->val = ti->mask = ts->val;
+ if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) {
+ /* High bits of a 32-bit quantity are garbage. */
+ ti->mask |= ~0xffffffffull;
+ }
+ } else {
+ ti->is_const = false;
+ ti->mask = -1;
+ }
set_bit(idx, temps_used->l);
}
}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 1650c5a9db..e413bf70d4 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1204,13 +1204,19 @@ TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base,
bigendian = 1;
#endif
- if (base_ts->kind != TEMP_FIXED) {
+ switch (base_ts->kind) {
+ case TEMP_FIXED:
+ break;
+ case TEMP_GLOBAL:
/* We do not support double-indirect registers. */
tcg_debug_assert(!base_ts->indirect_reg);
base_ts->indirect_base = 1;
s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64
? 2 : 1);
indirect_reg = 1;
+ break;
+ default:
+ g_assert_not_reached();
}
if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) {
@@ -1335,6 +1341,11 @@ void tcg_temp_free_internal(TCGTemp *ts)
TCGContext *s = tcg_ctx;
int k, idx;
+ /* In order to simplify users of tcg_constant_*, silently ignore free. */
+ if (ts->kind == TEMP_CONST) {
+ return;
+ }
+
#if defined(CONFIG_DEBUG_TCG)
s->temps_in_use--;
if (s->temps_in_use < 0) {
@@ -1351,6 +1362,60 @@ void tcg_temp_free_internal(TCGTemp *ts)
set_bit(idx, s->free_temps[k].l);
}
+TCGTemp *tcg_constant_internal(TCGType type, int64_t val)
+{
+ TCGContext *s = tcg_ctx;
+ GHashTable *h = s->const_table[type];
+ TCGTemp *ts;
+
+ if (h == NULL) {
+ h = g_hash_table_new(g_int64_hash, g_int64_equal);
+ s->const_table[type] = h;
+ }
+
+ ts = g_hash_table_lookup(h, &val);
+ if (ts == NULL) {
+ ts = tcg_temp_alloc(s);
+
+ if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) {
+ TCGTemp *ts2 = tcg_temp_alloc(s);
+
+ ts->base_type = TCG_TYPE_I64;
+ ts->type = TCG_TYPE_I32;
+ ts->kind = TEMP_CONST;
+ ts->temp_allocated = 1;
+ /*
+ * Retain the full value of the 64-bit constant in the low
+ * part, so that the hash table works. Actual uses will
+ * truncate the value to the low part.
+ */
+ ts->val = val;
+
+ tcg_debug_assert(ts2 == ts + 1);
+ ts2->base_type = TCG_TYPE_I64;
+ ts2->type = TCG_TYPE_I32;
+ ts2->kind = TEMP_CONST;
+ ts2->temp_allocated = 1;
+ ts2->val = val >> 32;
+ } else {
+ ts->base_type = type;
+ ts->type = type;
+ ts->kind = TEMP_CONST;
+ ts->temp_allocated = 1;
+ ts->val = val;
+ }
+ g_hash_table_insert(h, &ts->val, ts);
+ }
+
+ return ts;
+}
+
+TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val)
+{
+ val = dup_const(vece, val);
+ return temp_tcgv_vec(tcg_constant_internal(type, val));
+}
+
TCGv_i32 tcg_const_i32(int32_t val)
{
TCGv_i32 t0;
@@ -1883,6 +1948,9 @@ static void tcg_reg_alloc_start(TCGContext *s)
TCGTempVal val = TEMP_VAL_MEM;
switch (ts->kind) {
+ case TEMP_CONST:
+ val = TEMP_VAL_CONST;
+ break;
case TEMP_FIXED:
val = TEMP_VAL_REG;
break;
@@ -1919,6 +1987,26 @@ static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size,
case TEMP_NORMAL:
snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
break;
+ case TEMP_CONST:
+ switch (ts->type) {
+ case TCG_TYPE_I32:
+ snprintf(buf, buf_size, "$0x%x", (int32_t)ts->val);
+ break;
+#if TCG_TARGET_REG_BITS > 32
+ case TCG_TYPE_I64:
+ snprintf(buf, buf_size, "$0x%" PRIx64, ts->val);
+ break;
+#endif
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ case TCG_TYPE_V256:
+ snprintf(buf, buf_size, "v%d$0x%" PRIx64,
+ 64 << (ts->type - TCG_TYPE_V64), ts->val);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
}
return buf;
}
@@ -2519,6 +2607,7 @@ static void la_bb_end(TCGContext *s, int ng, int nt)
state = TS_DEAD | TS_MEM;
break;
case TEMP_NORMAL:
+ case TEMP_CONST:
state = TS_DEAD;
break;
default:
@@ -3172,15 +3261,28 @@ static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet);
mark it free; otherwise mark it dead. */
static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead)
{
- if (temp_readonly(ts)) {
+ TCGTempVal new_type;
+
+ switch (ts->kind) {
+ case TEMP_FIXED:
return;
+ case TEMP_GLOBAL:
+ case TEMP_LOCAL:
+ new_type = TEMP_VAL_MEM;
+ break;
+ case TEMP_NORMAL:
+ new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD;
+ break;
+ case TEMP_CONST:
+ new_type = TEMP_VAL_CONST;
+ break;
+ default:
+ g_assert_not_reached();
}
if (ts->val_type == TEMP_VAL_REG) {
s->reg_to_temp[ts->reg] = NULL;
}
- ts->val_type = (free_or_dead < 0
- || ts->kind != TEMP_NORMAL
- ? TEMP_VAL_MEM : TEMP_VAL_DEAD);
+ ts->val_type = new_type;
}
/* Mark a temporary as dead. */
@@ -3196,10 +3298,7 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts)
static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs,
TCGRegSet preferred_regs, int free_or_dead)
{
- if (temp_readonly(ts)) {
- return;
- }
- if (!ts->mem_coherent) {
+ if (!temp_readonly(ts) && !ts->mem_coherent) {
if (!ts->mem_allocated) {
temp_allocate_frame(s, ts);
}
@@ -3417,12 +3516,22 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
for (i = s->nb_globals; i < s->nb_temps; i++) {
TCGTemp *ts = &s->temps[i];
- if (ts->kind == TEMP_LOCAL) {
+
+ switch (ts->kind) {
+ case TEMP_LOCAL:
temp_save(s, ts, allocated_regs);
- } else {
+ break;
+ case TEMP_NORMAL:
/* The liveness analysis already ensures that temps are dead.
Keep an tcg_debug_assert for safety. */
tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD);
+ break;
+ case TEMP_CONST:
+ /* Similarly, we should have freed any allocated register. */
+ tcg_debug_assert(ts->val_type == TEMP_VAL_CONST);
+ break;
+ default:
+ g_assert_not_reached();
}
}
@@ -3715,45 +3824,42 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
i_preferred_regs = o_preferred_regs = 0;
if (arg_ct->ialias) {
o_preferred_regs = op->output_pref[arg_ct->alias_index];
- if (ts->kind == TEMP_FIXED) {
- /* if fixed register, we must allocate a new register
- if the alias is not the same register */
- if (arg != op->args[arg_ct->alias_index]) {
- goto allocate_in_reg;
- }
- } else {
- /* if the input is aliased to an output and if it is
- not dead after the instruction, we must allocate
- a new register and move it */
- if (!IS_DEAD_ARG(i)) {
- goto allocate_in_reg;
- }
- /* check if the current register has already been allocated
- for another input aliased to an output */
- if (ts->val_type == TEMP_VAL_REG) {
- int k2, i2;
- reg = ts->reg;
- for (k2 = 0 ; k2 < k ; k2++) {
- i2 = def->args_ct[nb_oargs + k2].sort_index;
- if (def->args_ct[i2].ialias && reg == new_args[i2]) {
- goto allocate_in_reg;
- }
+ /*
+ * If the input is readonly, then it cannot also be an
+ * output and aliased to itself. If the input is not
+ * dead after the instruction, we must allocate a new
+ * register and move it.
+ */
+ if (temp_readonly(ts) || !IS_DEAD_ARG(i)) {
+ goto allocate_in_reg;
+ }
+
+ /*
+ * Check if the current register has already been allocated
+ * for another input aliased to an output.
+ */
+ if (ts->val_type == TEMP_VAL_REG) {
+ reg = ts->reg;
+ for (int k2 = 0; k2 < k; k2++) {
+ int i2 = def->args_ct[nb_oargs + k2].sort_index;
+ if (def->args_ct[i2].ialias && reg == new_args[i2]) {
+ goto allocate_in_reg;
}
}
- i_preferred_regs = o_preferred_regs;
}
+ i_preferred_regs = o_preferred_regs;
}
temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
reg = ts->reg;
- if (tcg_regset_test_reg(arg_ct->regs, reg)) {
- /* nothing to do : the constraint is satisfied */
- } else {
- allocate_in_reg:
- /* allocate a new register matching the constraint
- and move the temporary register into it */
+ if (!tcg_regset_test_reg(arg_ct->regs, reg)) {
+ allocate_in_reg:
+ /*
+ * Allocate a new register matching the constraint
+ * and move the temporary register into it.
+ */
temp_load(s, ts, tcg_target_available_regs[ts->type],
i_allocated_regs, 0);
reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
@@ -4211,6 +4317,13 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
}
#endif
+ for (i = 0; i < TCG_TYPE_COUNT; ++i) {
+ if (s->const_table[i]) {
+ g_hash_table_destroy(s->const_table[i]);
+ s->const_table[i] = NULL;
+ }
+ }
+
tcg_reg_alloc_start(s);
s->code_buf = tb->tc.ptr;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 19/43] tcg/optimize: Improve find_better_copy
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (17 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 18/43] tcg: Introduce TYPE_CONST temporaries Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 20/43] tcg/optimize: Adjust TempOptInfo allocation Richard Henderson
` (23 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Prefer TEMP_CONST over anything else.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 27 ++++++++++++---------------
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index c0fd65d2e4..bf2c2a3ce5 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -122,31 +122,28 @@ static void init_arg_info(TempOptInfo *infos,
static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
{
- TCGTemp *i;
+ TCGTemp *i, *g, *l;
- /* If this is already a global, we can't do better. */
- if (ts->kind >= TEMP_GLOBAL) {
+ /* If this is already readonly, we can't do better. */
+ if (temp_readonly(ts)) {
return ts;
}
- /* Search for a global first. */
+ g = l = NULL;
for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
- if (i->kind >= TEMP_GLOBAL) {
+ if (temp_readonly(i)) {
return i;
- }
- }
-
- /* If it is a temp, search for a temp local. */
- if (ts->kind == TEMP_NORMAL) {
- for (i = ts_info(ts)->next_copy; i != ts; i = ts_info(i)->next_copy) {
- if (i->kind >= TEMP_LOCAL) {
- return i;
+ } else if (i->kind > ts->kind) {
+ if (i->kind == TEMP_GLOBAL) {
+ g = i;
+ } else if (i->kind == TEMP_LOCAL) {
+ l = i;
}
}
}
- /* Failure to find a better representation, return the same temp. */
- return ts;
+ /* If we didn't find a better representation, return the same temp. */
+ return g ? g : l ? l : ts;
}
static bool ts_are_copies(TCGTemp *ts1, TCGTemp *ts2)
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 20/43] tcg/optimize: Adjust TempOptInfo allocation
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (18 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 19/43] tcg/optimize: Improve find_better_copy Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 21/43] tcg/optimize: Use tcg_constant_internal with constant folding Richard Henderson
` (22 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
Do not allocate a large block for indexing. Instead, allocate
for each temporary as they are seen.
In general, this will use less memory, if we consider that most
TBs do not touch every target register. This also allows us to
allocate TempOptInfo for new temps created during optimization.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 60 ++++++++++++++++++++++++++++----------------------
1 file changed, 34 insertions(+), 26 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index bf2c2a3ce5..e269962932 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -89,35 +89,41 @@ static void reset_temp(TCGArg arg)
}
/* Initialize and activate a temporary. */
-static void init_ts_info(TempOptInfo *infos,
- TCGTempSet *temps_used, TCGTemp *ts)
+static void init_ts_info(TCGTempSet *temps_used, TCGTemp *ts)
{
size_t idx = temp_idx(ts);
- if (!test_bit(idx, temps_used->l)) {
- TempOptInfo *ti = &infos[idx];
+ TempOptInfo *ti;
+ if (test_bit(idx, temps_used->l)) {
+ return;
+ }
+ set_bit(idx, temps_used->l);
+
+ ti = ts->state_ptr;
+ if (ti == NULL) {
+ ti = tcg_malloc(sizeof(TempOptInfo));
ts->state_ptr = ti;
- ti->next_copy = ts;
- ti->prev_copy = ts;
- if (ts->kind == TEMP_CONST) {
- ti->is_const = true;
- ti->val = ti->mask = ts->val;
- if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) {
- /* High bits of a 32-bit quantity are garbage. */
- ti->mask |= ~0xffffffffull;
- }
- } else {
- ti->is_const = false;
- ti->mask = -1;
+ }
+
+ ti->next_copy = ts;
+ ti->prev_copy = ts;
+ if (ts->kind == TEMP_CONST) {
+ ti->is_const = true;
+ ti->val = ts->val;
+ ti->mask = ts->val;
+ if (TCG_TARGET_REG_BITS > 32 && ts->type == TCG_TYPE_I32) {
+ /* High bits of a 32-bit quantity are garbage. */
+ ti->mask |= ~0xffffffffull;
}
- set_bit(idx, temps_used->l);
+ } else {
+ ti->is_const = false;
+ ti->mask = -1;
}
}
-static void init_arg_info(TempOptInfo *infos,
- TCGTempSet *temps_used, TCGArg arg)
+static void init_arg_info(TCGTempSet *temps_used, TCGArg arg)
{
- init_ts_info(infos, temps_used, arg_temp(arg));
+ init_ts_info(temps_used, arg_temp(arg));
}
static TCGTemp *find_better_copy(TCGContext *s, TCGTemp *ts)
@@ -604,9 +610,8 @@ static bool swap_commutative2(TCGArg *p1, TCGArg *p2)
/* Propagate constants and copies, fold constant expressions. */
void tcg_optimize(TCGContext *s)
{
- int nb_temps, nb_globals;
+ int nb_temps, nb_globals, i;
TCGOp *op, *op_next, *prev_mb = NULL;
- TempOptInfo *infos;
TCGTempSet temps_used;
/* Array VALS has an element for each temp.
@@ -616,12 +621,15 @@ void tcg_optimize(TCGContext *s)
nb_temps = s->nb_temps;
nb_globals = s->nb_globals;
+
bitmap_zero(temps_used.l, nb_temps);
- infos = tcg_malloc(sizeof(TempOptInfo) * nb_temps);
+ for (i = 0; i < nb_temps; ++i) {
+ s->temps[i].state_ptr = NULL;
+ }
QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) {
uint64_t mask, partmask, affected, tmp;
- int nb_oargs, nb_iargs, i;
+ int nb_oargs, nb_iargs;
TCGOpcode opc = op->opc;
const TCGOpDef *def = &tcg_op_defs[opc];
@@ -633,14 +641,14 @@ void tcg_optimize(TCGContext *s)
for (i = 0; i < nb_oargs + nb_iargs; i++) {
TCGTemp *ts = arg_temp(op->args[i]);
if (ts) {
- init_ts_info(infos, &temps_used, ts);
+ init_ts_info(&temps_used, ts);
}
}
} else {
nb_oargs = def->nb_oargs;
nb_iargs = def->nb_iargs;
for (i = 0; i < nb_oargs + nb_iargs; i++) {
- init_arg_info(infos, &temps_used, op->args[i]);
+ init_arg_info(&temps_used, op->args[i]);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 21/43] tcg/optimize: Use tcg_constant_internal with constant folding
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (19 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 20/43] tcg/optimize: Adjust TempOptInfo allocation Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 22/43] tcg: Convert tcg_gen_dupi_vec to TCG_CONST Richard Henderson
` (21 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 108 ++++++++++++++++++++++---------------------------
1 file changed, 49 insertions(+), 59 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index e269962932..1eda7dc419 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -178,37 +178,6 @@ static bool args_are_copies(TCGArg arg1, TCGArg arg2)
return ts_are_copies(arg_temp(arg1), arg_temp(arg2));
}
-static void tcg_opt_gen_movi(TCGContext *s, TCGOp *op, TCGArg dst, uint64_t val)
-{
- const TCGOpDef *def;
- TCGOpcode new_op;
- uint64_t mask;
- TempOptInfo *di = arg_info(dst);
-
- def = &tcg_op_defs[op->opc];
- if (def->flags & TCG_OPF_VECTOR) {
- new_op = INDEX_op_dupi_vec;
- } else if (def->flags & TCG_OPF_64BIT) {
- new_op = INDEX_op_movi_i64;
- } else {
- new_op = INDEX_op_movi_i32;
- }
- op->opc = new_op;
- /* TCGOP_VECL and TCGOP_VECE remain unchanged. */
- op->args[0] = dst;
- op->args[1] = val;
-
- reset_temp(dst);
- di->is_const = true;
- di->val = val;
- mask = val;
- if (TCG_TARGET_REG_BITS > 32 && new_op == INDEX_op_movi_i32) {
- /* High bits of the destination are now garbage. */
- mask |= ~0xffffffffull;
- }
- di->mask = mask;
-}
-
static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
{
TCGTemp *dst_ts = arg_temp(dst);
@@ -259,6 +228,27 @@ static void tcg_opt_gen_mov(TCGContext *s, TCGOp *op, TCGArg dst, TCGArg src)
}
}
+static void tcg_opt_gen_movi(TCGContext *s, TCGTempSet *temps_used,
+ TCGOp *op, TCGArg dst, uint64_t val)
+{
+ const TCGOpDef *def = &tcg_op_defs[op->opc];
+ TCGType type;
+ TCGTemp *tv;
+
+ if (def->flags & TCG_OPF_VECTOR) {
+ type = TCGOP_VECL(op) + TCG_TYPE_V64;
+ } else if (def->flags & TCG_OPF_64BIT) {
+ type = TCG_TYPE_I64;
+ } else {
+ type = TCG_TYPE_I32;
+ }
+
+ /* Convert movi to mov with constant temp. */
+ tv = tcg_constant_internal(type, val);
+ init_ts_info(temps_used, tv);
+ tcg_opt_gen_mov(s, op, dst, temp_arg(tv));
+}
+
static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
{
uint64_t l64, h64;
@@ -622,7 +612,7 @@ void tcg_optimize(TCGContext *s)
nb_temps = s->nb_temps;
nb_globals = s->nb_globals;
- bitmap_zero(temps_used.l, nb_temps);
+ memset(&temps_used, 0, sizeof(temps_used));
for (i = 0; i < nb_temps; ++i) {
s->temps[i].state_ptr = NULL;
}
@@ -727,7 +717,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(rotr):
if (arg_is_const(op->args[1])
&& arg_info(op->args[1])->val == 0) {
- tcg_opt_gen_movi(s, op, op->args[0], 0);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
continue;
}
break;
@@ -1050,7 +1040,7 @@ void tcg_optimize(TCGContext *s)
if (partmask == 0) {
tcg_debug_assert(nb_oargs == 1);
- tcg_opt_gen_movi(s, op, op->args[0], 0);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
continue;
}
if (affected == 0) {
@@ -1067,7 +1057,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(mulsh):
if (arg_is_const(op->args[2])
&& arg_info(op->args[2])->val == 0) {
- tcg_opt_gen_movi(s, op, op->args[0], 0);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
continue;
}
break;
@@ -1094,7 +1084,7 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(sub):
CASE_OP_32_64_VEC(xor):
if (args_are_copies(op->args[1], op->args[2])) {
- tcg_opt_gen_movi(s, op, op->args[0], 0);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], 0);
continue;
}
break;
@@ -1111,14 +1101,14 @@ void tcg_optimize(TCGContext *s)
break;
CASE_OP_32_64(movi):
case INDEX_op_dupi_vec:
- tcg_opt_gen_movi(s, op, op->args[0], op->args[1]);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], op->args[1]);
break;
case INDEX_op_dup_vec:
if (arg_is_const(op->args[1])) {
tmp = arg_info(op->args[1])->val;
tmp = dup_const(TCGOP_VECE(op), tmp);
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1128,7 +1118,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
tmp = arg_info(op->args[1])->val;
if (tmp == arg_info(op->args[2])->val) {
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
break;
}
} else if (args_are_copies(op->args[1], op->args[2])) {
@@ -1156,7 +1146,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_extrh_i64_i32:
if (arg_is_const(op->args[1])) {
tmp = do_constant_folding(opc, arg_info(op->args[1])->val, 0);
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1186,7 +1176,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
tmp = do_constant_folding(opc, arg_info(op->args[1])->val,
arg_info(op->args[2])->val);
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1197,7 +1187,7 @@ void tcg_optimize(TCGContext *s)
TCGArg v = arg_info(op->args[1])->val;
if (v != 0) {
tmp = do_constant_folding(opc, v, 0);
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
} else {
tcg_opt_gen_mov(s, op, op->args[0], op->args[2]);
}
@@ -1210,7 +1200,7 @@ void tcg_optimize(TCGContext *s)
tmp = deposit64(arg_info(op->args[1])->val,
op->args[3], op->args[4],
arg_info(op->args[2])->val);
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1219,7 +1209,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1])) {
tmp = extract64(arg_info(op->args[1])->val,
op->args[2], op->args[3]);
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1228,7 +1218,7 @@ void tcg_optimize(TCGContext *s)
if (arg_is_const(op->args[1])) {
tmp = sextract64(arg_info(op->args[1])->val,
op->args[2], op->args[3]);
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1245,7 +1235,7 @@ void tcg_optimize(TCGContext *s)
tmp = (int32_t)(((uint32_t)v1 >> shr) |
((uint32_t)v2 << (32 - shr)));
}
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1254,7 +1244,7 @@ void tcg_optimize(TCGContext *s)
tmp = do_constant_folding_cond(opc, op->args[1],
op->args[2], op->args[3]);
if (tmp != 2) {
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
break;
}
goto do_default;
@@ -1264,7 +1254,7 @@ void tcg_optimize(TCGContext *s)
op->args[1], op->args[2]);
if (tmp != 2) {
if (tmp) {
- bitmap_zero(temps_used.l, nb_temps);
+ memset(&temps_used, 0, sizeof(temps_used));
op->opc = INDEX_op_br;
op->args[0] = op->args[3];
} else {
@@ -1310,7 +1300,7 @@ void tcg_optimize(TCGContext *s)
uint64_t a = ((uint64_t)ah << 32) | al;
uint64_t b = ((uint64_t)bh << 32) | bl;
TCGArg rl, rh;
- TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32);
+ TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32);
if (opc == INDEX_op_add2_i32) {
a += b;
@@ -1320,8 +1310,8 @@ void tcg_optimize(TCGContext *s)
rl = op->args[0];
rh = op->args[1];
- tcg_opt_gen_movi(s, op, rl, (int32_t)a);
- tcg_opt_gen_movi(s, op2, rh, (int32_t)(a >> 32));
+ tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)a);
+ tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(a >> 32));
break;
}
goto do_default;
@@ -1332,12 +1322,12 @@ void tcg_optimize(TCGContext *s)
uint32_t b = arg_info(op->args[3])->val;
uint64_t r = (uint64_t)a * b;
TCGArg rl, rh;
- TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_movi_i32);
+ TCGOp *op2 = tcg_op_insert_before(s, op, INDEX_op_mov_i32);
rl = op->args[0];
rh = op->args[1];
- tcg_opt_gen_movi(s, op, rl, (int32_t)r);
- tcg_opt_gen_movi(s, op2, rh, (int32_t)(r >> 32));
+ tcg_opt_gen_movi(s, &temps_used, op, rl, (int32_t)r);
+ tcg_opt_gen_movi(s, &temps_used, op2, rh, (int32_t)(r >> 32));
break;
}
goto do_default;
@@ -1348,7 +1338,7 @@ void tcg_optimize(TCGContext *s)
if (tmp != 2) {
if (tmp) {
do_brcond_true:
- bitmap_zero(temps_used.l, nb_temps);
+ memset(&temps_used, 0, sizeof(temps_used));
op->opc = INDEX_op_br;
op->args[0] = op->args[5];
} else {
@@ -1364,7 +1354,7 @@ void tcg_optimize(TCGContext *s)
/* Simplify LT/GE comparisons vs zero to a single compare
vs the high word of the input. */
do_brcond_high:
- bitmap_zero(temps_used.l, nb_temps);
+ memset(&temps_used, 0, sizeof(temps_used));
op->opc = INDEX_op_brcond_i32;
op->args[0] = op->args[1];
op->args[1] = op->args[3];
@@ -1390,7 +1380,7 @@ void tcg_optimize(TCGContext *s)
goto do_default;
}
do_brcond_low:
- bitmap_zero(temps_used.l, nb_temps);
+ memset(&temps_used, 0, sizeof(temps_used));
op->opc = INDEX_op_brcond_i32;
op->args[1] = op->args[2];
op->args[2] = op->args[4];
@@ -1425,7 +1415,7 @@ void tcg_optimize(TCGContext *s)
op->args[5]);
if (tmp != 2) {
do_setcond_const:
- tcg_opt_gen_movi(s, op, op->args[0], tmp);
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
} else if ((op->args[5] == TCG_COND_LT
|| op->args[5] == TCG_COND_GE)
&& arg_is_const(op->args[3])
@@ -1510,7 +1500,7 @@ void tcg_optimize(TCGContext *s)
block, otherwise we only trash the output args. "mask" is
the non-zero bits mask for the first output arg. */
if (def->flags & TCG_OPF_BB_END) {
- bitmap_zero(temps_used.l, nb_temps);
+ memset(&temps_used, 0, sizeof(temps_used));
} else {
do_reset_output:
for (i = 0; i < nb_oargs; i++) {
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 22/43] tcg: Convert tcg_gen_dupi_vec to TCG_CONST
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (20 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 21/43] tcg/optimize: Use tcg_constant_internal with constant folding Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 23/43] tcg: Use tcg_constant_i32 with icount expander Richard Henderson
` (20 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Because we now store uint64_t in TCGTemp, we can now always
store the full 64-bit duplicate immediate. So remove the
difference between 32- and 64-bit hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 9 ++++-----
tcg/tcg-op-vec.c | 39 ++++++++++-----------------------------
tcg/tcg.c | 7 +------
3 files changed, 15 insertions(+), 40 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 1eda7dc419..af07c6f628 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1116,11 +1116,10 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_dup2_vec:
assert(TCG_TARGET_REG_BITS == 32);
if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
- tmp = arg_info(op->args[1])->val;
- if (tmp == arg_info(op->args[2])->val) {
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], tmp);
- break;
- }
+ tcg_opt_gen_movi(s, &temps_used, op, op->args[0],
+ deposit64(arg_info(op->args[1])->val, 32, 32,
+ arg_info(op->args[2])->val));
+ break;
} else if (args_are_copies(op->args[1], op->args[2])) {
op->opc = INDEX_op_dup_vec;
TCGOP_VECE(op) = MO_32;
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index cdbf11c573..9fbed1366c 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -216,25 +216,17 @@ void tcg_gen_mov_vec(TCGv_vec r, TCGv_vec a)
}
}
-#define MO_REG (TCG_TARGET_REG_BITS == 64 ? MO_64 : MO_32)
-
-static void do_dupi_vec(TCGv_vec r, unsigned vece, TCGArg a)
-{
- TCGTemp *rt = tcgv_vec_temp(r);
- vec_gen_2(INDEX_op_dupi_vec, rt->base_type, vece, temp_arg(rt), a);
-}
-
TCGv_vec tcg_const_zeros_vec(TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(type);
- do_dupi_vec(ret, MO_REG, 0);
+ tcg_gen_dupi_vec(MO_64, ret, 0);
return ret;
}
TCGv_vec tcg_const_ones_vec(TCGType type)
{
TCGv_vec ret = tcg_temp_new_vec(type);
- do_dupi_vec(ret, MO_REG, -1);
+ tcg_gen_dupi_vec(MO_64, ret, -1);
return ret;
}
@@ -252,39 +244,28 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
{
- if (TCG_TARGET_REG_BITS == 64) {
- do_dupi_vec(r, MO_64, a);
- } else if (a == dup_const(MO_32, a)) {
- do_dupi_vec(r, MO_32, a);
- } else {
- TCGv_i64 c = tcg_const_i64(a);
- tcg_gen_dup_i64_vec(MO_64, r, c);
- tcg_temp_free_i64(c);
- }
+ tcg_gen_dupi_vec(MO_64, r, a);
}
void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)
{
- do_dupi_vec(r, MO_REG, dup_const(MO_32, a));
+ tcg_gen_dupi_vec(MO_32, r, a);
}
void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)
{
- do_dupi_vec(r, MO_REG, dup_const(MO_16, a));
+ tcg_gen_dupi_vec(MO_16, r, a);
}
void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
{
- do_dupi_vec(r, MO_REG, dup_const(MO_8, a));
+ tcg_gen_dupi_vec(MO_8, r, a);
}
void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
{
- if (vece == MO_64) {
- tcg_gen_dup64i_vec(r, a);
- } else {
- do_dupi_vec(r, MO_REG, dup_const(vece, a));
- }
+ TCGTemp *rt = tcgv_vec_temp(r);
+ tcg_gen_mov_vec(r, tcg_constant_vec(rt->base_type, vece, a));
}
void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
@@ -489,8 +470,8 @@ void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a)
if (tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) > 0) {
tcg_gen_sari_vec(vece, t, a, (8 << vece) - 1);
} else {
- do_dupi_vec(t, MO_REG, 0);
- tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a, t);
+ tcg_gen_cmp_vec(TCG_COND_LT, vece, t, a,
+ tcg_constant_vec(type, vece, 0));
}
tcg_gen_xor_vec(vece, r, a, t);
tcg_gen_sub_vec(vece, r, r, t);
diff --git a/tcg/tcg.c b/tcg/tcg.c
index e413bf70d4..0ce45fd123 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3440,16 +3440,11 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs,
* The targets will, in general, have to do this search anyway,
* do this generically.
*/
- if (TCG_TARGET_REG_BITS == 32) {
- val = dup_const(MO_32, val);
- vece = MO_32;
- }
if (val == dup_const(MO_8, val)) {
vece = MO_8;
} else if (val == dup_const(MO_16, val)) {
vece = MO_16;
- } else if (TCG_TARGET_REG_BITS == 64 &&
- val == dup_const(MO_32, val)) {
+ } else if (val == dup_const(MO_32, val)) {
vece = MO_32;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 23/43] tcg: Use tcg_constant_i32 with icount expander
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (21 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 22/43] tcg: Convert tcg_gen_dupi_vec to TCG_CONST Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 24/43] tcg: Use tcg_constant_{i32,i64} with tcg int expanders Richard Henderson
` (19 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
We must do this before we adjust tcg_out_movi_i32, lest the
under-the-hood poking that we do for icount be broken.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/gen-icount.h | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 822c43cfd3..404732518a 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -34,7 +34,7 @@ static inline void gen_io_end(void)
static inline void gen_tb_start(TranslationBlock *tb)
{
- TCGv_i32 count, imm;
+ TCGv_i32 count;
tcg_ctx->exitreq_label = gen_new_label();
if (tb_cflags(tb) & CF_USE_ICOUNT) {
@@ -48,15 +48,13 @@ static inline void gen_tb_start(TranslationBlock *tb)
offsetof(ArchCPU, env));
if (tb_cflags(tb) & CF_USE_ICOUNT) {
- imm = tcg_temp_new_i32();
- /* We emit a movi with a dummy immediate argument. Keep the insn index
- * of the movi so that we later (when we know the actual insn count)
- * can update the immediate argument with the actual insn count. */
- tcg_gen_movi_i32(imm, 0xdeadbeef);
+ /*
+ * We emit a sub with a dummy immediate argument. Keep the insn index
+ * of the sub so that we later (when we know the actual insn count)
+ * can update the argument with the actual insn count.
+ */
+ tcg_gen_sub_i32(count, count, tcg_constant_i32(0));
icount_start_insn = tcg_last_op();
-
- tcg_gen_sub_i32(count, count, imm);
- tcg_temp_free_i32(imm);
}
tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label);
@@ -74,9 +72,12 @@ static inline void gen_tb_start(TranslationBlock *tb)
static inline void gen_tb_end(TranslationBlock *tb, int num_insns)
{
if (tb_cflags(tb) & CF_USE_ICOUNT) {
- /* Update the num_insn immediate parameter now that we know
- * the actual insn count. */
- tcg_set_insn_param(icount_start_insn, 1, num_insns);
+ /*
+ * Update the num_insn immediate parameter now that we know
+ * the actual insn count.
+ */
+ tcg_set_insn_param(icount_start_insn, 2,
+ tcgv_i32_arg(tcg_constant_i32(num_insns)));
}
gen_set_label(tcg_ctx->exitreq_label);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 24/43] tcg: Use tcg_constant_{i32,i64} with tcg int expanders
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (22 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 23/43] tcg: Use tcg_constant_i32 with icount expander Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 25/43] tcg: Use tcg_constant_{i32,i64} with tcg plugins Richard Henderson
` (18 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op.h | 13 +--
tcg/tcg-op.c | 227 ++++++++++++++++++++-----------------------
2 files changed, 109 insertions(+), 131 deletions(-)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 5abf17fecc..b4fba35e87 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -271,6 +271,7 @@ void tcg_gen_mb(TCGBar);
/* 32 bit ops */
+void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg);
void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
@@ -349,11 +350,6 @@ static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
}
}
-static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
-{
- tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
-}
-
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
tcg_target_long offset)
{
@@ -467,6 +463,7 @@ static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
/* 64 bit ops */
+void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
@@ -550,11 +547,6 @@ static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
}
}
-static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
-{
- tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
-}
-
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
tcg_target_long offset)
{
@@ -698,7 +690,6 @@ static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
void tcg_gen_discard_i64(TCGv_i64 arg);
void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
-void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 4b8a473fad..e2d8ae3234 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -104,15 +104,18 @@ void tcg_gen_mb(TCGBar mb_type)
/* 32 bit ops */
+void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
+{
+ tcg_gen_mov_i32(ret, tcg_constant_i32(arg));
+}
+
void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
{
/* some cases can be optimized here */
if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else {
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_add_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
+ tcg_gen_add_i32(ret, arg1, tcg_constant_i32(arg2));
}
}
@@ -122,9 +125,7 @@ void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
/* Don't recurse with tcg_gen_neg_i32. */
tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg2);
} else {
- TCGv_i32 t0 = tcg_const_i32(arg1);
- tcg_gen_sub_i32(ret, t0, arg2);
- tcg_temp_free_i32(t0);
+ tcg_gen_sub_i32(ret, tcg_constant_i32(arg1), arg2);
}
}
@@ -134,15 +135,12 @@ void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else {
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_sub_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
+ tcg_gen_sub_i32(ret, arg1, tcg_constant_i32(arg2));
}
}
void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
{
- TCGv_i32 t0;
/* Some cases can be optimized here. */
switch (arg2) {
case 0:
@@ -165,9 +163,8 @@ void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
}
break;
}
- t0 = tcg_const_i32(arg2);
- tcg_gen_and_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
+
+ tcg_gen_and_i32(ret, arg1, tcg_constant_i32(arg2));
}
void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
@@ -178,9 +175,7 @@ void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
} else if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else {
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_or_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
+ tcg_gen_or_i32(ret, arg1, tcg_constant_i32(arg2));
}
}
@@ -193,9 +188,7 @@ void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
/* Don't recurse with tcg_gen_not_i32. */
tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
} else {
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_xor_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
+ tcg_gen_xor_i32(ret, arg1, tcg_constant_i32(arg2));
}
}
@@ -205,9 +198,7 @@ void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else {
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_shl_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
+ tcg_gen_shl_i32(ret, arg1, tcg_constant_i32(arg2));
}
}
@@ -217,9 +208,7 @@ void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else {
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_shr_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
+ tcg_gen_shr_i32(ret, arg1, tcg_constant_i32(arg2));
}
}
@@ -229,9 +218,7 @@ void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else {
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_sar_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
+ tcg_gen_sar_i32(ret, arg1, tcg_constant_i32(arg2));
}
}
@@ -250,9 +237,7 @@ void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *l)
if (cond == TCG_COND_ALWAYS) {
tcg_gen_br(l);
} else if (cond != TCG_COND_NEVER) {
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_brcond_i32(cond, arg1, t0, l);
- tcg_temp_free_i32(t0);
+ tcg_gen_brcond_i32(cond, arg1, tcg_constant_i32(arg2), l);
}
}
@@ -271,9 +256,7 @@ void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
TCGv_i32 arg1, int32_t arg2)
{
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_setcond_i32(cond, ret, arg1, t0);
- tcg_temp_free_i32(t0);
+ tcg_gen_setcond_i32(cond, ret, arg1, tcg_constant_i32(arg2));
}
void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
@@ -283,9 +266,7 @@ void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
} else if (is_power_of_2(arg2)) {
tcg_gen_shli_i32(ret, arg1, ctz32(arg2));
} else {
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_mul_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
+ tcg_gen_mul_i32(ret, arg1, tcg_constant_i32(arg2));
}
}
@@ -433,9 +414,7 @@ void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
{
- TCGv_i32 t = tcg_const_i32(arg2);
- tcg_gen_clz_i32(ret, arg1, t);
- tcg_temp_free_i32(t);
+ tcg_gen_clz_i32(ret, arg1, tcg_constant_i32(arg2));
}
void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
@@ -468,10 +447,9 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
tcg_gen_clzi_i32(t, t, 32);
tcg_gen_xori_i32(t, t, 31);
}
- z = tcg_const_i32(0);
+ z = tcg_constant_i32(0);
tcg_gen_movcond_i32(TCG_COND_EQ, ret, arg1, z, arg2, t);
tcg_temp_free_i32(t);
- tcg_temp_free_i32(z);
} else {
gen_helper_ctz_i32(ret, arg1, arg2);
}
@@ -487,9 +465,7 @@ void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
tcg_gen_ctpop_i32(ret, t);
tcg_temp_free_i32(t);
} else {
- TCGv_i32 t = tcg_const_i32(arg2);
- tcg_gen_ctz_i32(ret, arg1, t);
- tcg_temp_free_i32(t);
+ tcg_gen_ctz_i32(ret, arg1, tcg_constant_i32(arg2));
}
}
@@ -547,9 +523,7 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else if (TCG_TARGET_HAS_rot_i32) {
- TCGv_i32 t0 = tcg_const_i32(arg2);
- tcg_gen_rotl_i32(ret, arg1, t0);
- tcg_temp_free_i32(t0);
+ tcg_gen_rotl_i32(ret, arg1, tcg_constant_i32(arg2));
} else {
TCGv_i32 t0, t1;
t0 = tcg_temp_new_i32();
@@ -653,9 +627,8 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
tcg_gen_andi_i32(ret, arg, (1u << len) - 1);
} else if (TCG_TARGET_HAS_deposit_i32
&& TCG_TARGET_deposit_i32_valid(ofs, len)) {
- TCGv_i32 zero = tcg_const_i32(0);
+ TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len);
- tcg_temp_free_i32(zero);
} else {
/* To help two-operand hosts we prefer to zero-extend first,
which allows ARG to stay live. */
@@ -1052,7 +1025,7 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
} else {
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv_i32 t1 = tcg_temp_new_i32();
- TCGv_i32 t2 = tcg_const_i32(0x00ff00ff);
+ TCGv_i32 t2 = tcg_constant_i32(0x00ff00ff);
/* arg = abcd */
tcg_gen_shri_i32(t0, arg, 8); /* t0 = .abc */
@@ -1067,7 +1040,6 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg)
tcg_temp_free_i32(t0);
tcg_temp_free_i32(t1);
- tcg_temp_free_i32(t2);
}
}
@@ -1114,8 +1086,15 @@ void tcg_gen_discard_i64(TCGv_i64 arg)
void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
{
- tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
- tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
+ TCGTemp *ts = tcgv_i64_temp(arg);
+
+ /* Canonicalize TCGv_i64 TEMP_CONST into TCGv_i32 TEMP_CONST. */
+ if (ts->kind == TEMP_CONST) {
+ tcg_gen_movi_i64(ret, ts->val);
+ } else {
+ tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
+ tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
+ }
}
void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
@@ -1237,6 +1216,14 @@ void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
tcg_temp_free_i64(t0);
tcg_temp_free_i32(t1);
}
+
+#else
+
+void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
+{
+ tcg_gen_mov_i64(ret, tcg_constant_i64(arg));
+}
+
#endif /* TCG_TARGET_REG_SIZE == 32 */
void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
@@ -1244,10 +1231,12 @@ void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
/* some cases can be optimized here */
if (arg2 == 0) {
tcg_gen_mov_i64(ret, arg1);
+ } else if (TCG_TARGET_REG_BITS == 64) {
+ tcg_gen_add_i64(ret, arg1, tcg_constant_i64(arg2));
} else {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_add_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret),
+ TCGV_LOW(arg1), TCGV_HIGH(arg1),
+ tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32));
}
}
@@ -1256,10 +1245,12 @@ void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
if (arg1 == 0 && TCG_TARGET_HAS_neg_i64) {
/* Don't recurse with tcg_gen_neg_i64. */
tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg2);
+ } else if (TCG_TARGET_REG_BITS == 64) {
+ tcg_gen_sub_i64(ret, tcg_constant_i64(arg1), arg2);
} else {
- TCGv_i64 t0 = tcg_const_i64(arg1);
- tcg_gen_sub_i64(ret, t0, arg2);
- tcg_temp_free_i64(t0);
+ tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret),
+ tcg_constant_i32(arg1), tcg_constant_i32(arg1 >> 32),
+ TCGV_LOW(arg2), TCGV_HIGH(arg2));
}
}
@@ -1268,17 +1259,17 @@ void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
/* some cases can be optimized here */
if (arg2 == 0) {
tcg_gen_mov_i64(ret, arg1);
+ } else if (TCG_TARGET_REG_BITS == 64) {
+ tcg_gen_sub_i64(ret, arg1, tcg_constant_i64(arg2));
} else {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_sub_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret),
+ TCGV_LOW(arg1), TCGV_HIGH(arg1),
+ tcg_constant_i32(arg2), tcg_constant_i32(arg2 >> 32));
}
}
void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
{
- TCGv_i64 t0;
-
if (TCG_TARGET_REG_BITS == 32) {
tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
@@ -1313,9 +1304,8 @@ void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
}
break;
}
- t0 = tcg_const_i64(arg2);
- tcg_gen_and_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+
+ tcg_gen_and_i64(ret, arg1, tcg_constant_i64(arg2));
}
void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
@@ -1331,9 +1321,7 @@ void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
} else if (arg2 == 0) {
tcg_gen_mov_i64(ret, arg1);
} else {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_or_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_or_i64(ret, arg1, tcg_constant_i64(arg2));
}
}
@@ -1351,9 +1339,7 @@ void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
/* Don't recurse with tcg_gen_not_i64. */
tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
} else {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_xor_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_xor_i64(ret, arg1, tcg_constant_i64(arg2));
}
}
@@ -1415,9 +1401,7 @@ void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
} else if (arg2 == 0) {
tcg_gen_mov_i64(ret, arg1);
} else {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_shl_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_shl_i64(ret, arg1, tcg_constant_i64(arg2));
}
}
@@ -1429,9 +1413,7 @@ void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
} else if (arg2 == 0) {
tcg_gen_mov_i64(ret, arg1);
} else {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_shr_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_shr_i64(ret, arg1, tcg_constant_i64(arg2));
}
}
@@ -1443,9 +1425,7 @@ void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
} else if (arg2 == 0) {
tcg_gen_mov_i64(ret, arg1);
} else {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_sar_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_sar_i64(ret, arg1, tcg_constant_i64(arg2));
}
}
@@ -1468,12 +1448,17 @@ void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l)
void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *l)
{
- if (cond == TCG_COND_ALWAYS) {
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_gen_brcond_i64(cond, arg1, tcg_constant_i64(arg2), l);
+ } else if (cond == TCG_COND_ALWAYS) {
tcg_gen_br(l);
} else if (cond != TCG_COND_NEVER) {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_brcond_i64(cond, arg1, t0, l);
- tcg_temp_free_i64(t0);
+ l->refs++;
+ tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
+ TCGV_LOW(arg1), TCGV_HIGH(arg1),
+ tcg_constant_i32(arg2),
+ tcg_constant_i32(arg2 >> 32),
+ cond, label_arg(l));
}
}
@@ -1499,9 +1484,19 @@ void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
TCGv_i64 arg1, int64_t arg2)
{
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_setcond_i64(cond, ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ if (TCG_TARGET_REG_BITS == 64) {
+ tcg_gen_setcond_i64(cond, ret, arg1, tcg_constant_i64(arg2));
+ } else if (cond == TCG_COND_ALWAYS) {
+ tcg_gen_movi_i64(ret, 1);
+ } else if (cond == TCG_COND_NEVER) {
+ tcg_gen_movi_i64(ret, 0);
+ } else {
+ tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret),
+ TCGV_LOW(arg1), TCGV_HIGH(arg1),
+ tcg_constant_i32(arg2),
+ tcg_constant_i32(arg2 >> 32), cond);
+ tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
+ }
}
void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
@@ -1690,7 +1685,7 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
} else {
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
- TCGv_i64 t2 = tcg_const_i64(0x00ff00ff);
+ TCGv_i64 t2 = tcg_constant_i64(0x00ff00ff);
/* arg = ....abcd */
tcg_gen_shri_i64(t0, arg, 8); /* t0 = .....abc */
@@ -1706,7 +1701,6 @@ void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg)
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
- tcg_temp_free_i64(t2);
}
}
@@ -1850,16 +1844,16 @@ void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
if (TCG_TARGET_REG_BITS == 32
&& TCG_TARGET_HAS_clz_i32
&& arg2 <= 0xffffffffu) {
- TCGv_i32 t = tcg_const_i32((uint32_t)arg2 - 32);
- tcg_gen_clz_i32(t, TCGV_LOW(arg1), t);
+ TCGv_i32 t = tcg_temp_new_i32();
+ tcg_gen_clzi_i32(t, TCGV_LOW(arg1), arg2 - 32);
tcg_gen_addi_i32(t, t, 32);
tcg_gen_clz_i32(TCGV_LOW(ret), TCGV_HIGH(arg1), t);
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
tcg_temp_free_i32(t);
} else {
- TCGv_i64 t = tcg_const_i64(arg2);
- tcg_gen_clz_i64(ret, arg1, t);
- tcg_temp_free_i64(t);
+ TCGv_i64 t0 = tcg_const_i64(arg2);
+ tcg_gen_clz_i64(ret, arg1, t0);
+ tcg_temp_free_i64(t0);
}
}
@@ -1881,7 +1875,7 @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
tcg_gen_clzi_i64(t, t, 64);
tcg_gen_xori_i64(t, t, 63);
}
- z = tcg_const_i64(0);
+ z = tcg_constant_i64(0);
tcg_gen_movcond_i64(TCG_COND_EQ, ret, arg1, z, arg2, t);
tcg_temp_free_i64(t);
tcg_temp_free_i64(z);
@@ -1895,8 +1889,8 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
if (TCG_TARGET_REG_BITS == 32
&& TCG_TARGET_HAS_ctz_i32
&& arg2 <= 0xffffffffu) {
- TCGv_i32 t32 = tcg_const_i32((uint32_t)arg2 - 32);
- tcg_gen_ctz_i32(t32, TCGV_HIGH(arg1), t32);
+ TCGv_i32 t32 = tcg_temp_new_i32();
+ tcg_gen_ctzi_i32(t32, TCGV_HIGH(arg1), arg2 - 32);
tcg_gen_addi_i32(t32, t32, 32);
tcg_gen_ctz_i32(TCGV_LOW(ret), TCGV_LOW(arg1), t32);
tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
@@ -1911,9 +1905,9 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
tcg_gen_ctpop_i64(ret, t);
tcg_temp_free_i64(t);
} else {
- TCGv_i64 t64 = tcg_const_i64(arg2);
- tcg_gen_ctz_i64(ret, arg1, t64);
- tcg_temp_free_i64(t64);
+ TCGv_i64 t0 = tcg_const_i64(arg2);
+ tcg_gen_ctz_i64(ret, arg1, t0);
+ tcg_temp_free_i64(t0);
}
}
@@ -1969,9 +1963,7 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
if (arg2 == 0) {
tcg_gen_mov_i64(ret, arg1);
} else if (TCG_TARGET_HAS_rot_i64) {
- TCGv_i64 t0 = tcg_const_i64(arg2);
- tcg_gen_rotl_i64(ret, arg1, t0);
- tcg_temp_free_i64(t0);
+ tcg_gen_rotl_i64(ret, arg1, tcg_constant_i64(arg2));
} else {
TCGv_i64 t0, t1;
t0 = tcg_temp_new_i64();
@@ -2089,9 +2081,8 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
tcg_gen_andi_i64(ret, arg, (1ull << len) - 1);
} else if (TCG_TARGET_HAS_deposit_i64
&& TCG_TARGET_deposit_i64_valid(ofs, len)) {
- TCGv_i64 zero = tcg_const_i64(0);
+ TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len);
- tcg_temp_free_i64(zero);
} else {
if (TCG_TARGET_REG_BITS == 32) {
if (ofs >= 32) {
@@ -3102,9 +3093,8 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
#ifdef CONFIG_SOFTMMU
{
- TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
- gen(retv, cpu_env, addr, cmpv, newv, oi);
- tcg_temp_free_i32(oi);
+ TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx);
+ gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi));
}
#else
gen(retv, cpu_env, addr, cmpv, newv);
@@ -3147,9 +3137,8 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
#ifdef CONFIG_SOFTMMU
{
- TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop, idx));
- gen(retv, cpu_env, addr, cmpv, newv, oi);
- tcg_temp_free_i32(oi);
+ TCGMemOpIdx oi = make_memop_idx(memop, idx);
+ gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi));
}
#else
gen(retv, cpu_env, addr, cmpv, newv);
@@ -3211,9 +3200,8 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
#ifdef CONFIG_SOFTMMU
{
- TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
- gen(ret, cpu_env, addr, val, oi);
- tcg_temp_free_i32(oi);
+ TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx);
+ gen(ret, cpu_env, addr, val, tcg_constant_i32(oi));
}
#else
gen(ret, cpu_env, addr, val);
@@ -3257,9 +3245,8 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
#ifdef CONFIG_SOFTMMU
{
- TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
- gen(ret, cpu_env, addr, val, oi);
- tcg_temp_free_i32(oi);
+ TCGMemOpIdx oi = make_memop_idx(memop & ~MO_SIGN, idx);
+ gen(ret, cpu_env, addr, val, tcg_constant_i32(oi));
}
#else
gen(ret, cpu_env, addr, val);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 25/43] tcg: Use tcg_constant_{i32,i64} with tcg plugins
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (23 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 24/43] tcg: Use tcg_constant_{i32,i64} with tcg int expanders Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 26/43] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders Richard Henderson
` (17 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/plugin-gen.c | 49 +++++++++++++++++++-----------------------
1 file changed, 22 insertions(+), 27 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 51580d51a0..e5dc9d0ca9 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -284,8 +284,8 @@ static TCGOp *copy_extu_i32_i64(TCGOp **begin_op, TCGOp *op)
if (TCG_TARGET_REG_BITS == 32) {
/* mov_i32 */
op = copy_op(begin_op, op, INDEX_op_mov_i32);
- /* movi_i32 */
- op = copy_op(begin_op, op, INDEX_op_movi_i32);
+ /* mov_i32 w/ $0 */
+ op = copy_op(begin_op, op, INDEX_op_mov_i32);
} else {
/* extu_i32_i64 */
op = copy_op(begin_op, op, INDEX_op_extu_i32_i64);
@@ -306,39 +306,34 @@ static TCGOp *copy_mov_i64(TCGOp **begin_op, TCGOp *op)
return op;
}
-static TCGOp *copy_movi_i64(TCGOp **begin_op, TCGOp *op, uint64_t v)
-{
- if (TCG_TARGET_REG_BITS == 32) {
- /* 2x movi_i32 */
- op = copy_op(begin_op, op, INDEX_op_movi_i32);
- op->args[1] = v;
-
- op = copy_op(begin_op, op, INDEX_op_movi_i32);
- op->args[1] = v >> 32;
- } else {
- /* movi_i64 */
- op = copy_op(begin_op, op, INDEX_op_movi_i64);
- op->args[1] = v;
- }
- return op;
-}
-
static TCGOp *copy_const_ptr(TCGOp **begin_op, TCGOp *op, void *ptr)
{
if (UINTPTR_MAX == UINT32_MAX) {
- /* movi_i32 */
- op = copy_op(begin_op, op, INDEX_op_movi_i32);
- op->args[1] = (uintptr_t)ptr;
+ /* mov_i32 */
+ op = copy_op(begin_op, op, INDEX_op_mov_i32);
+ op->args[1] = tcgv_i32_arg(tcg_constant_i32((uintptr_t)ptr));
} else {
- /* movi_i64 */
- op = copy_movi_i64(begin_op, op, (uint64_t)(uintptr_t)ptr);
+ /* mov_i64 */
+ op = copy_op(begin_op, op, INDEX_op_mov_i64);
+ op->args[1] = tcgv_i64_arg(tcg_constant_i64((uintptr_t)ptr));
}
return op;
}
static TCGOp *copy_const_i64(TCGOp **begin_op, TCGOp *op, uint64_t v)
{
- return copy_movi_i64(begin_op, op, v);
+ if (TCG_TARGET_REG_BITS == 32) {
+ /* 2x mov_i32 */
+ op = copy_op(begin_op, op, INDEX_op_mov_i32);
+ op->args[1] = tcgv_i32_arg(tcg_constant_i32(v));
+ op = copy_op(begin_op, op, INDEX_op_mov_i32);
+ op->args[1] = tcgv_i32_arg(tcg_constant_i32(v >> 32));
+ } else {
+ /* mov_i64 */
+ op = copy_op(begin_op, op, INDEX_op_mov_i64);
+ op->args[1] = tcgv_i64_arg(tcg_constant_i64(v));
+ }
+ return op;
}
static TCGOp *copy_extu_tl_i64(TCGOp **begin_op, TCGOp *op)
@@ -486,8 +481,8 @@ static TCGOp *append_mem_cb(const struct qemu_plugin_dyn_cb *cb,
tcg_debug_assert(type == PLUGIN_GEN_CB_MEM);
- /* const_i32 == movi_i32 ("info", so it remains as is) */
- op = copy_op(&begin_op, op, INDEX_op_movi_i32);
+ /* const_i32 == mov_i32 ("info", so it remains as is) */
+ op = copy_op(&begin_op, op, INDEX_op_mov_i32);
/* const_ptr */
op = copy_const_ptr(&begin_op, op, cb->userp);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 26/43] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (24 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 25/43] tcg: Use tcg_constant_{i32,i64} with tcg plugins Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 27/43] tcg/tci: Add special tci_movi_{i32,i64} opcodes Richard Henderson
` (16 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 1 +
tcg/tcg-op-gvec.c | 125 ++++++++++++++++++----------------------------
tcg/tcg.c | 8 +++
3 files changed, 58 insertions(+), 76 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index aa7b0ba163..309460704a 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -1081,6 +1081,7 @@ static inline TCGv_i64 tcg_constant_i64(int64_t val)
}
TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val);
+TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val);
#if UINTPTR_MAX == UINT32_MAX
# define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index ddbe06b71a..80eb53c770 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -115,7 +115,7 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
gen_helper_gvec_2 *fn)
{
TCGv_ptr a0, a1;
- TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data));
a0 = tcg_temp_new_ptr();
a1 = tcg_temp_new_ptr();
@@ -127,7 +127,6 @@ void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs,
tcg_temp_free_ptr(a0);
tcg_temp_free_ptr(a1);
- tcg_temp_free_i32(desc);
}
/* Generate a call to a gvec-style helper with two vector operands
@@ -137,7 +136,7 @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
gen_helper_gvec_2i *fn)
{
TCGv_ptr a0, a1;
- TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data));
a0 = tcg_temp_new_ptr();
a1 = tcg_temp_new_ptr();
@@ -149,7 +148,6 @@ void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c,
tcg_temp_free_ptr(a0);
tcg_temp_free_ptr(a1);
- tcg_temp_free_i32(desc);
}
/* Generate a call to a gvec-style helper with three vector operands. */
@@ -158,7 +156,7 @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
gen_helper_gvec_3 *fn)
{
TCGv_ptr a0, a1, a2;
- TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data));
a0 = tcg_temp_new_ptr();
a1 = tcg_temp_new_ptr();
@@ -173,7 +171,6 @@ void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
tcg_temp_free_ptr(a0);
tcg_temp_free_ptr(a1);
tcg_temp_free_ptr(a2);
- tcg_temp_free_i32(desc);
}
/* Generate a call to a gvec-style helper with four vector operands. */
@@ -182,7 +179,7 @@ void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
int32_t data, gen_helper_gvec_4 *fn)
{
TCGv_ptr a0, a1, a2, a3;
- TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data));
a0 = tcg_temp_new_ptr();
a1 = tcg_temp_new_ptr();
@@ -200,7 +197,6 @@ void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
tcg_temp_free_ptr(a1);
tcg_temp_free_ptr(a2);
tcg_temp_free_ptr(a3);
- tcg_temp_free_i32(desc);
}
/* Generate a call to a gvec-style helper with five vector operands. */
@@ -209,7 +205,7 @@ void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn)
{
TCGv_ptr a0, a1, a2, a3, a4;
- TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data));
a0 = tcg_temp_new_ptr();
a1 = tcg_temp_new_ptr();
@@ -230,7 +226,6 @@ void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs,
tcg_temp_free_ptr(a2);
tcg_temp_free_ptr(a3);
tcg_temp_free_ptr(a4);
- tcg_temp_free_i32(desc);
}
/* Generate a call to a gvec-style helper with three vector operands
@@ -240,7 +235,7 @@ void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
int32_t data, gen_helper_gvec_2_ptr *fn)
{
TCGv_ptr a0, a1;
- TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data));
a0 = tcg_temp_new_ptr();
a1 = tcg_temp_new_ptr();
@@ -252,7 +247,6 @@ void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs,
tcg_temp_free_ptr(a0);
tcg_temp_free_ptr(a1);
- tcg_temp_free_i32(desc);
}
/* Generate a call to a gvec-style helper with three vector operands
@@ -262,7 +256,7 @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
int32_t data, gen_helper_gvec_3_ptr *fn)
{
TCGv_ptr a0, a1, a2;
- TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data));
a0 = tcg_temp_new_ptr();
a1 = tcg_temp_new_ptr();
@@ -277,7 +271,6 @@ void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
tcg_temp_free_ptr(a0);
tcg_temp_free_ptr(a1);
tcg_temp_free_ptr(a2);
- tcg_temp_free_i32(desc);
}
/* Generate a call to a gvec-style helper with four vector operands
@@ -288,7 +281,7 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
gen_helper_gvec_4_ptr *fn)
{
TCGv_ptr a0, a1, a2, a3;
- TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data));
a0 = tcg_temp_new_ptr();
a1 = tcg_temp_new_ptr();
@@ -306,7 +299,6 @@ void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
tcg_temp_free_ptr(a1);
tcg_temp_free_ptr(a2);
tcg_temp_free_ptr(a3);
- tcg_temp_free_i32(desc);
}
/* Generate a call to a gvec-style helper with five vector operands
@@ -317,7 +309,7 @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
gen_helper_gvec_5_ptr *fn)
{
TCGv_ptr a0, a1, a2, a3, a4;
- TCGv_i32 desc = tcg_const_i32(simd_desc(oprsz, maxsz, data));
+ TCGv_i32 desc = tcg_constant_i32(simd_desc(oprsz, maxsz, data));
a0 = tcg_temp_new_ptr();
a1 = tcg_temp_new_ptr();
@@ -338,7 +330,6 @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs,
tcg_temp_free_ptr(a2);
tcg_temp_free_ptr(a3);
tcg_temp_free_ptr(a4);
- tcg_temp_free_i32(desc);
}
/* Return true if we want to implement something of OPRSZ bytes
@@ -602,9 +593,9 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
|| (TCG_TARGET_REG_BITS == 64
&& (in_c == 0 || in_c == -1
|| !check_size_impl(oprsz, 4)))) {
- t_64 = tcg_const_i64(in_c);
+ t_64 = tcg_constant_i64(in_c);
} else {
- t_32 = tcg_const_i32(in_c);
+ t_32 = tcg_constant_i32(in_c);
}
}
@@ -628,15 +619,14 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
/* Otherwise implement out of line. */
t_ptr = tcg_temp_new_ptr();
tcg_gen_addi_ptr(t_ptr, cpu_env, dofs);
- t_desc = tcg_const_i32(simd_desc(oprsz, maxsz, 0));
+ t_desc = tcg_constant_i32(simd_desc(oprsz, maxsz, 0));
if (vece == MO_64) {
if (in_64) {
gen_helper_gvec_dup64(t_ptr, t_desc, in_64);
} else {
- t_64 = tcg_const_i64(in_c);
+ t_64 = tcg_constant_i64(in_c);
gen_helper_gvec_dup64(t_ptr, t_desc, t_64);
- tcg_temp_free_i64(t_64);
}
} else {
typedef void dup_fn(TCGv_ptr, TCGv_i32, TCGv_i32);
@@ -648,24 +638,23 @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz,
if (in_32) {
fns[vece](t_ptr, t_desc, in_32);
- } else {
+ } else if (in_64) {
t_32 = tcg_temp_new_i32();
- if (in_64) {
- tcg_gen_extrl_i64_i32(t_32, in_64);
- } else if (vece == MO_8) {
- tcg_gen_movi_i32(t_32, in_c & 0xff);
- } else if (vece == MO_16) {
- tcg_gen_movi_i32(t_32, in_c & 0xffff);
- } else {
- tcg_gen_movi_i32(t_32, in_c);
- }
+ tcg_gen_extrl_i64_i32(t_32, in_64);
fns[vece](t_ptr, t_desc, t_32);
tcg_temp_free_i32(t_32);
+ } else {
+ if (vece == MO_8) {
+ in_c &= 0xff;
+ } else if (vece == MO_16) {
+ in_c &= 0xffff;
+ }
+ t_32 = tcg_constant_i32(in_c);
+ fns[vece](t_ptr, t_desc, t_32);
}
}
tcg_temp_free_ptr(t_ptr);
- tcg_temp_free_i32(t_desc);
return;
done:
@@ -1215,10 +1204,9 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
if (g->fno) {
tcg_gen_gvec_2_ool(dofs, aofs, oprsz, maxsz, c, g->fno);
} else {
- TCGv_i64 tcg_c = tcg_const_i64(c);
+ TCGv_i64 tcg_c = tcg_constant_i64(c);
tcg_gen_gvec_2i_ool(dofs, aofs, tcg_c, oprsz,
maxsz, c, g->fnoi);
- tcg_temp_free_i64(tcg_c);
}
oprsz = maxsz;
}
@@ -1712,16 +1700,14 @@ static void gen_addv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
- TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));
+ TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80));
gen_addv_mask(d, a, b, m);
- tcg_temp_free_i64(m);
}
void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
- TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));
+ TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000));
gen_addv_mask(d, a, b, m);
- tcg_temp_free_i64(m);
}
void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
@@ -1805,9 +1791,8 @@ void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t c, uint32_t oprsz, uint32_t maxsz)
{
- TCGv_i64 tmp = tcg_const_i64(c);
+ TCGv_i64 tmp = tcg_constant_i64(c);
tcg_gen_gvec_adds(vece, dofs, aofs, tmp, oprsz, maxsz);
- tcg_temp_free_i64(tmp);
}
static const TCGOpcode vecop_list_sub[] = { INDEX_op_sub_vec, 0 };
@@ -1865,16 +1850,14 @@ static void gen_subv_mask(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b, TCGv_i64 m)
void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
- TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));
+ TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80));
gen_subv_mask(d, a, b, m);
- tcg_temp_free_i64(m);
}
void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
- TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));
+ TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000));
gen_subv_mask(d, a, b, m);
- tcg_temp_free_i64(m);
}
void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
@@ -1985,9 +1968,8 @@ void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t c, uint32_t oprsz, uint32_t maxsz)
{
- TCGv_i64 tmp = tcg_const_i64(c);
+ TCGv_i64 tmp = tcg_constant_i64(c);
tcg_gen_gvec_muls(vece, dofs, aofs, tmp, oprsz, maxsz);
- tcg_temp_free_i64(tmp);
}
void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -2044,18 +2026,16 @@ void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs,
static void tcg_gen_usadd_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
- TCGv_i32 max = tcg_const_i32(-1);
+ TCGv_i32 max = tcg_constant_i32(-1);
tcg_gen_add_i32(d, a, b);
tcg_gen_movcond_i32(TCG_COND_LTU, d, d, a, max, d);
- tcg_temp_free_i32(max);
}
static void tcg_gen_usadd_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
- TCGv_i64 max = tcg_const_i64(-1);
+ TCGv_i64 max = tcg_constant_i64(-1);
tcg_gen_add_i64(d, a, b);
tcg_gen_movcond_i64(TCG_COND_LTU, d, d, a, max, d);
- tcg_temp_free_i64(max);
}
void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -2088,18 +2068,16 @@ void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs,
static void tcg_gen_ussub_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
{
- TCGv_i32 min = tcg_const_i32(0);
+ TCGv_i32 min = tcg_constant_i32(0);
tcg_gen_sub_i32(d, a, b);
tcg_gen_movcond_i32(TCG_COND_LTU, d, a, b, min, d);
- tcg_temp_free_i32(min);
}
static void tcg_gen_ussub_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
{
- TCGv_i64 min = tcg_const_i64(0);
+ TCGv_i64 min = tcg_constant_i64(0);
tcg_gen_sub_i64(d, a, b);
tcg_gen_movcond_i64(TCG_COND_LTU, d, a, b, min, d);
- tcg_temp_free_i64(min);
}
void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs,
@@ -2260,16 +2238,14 @@ static void gen_negv_mask(TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 b)
{
- TCGv_i64 m = tcg_const_i64(dup_const(MO_8, 0x80));
+ TCGv_i64 m = tcg_constant_i64(dup_const(MO_8, 0x80));
gen_negv_mask(d, b, m);
- tcg_temp_free_i64(m);
}
void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 b)
{
- TCGv_i64 m = tcg_const_i64(dup_const(MO_16, 0x8000));
+ TCGv_i64 m = tcg_constant_i64(dup_const(MO_16, 0x8000));
gen_negv_mask(d, b, m);
- tcg_temp_free_i64(m);
}
void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 b)
@@ -2538,9 +2514,8 @@ void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t c, uint32_t oprsz, uint32_t maxsz)
{
- TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c));
+ TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c));
tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands);
- tcg_temp_free_i64(tmp);
}
static const GVecGen2s gop_xors = {
@@ -2563,9 +2538,8 @@ void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t c, uint32_t oprsz, uint32_t maxsz)
{
- TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c));
+ TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c));
tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors);
- tcg_temp_free_i64(tmp);
}
static const GVecGen2s gop_ors = {
@@ -2588,9 +2562,8 @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs,
void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs,
int64_t c, uint32_t oprsz, uint32_t maxsz)
{
- TCGv_i64 tmp = tcg_const_i64(dup_const(vece, c));
+ TCGv_i64 tmp = tcg_constant_i64(dup_const(vece, c));
tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors);
- tcg_temp_free_i64(tmp);
}
void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c)
@@ -3078,9 +3051,9 @@ static void tcg_gen_shlv_mod_vec(unsigned vece, TCGv_vec d,
TCGv_vec a, TCGv_vec b)
{
TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1);
- tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
- tcg_gen_and_vec(vece, t, t, b);
+ tcg_gen_and_vec(vece, t, b, m);
tcg_gen_shlv_vec(vece, d, a, t);
tcg_temp_free_vec(t);
}
@@ -3141,9 +3114,9 @@ static void tcg_gen_shrv_mod_vec(unsigned vece, TCGv_vec d,
TCGv_vec a, TCGv_vec b)
{
TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1);
- tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
- tcg_gen_and_vec(vece, t, t, b);
+ tcg_gen_and_vec(vece, t, b, m);
tcg_gen_shrv_vec(vece, d, a, t);
tcg_temp_free_vec(t);
}
@@ -3204,9 +3177,9 @@ static void tcg_gen_sarv_mod_vec(unsigned vece, TCGv_vec d,
TCGv_vec a, TCGv_vec b)
{
TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1);
- tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
- tcg_gen_and_vec(vece, t, t, b);
+ tcg_gen_and_vec(vece, t, b, m);
tcg_gen_sarv_vec(vece, d, a, t);
tcg_temp_free_vec(t);
}
@@ -3267,9 +3240,9 @@ static void tcg_gen_rotlv_mod_vec(unsigned vece, TCGv_vec d,
TCGv_vec a, TCGv_vec b)
{
TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1);
- tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
- tcg_gen_and_vec(vece, t, t, b);
+ tcg_gen_and_vec(vece, t, b, m);
tcg_gen_rotlv_vec(vece, d, a, t);
tcg_temp_free_vec(t);
}
@@ -3326,9 +3299,9 @@ static void tcg_gen_rotrv_mod_vec(unsigned vece, TCGv_vec d,
TCGv_vec a, TCGv_vec b)
{
TCGv_vec t = tcg_temp_new_vec_matching(d);
+ TCGv_vec m = tcg_constant_vec_matching(d, vece, (8 << vece) - 1);
- tcg_gen_dupi_vec(vece, t, (8 << vece) - 1);
- tcg_gen_and_vec(vece, t, t, b);
+ tcg_gen_and_vec(vece, t, b, m);
tcg_gen_rotrv_vec(vece, d, a, t);
tcg_temp_free_vec(t);
}
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 0ce45fd123..b63da0b603 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1416,6 +1416,14 @@ TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val)
return temp_tcgv_vec(tcg_constant_internal(type, val));
}
+TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val)
+{
+ TCGTemp *t = tcgv_vec_temp(match);
+
+ tcg_debug_assert(t->temp_allocated != 0);
+ return tcg_constant_vec(t->base_type, vece, val);
+}
+
TCGv_i32 tcg_const_i32(int32_t val)
{
TCGv_i32 t0;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 27/43] tcg/tci: Add special tci_movi_{i32,i64} opcodes
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (25 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 26/43] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 28/43] tcg: Remove movi and dupi opcodes Richard Henderson
` (15 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
The normal movi opcodes are going away. We need something
for TCI to use internally.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-opc.h | 8 ++++++++
tcg/tci.c | 4 ++--
tcg/tci/tcg-target.c.inc | 4 ++--
3 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index e3929b80d2..5a941eaa07 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -272,6 +272,14 @@ DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
#include "tcg-target.opc.h"
#endif
+#ifdef TCG_TARGET_INTERPRETER
+/* These opcodes are only for use between the tci generator and interpreter. */
+DEF(tci_movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
+#if TCG_TARGET_REG_BITS == 64
+DEF(tci_movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
+#endif
+#endif
+
#undef TLADDR_ARGS
#undef DATA64_ARGS
#undef IMPL
diff --git a/tcg/tci.c b/tcg/tci.c
index 46fe9ce63f..a6c1aaf5af 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -576,7 +576,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
t1 = tci_read_r32(regs, &tb_ptr);
tci_write_reg32(regs, t0, t1);
break;
- case INDEX_op_movi_i32:
+ case INDEX_op_tci_movi_i32:
t0 = *tb_ptr++;
t1 = tci_read_i32(&tb_ptr);
tci_write_reg32(regs, t0, t1);
@@ -847,7 +847,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
t1 = tci_read_r64(regs, &tb_ptr);
tci_write_reg64(regs, t0, t1);
break;
- case INDEX_op_movi_i64:
+ case INDEX_op_tci_movi_i64:
t0 = *tb_ptr++;
t1 = tci_read_i64(&tb_ptr);
tci_write_reg64(regs, t0, t1);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 231b9b1775..c8c8386a72 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -529,13 +529,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
uint8_t *old_code_ptr = s->code_ptr;
uint32_t arg32 = arg;
if (type == TCG_TYPE_I32 || arg == arg32) {
- tcg_out_op_t(s, INDEX_op_movi_i32);
+ tcg_out_op_t(s, INDEX_op_tci_movi_i32);
tcg_out_r(s, t0);
tcg_out32(s, arg32);
} else {
tcg_debug_assert(type == TCG_TYPE_I64);
#if TCG_TARGET_REG_BITS == 64
- tcg_out_op_t(s, INDEX_op_movi_i64);
+ tcg_out_op_t(s, INDEX_op_tci_movi_i64);
tcg_out_r(s, t0);
tcg_out64(s, arg);
#else
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 28/43] tcg: Remove movi and dupi opcodes
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (26 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 27/43] tcg/tci: Add special tci_movi_{i32,i64} opcodes Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 29/43] tcg: Add tcg_reg_alloc_dup2 Richard Henderson
` (14 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Markovic, Alex Bennée
These are now completely covered by mov from a
TYPE_CONST temporary.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-opc.h | 3 ---
tcg/optimize.c | 4 ----
tcg/tcg-op-vec.c | 1 -
tcg/tcg.c | 18 +-----------------
tcg/aarch64/tcg-target.c.inc | 3 ---
tcg/arm/tcg-target.c.inc | 1 -
tcg/i386/tcg-target.c.inc | 3 ---
tcg/mips/tcg-target.c.inc | 2 --
tcg/ppc/tcg-target.c.inc | 3 ---
tcg/riscv/tcg-target.c.inc | 2 --
tcg/s390/tcg-target.c.inc | 2 --
tcg/sparc/tcg-target.c.inc | 2 --
tcg/tci/tcg-target.c.inc | 2 --
13 files changed, 1 insertion(+), 45 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 5a941eaa07..d63c6bcb3d 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -45,7 +45,6 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END)
DEF(mb, 0, 0, 1, 0)
DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
-DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
DEF(setcond_i32, 1, 2, 1, 0)
DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
/* load/store */
@@ -110,7 +109,6 @@ DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
-DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
DEF(setcond_i64, 1, 2, 1, IMPL64)
DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
/* load/store */
@@ -215,7 +213,6 @@ DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
#define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)
DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
-DEF(dupi_vec, 1, 0, 1, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT)
DEF(dup_vec, 1, 1, 0, IMPLVEC)
DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32))
diff --git a/tcg/optimize.c b/tcg/optimize.c
index af07c6f628..1a94e9a41b 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -1099,10 +1099,6 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64_VEC(mov):
tcg_opt_gen_mov(s, op, op->args[0], op->args[1]);
break;
- CASE_OP_32_64(movi):
- case INDEX_op_dupi_vec:
- tcg_opt_gen_movi(s, &temps_used, op, op->args[0], op->args[1]);
- break;
case INDEX_op_dup_vec:
if (arg_is_const(op->args[1])) {
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index 9fbed1366c..ce0d2f6e0e 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -83,7 +83,6 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list,
case INDEX_op_xor_vec:
case INDEX_op_mov_vec:
case INDEX_op_dup_vec:
- case INDEX_op_dupi_vec:
case INDEX_op_dup2_vec:
case INDEX_op_ld_vec:
case INDEX_op_st_vec:
diff --git a/tcg/tcg.c b/tcg/tcg.c
index b63da0b603..f9c6450837 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1503,7 +1503,6 @@ bool tcg_op_supported(TCGOpcode op)
return TCG_TARGET_HAS_goto_ptr;
case INDEX_op_mov_i32:
- case INDEX_op_movi_i32:
case INDEX_op_setcond_i32:
case INDEX_op_brcond_i32:
case INDEX_op_ld8u_i32:
@@ -1597,7 +1596,6 @@ bool tcg_op_supported(TCGOpcode op)
return TCG_TARGET_REG_BITS == 32;
case INDEX_op_mov_i64:
- case INDEX_op_movi_i64:
case INDEX_op_setcond_i64:
case INDEX_op_brcond_i64:
case INDEX_op_ld8u_i64:
@@ -1703,7 +1701,6 @@ bool tcg_op_supported(TCGOpcode op)
case INDEX_op_mov_vec:
case INDEX_op_dup_vec:
- case INDEX_op_dupi_vec:
case INDEX_op_dupm_vec:
case INDEX_op_ld_vec:
case INDEX_op_st_vec:
@@ -3542,7 +3539,7 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
}
/*
- * Specialized code generation for INDEX_op_movi_*.
+ * Specialized code generation for INDEX_op_mov_* with a constant.
*/
static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
tcg_target_ulong val, TCGLifeData arg_life,
@@ -3565,14 +3562,6 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots,
}
}
-static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op)
-{
- TCGTemp *ots = arg_temp(op->args[0]);
- tcg_target_ulong val = op->args[1];
-
- tcg_reg_alloc_do_movi(s, ots, val, op->life, op->output_pref[0]);
-}
-
/*
* Specialized code generation for INDEX_op_mov_*.
*/
@@ -4353,11 +4342,6 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
case INDEX_op_mov_vec:
tcg_reg_alloc_mov(s, op);
break;
- case INDEX_op_movi_i32:
- case INDEX_op_movi_i64:
- case INDEX_op_dupi_vec:
- tcg_reg_alloc_movi(s, op);
- break;
case INDEX_op_dup_vec:
tcg_reg_alloc_dup(s, op);
break;
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 5692607087..fdc118391c 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2252,8 +2252,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
g_assert_not_reached();
@@ -2461,7 +2459,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
- case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
g_assert_not_reached();
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 62c37a954b..30d30874c7 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -2065,7 +2065,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 6b7cbaa47a..819ee25cff 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2692,8 +2692,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
@@ -2979,7 +2977,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
- case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
g_assert_not_reached();
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 98c6a41caf..3e282c1bde 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2152,8 +2152,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index ff56f1971f..3d23a6b226 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2973,8 +2973,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
@@ -3322,7 +3320,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
return;
case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
- case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
default:
g_assert_not_reached();
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index d536f3ccc1..aaef1c5eed 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1602,8 +1602,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
g_assert_not_reached();
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index c5e096449b..824a07aa7a 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -2306,8 +2306,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index 44373d742b..af480115c5 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -1586,8 +1586,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index c8c8386a72..25ed868505 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -814,8 +814,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:
- case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
- case INDEX_op_movi_i64:
case INDEX_op_call: /* Always emitted via tcg_out_call. */
default:
tcg_abort();
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 29/43] tcg: Add tcg_reg_alloc_dup2
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (27 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 28/43] tcg: Remove movi and dupi opcodes Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 30/43] tcg/i386: Use tcg_constant_vec with tcg vec expanders Richard Henderson
` (13 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
There are several ways we can expand a vector dup of a 64-bit
element on a 32-bit host.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f9c6450837..507c95cd39 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3954,6 +3954,100 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
}
+static void tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op)
+{
+ const TCGLifeData arg_life = op->life;
+ TCGTemp *ots, *itsl, *itsh;
+ TCGType vtype = TCGOP_VECL(op) + TCG_TYPE_V64;
+
+ /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
+ tcg_debug_assert(TCGOP_VECE(op) == MO_64);
+
+ ots = arg_temp(op->args[0]);
+ itsl = arg_temp(op->args[1]);
+ itsh = arg_temp(op->args[2]);
+
+ /* ENV should not be modified. */
+ tcg_debug_assert(!temp_readonly(ots));
+
+ /* Allocate the output register now. */
+ if (ots->val_type != TEMP_VAL_REG) {
+ TCGRegSet allocated_regs = s->reserved_regs;
+ TCGRegSet dup_out_regs =
+ tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
+
+ /* Make sure to not spill the input registers. */
+ if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) {
+ tcg_regset_set_reg(allocated_regs, itsl->reg);
+ }
+ if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) {
+ tcg_regset_set_reg(allocated_regs, itsh->reg);
+ }
+
+ ots->reg = tcg_reg_alloc(s, dup_out_regs, allocated_regs,
+ op->output_pref[0], ots->indirect_base);
+ ots->val_type = TEMP_VAL_REG;
+ ots->mem_coherent = 0;
+ s->reg_to_temp[ots->reg] = ots;
+ }
+
+ /* Promote dup2 of immediates to dupi_vec. */
+ if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) {
+ uint64_t val = deposit64(itsl->val, 32, 32, itsh->val);
+ MemOp vece = MO_64;
+
+ if (val == dup_const(MO_8, val)) {
+ vece = MO_8;
+ } else if (val == dup_const(MO_16, val)) {
+ vece = MO_16;
+ } else if (val == dup_const(MO_32, val)) {
+ vece = MO_32;
+ }
+
+ tcg_out_dupi_vec(s, vtype, vece, ots->reg, val);
+ goto done;
+ }
+
+ /* If the two inputs form one 64-bit value, try dupm_vec. */
+ if (itsl + 1 == itsh &&
+ itsl->base_type == TCG_TYPE_I64 &&
+ itsh->base_type == TCG_TYPE_I64) {
+ if (!itsl->mem_coherent) {
+ temp_sync(s, itsl, s->reserved_regs, 0, 0);
+ }
+ if (!itsl->mem_coherent) {
+ temp_sync(s, itsl, s->reserved_regs, 0, 0);
+ }
+#ifdef HOST_WORDS_BIGENDIAN
+ TCGTemp *its = itsh;
+#else
+ TCGTemp *its = itsl;
+#endif
+ if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg,
+ its->mem_base->reg, its->mem_offset)) {
+ goto done;
+ }
+ }
+
+ /* Fall back to generic expansion. */
+ tcg_reg_alloc_op(s, op);
+ return;
+
+ done:
+ if (IS_DEAD_ARG(1)) {
+ temp_dead(s, itsl);
+ }
+ if (IS_DEAD_ARG(2)) {
+ temp_dead(s, itsh);
+ }
+ if (NEED_SYNC_ARG(0)) {
+ temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0));
+ } else if (IS_DEAD_ARG(0)) {
+ temp_dead(s, ots);
+ }
+}
+
#ifdef TCG_TARGET_STACK_GROWSUP
#define STACK_DIR(x) (-(x))
#else
@@ -4345,6 +4439,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
case INDEX_op_dup_vec:
tcg_reg_alloc_dup(s, op);
break;
+ case INDEX_op_dup2_vec:
+ tcg_reg_alloc_dup2(s, op);
+ break;
case INDEX_op_insn_start:
if (num_insns >= 0) {
size_t off = tcg_current_code_size(s);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 30/43] tcg/i386: Use tcg_constant_vec with tcg vec expanders
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (28 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 29/43] tcg: Add tcg_reg_alloc_dup2 Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 31/43] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec Richard Henderson
` (12 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 819ee25cff..36a90e7ef3 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -3508,7 +3508,7 @@ static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
static void expand_vec_mul(TCGType type, unsigned vece,
TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
{
- TCGv_vec t1, t2, t3, t4;
+ TCGv_vec t1, t2, t3, t4, zero;
tcg_debug_assert(vece == MO_8);
@@ -3526,11 +3526,11 @@ static void expand_vec_mul(TCGType type, unsigned vece,
case TCG_TYPE_V64:
t1 = tcg_temp_new_vec(TCG_TYPE_V128);
t2 = tcg_temp_new_vec(TCG_TYPE_V128);
- tcg_gen_dup16i_vec(t2, 0);
+ zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0);
vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
- tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t2));
+ tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero));
vec_gen_3(INDEX_op_x86_punpckl_vec, TCG_TYPE_V128, MO_8,
- tcgv_vec_arg(t2), tcgv_vec_arg(t2), tcgv_vec_arg(v2));
+ tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2));
tcg_gen_mul_vec(MO_16, t1, t1, t2);
tcg_gen_shri_vec(MO_16, t1, t1, 8);
vec_gen_3(INDEX_op_x86_packus_vec, TCG_TYPE_V128, MO_8,
@@ -3545,15 +3545,15 @@ static void expand_vec_mul(TCGType type, unsigned vece,
t2 = tcg_temp_new_vec(type);
t3 = tcg_temp_new_vec(type);
t4 = tcg_temp_new_vec(type);
- tcg_gen_dup16i_vec(t4, 0);
+ zero = tcg_constant_vec(TCG_TYPE_V128, MO_8, 0);
vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
- tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(t4));
+ tcgv_vec_arg(t1), tcgv_vec_arg(v1), tcgv_vec_arg(zero));
vec_gen_3(INDEX_op_x86_punpckl_vec, type, MO_8,
- tcgv_vec_arg(t2), tcgv_vec_arg(t4), tcgv_vec_arg(v2));
+ tcgv_vec_arg(t2), tcgv_vec_arg(zero), tcgv_vec_arg(v2));
vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
- tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(t4));
+ tcgv_vec_arg(t3), tcgv_vec_arg(v1), tcgv_vec_arg(zero));
vec_gen_3(INDEX_op_x86_punpckh_vec, type, MO_8,
- tcgv_vec_arg(t4), tcgv_vec_arg(t4), tcgv_vec_arg(v2));
+ tcgv_vec_arg(t4), tcgv_vec_arg(zero), tcgv_vec_arg(v2));
tcg_gen_mul_vec(MO_16, t1, t1, t2);
tcg_gen_mul_vec(MO_16, t3, t3, t4);
tcg_gen_shri_vec(MO_16, t1, t1, 8);
@@ -3581,7 +3581,7 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
NEED_UMIN = 8,
NEED_UMAX = 16,
};
- TCGv_vec t1, t2;
+ TCGv_vec t1, t2, t3;
uint8_t fixup;
switch (cond) {
@@ -3652,9 +3652,9 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
} else if (fixup & NEED_BIAS) {
t1 = tcg_temp_new_vec(type);
t2 = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(vece, t2, 1ull << ((8 << vece) - 1));
- tcg_gen_sub_vec(vece, t1, v1, t2);
- tcg_gen_sub_vec(vece, t2, v2, t2);
+ t3 = tcg_constant_vec(type, vece, 1ull << ((8 << vece) - 1));
+ tcg_gen_sub_vec(vece, t1, v1, t3);
+ tcg_gen_sub_vec(vece, t2, v2, t3);
v1 = t1;
v2 = t2;
cond = tcg_signed_cond(cond);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 31/43] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (29 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 30/43] tcg/i386: Use tcg_constant_vec with tcg vec expanders Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 32/43] tcg/ppc: Use tcg_constant_vec with tcg vec expanders Richard Henderson
` (11 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel; +Cc: Alex Bennée
These interfaces have been replaced by tcg_gen_dupi_vec
and tcg_constant_vec.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op.h | 4 ----
tcg/tcg-op-vec.c | 20 --------------------
2 files changed, 24 deletions(-)
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index b4fba35e87..d0319692ec 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -959,10 +959,6 @@ void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long);
-void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
-void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
-void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
-void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index ce0d2f6e0e..d19aa7373e 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -241,26 +241,6 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
return tcg_const_ones_vec(t->base_type);
}
-void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
-{
- tcg_gen_dupi_vec(MO_64, r, a);
-}
-
-void tcg_gen_dup32i_vec(TCGv_vec r, uint32_t a)
-{
- tcg_gen_dupi_vec(MO_32, r, a);
-}
-
-void tcg_gen_dup16i_vec(TCGv_vec r, uint32_t a)
-{
- tcg_gen_dupi_vec(MO_16, r, a);
-}
-
-void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
-{
- tcg_gen_dupi_vec(MO_8, r, a);
-}
-
void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
{
TCGTemp *rt = tcgv_vec_temp(r);
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 32/43] tcg/ppc: Use tcg_constant_vec with tcg vec expanders
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (30 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 31/43] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 33/43] tcg/aarch64: " Richard Henderson
` (10 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Improve expand_vec_shi to use sign-extraction for MO_32.
This allows a single VSPLTISB instruction to load all of
the valid shift constants.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 44 ++++++++++++++++++++++++----------------
1 file changed, 27 insertions(+), 17 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 3d23a6b226..155c42ed24 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -3332,13 +3332,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
TCGv_vec v1, TCGArg imm, TCGOpcode opci)
{
- TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t1;
- /* Splat w/bytes for xxspltib. */
- tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1));
+ if (vece == MO_32) {
+ /*
+ * Only 5 bits are significant, and VSPLTISB can represent -16..15.
+ * So using negative numbers gets us the 4th bit easily.
+ */
+ imm = sextract32(imm, 0, 5);
+ } else {
+ imm &= (8 << vece) - 1;
+ }
+
+ /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */
+ t1 = tcg_constant_vec(type, MO_8, imm);
vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
tcgv_vec_arg(v1), tcgv_vec_arg(t1));
- tcg_temp_free_vec(t1);
}
static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
@@ -3396,7 +3405,7 @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
{
TCGv_vec t1 = tcg_temp_new_vec(type);
TCGv_vec t2 = tcg_temp_new_vec(type);
- TCGv_vec t3, t4;
+ TCGv_vec c0, c16;
switch (vece) {
case MO_8:
@@ -3415,21 +3424,22 @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
case MO_32:
tcg_debug_assert(!have_isa_2_07);
- t3 = tcg_temp_new_vec(type);
- t4 = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(MO_8, t4, -16);
+ /*
+ * Only 5 bits are significant, and VSPLTISB can represent -16..15.
+ * So using -16 is a quick way to represent 16.
+ */
+ c16 = tcg_constant_vec(type, MO_8, -16);
+ c0 = tcg_constant_vec(type, MO_8, 0);
+
vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1),
- tcgv_vec_arg(v2), tcgv_vec_arg(t4));
+ tcgv_vec_arg(v2), tcgv_vec_arg(c16));
vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
tcgv_vec_arg(v1), tcgv_vec_arg(v2));
- tcg_gen_dupi_vec(MO_8, t3, 0);
- vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3),
- tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3));
- vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3),
- tcgv_vec_arg(t3), tcgv_vec_arg(t4));
- tcg_gen_add_vec(MO_32, v0, t2, t3);
- tcg_temp_free_vec(t3);
- tcg_temp_free_vec(t4);
+ vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0));
+ vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1),
+ tcgv_vec_arg(t1), tcgv_vec_arg(c16));
+ tcg_gen_add_vec(MO_32, v0, t1, t2);
break;
default:
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 33/43] tcg/aarch64: Use tcg_constant_vec with tcg vec expanders
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (31 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 32/43] tcg/ppc: Use tcg_constant_vec with tcg vec expanders Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 34/43] tcg: Add tcg-constr.c.inc Richard Henderson
` (9 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Improve rotrv_vec to reduce "t1 = -v2, t2 = t1 + c" to
"t1 = -v, t2 = c - v2". This avoids a serial dependency
between t1 and t2.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.c.inc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index fdc118391c..d9d397075a 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2511,7 +2511,7 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...)
{
va_list va;
- TCGv_vec v0, v1, v2, t1, t2;
+ TCGv_vec v0, v1, v2, t1, t2, c1;
TCGArg a2;
va_start(va, a0);
@@ -2543,8 +2543,8 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
case INDEX_op_rotlv_vec:
t1 = tcg_temp_new_vec(type);
- tcg_gen_dupi_vec(vece, t1, 8 << vece);
- tcg_gen_sub_vec(vece, t1, v2, t1);
+ c1 = tcg_constant_vec(type, vece, 8 << vece);
+ tcg_gen_sub_vec(vece, t1, v2, c1);
/* Right shifts are negative left shifts for AArch64. */
vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
tcgv_vec_arg(v1), tcgv_vec_arg(t1));
@@ -2557,9 +2557,9 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
case INDEX_op_rotrv_vec:
t1 = tcg_temp_new_vec(type);
t2 = tcg_temp_new_vec(type);
+ c1 = tcg_constant_vec(type, vece, 8 << vece);
tcg_gen_neg_vec(vece, t1, v2);
- tcg_gen_dupi_vec(vece, t2, 8 << vece);
- tcg_gen_add_vec(vece, t2, t1, t2);
+ tcg_gen_sub_vec(vece, t2, c1, v2);
/* Right shifts are negative left shifts for AArch64. */
vec_gen_3(INDEX_op_shlv_vec, type, vece, tcgv_vec_arg(t1),
tcgv_vec_arg(v1), tcgv_vec_arg(t1));
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 34/43] tcg: Add tcg-constr.c.inc
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (32 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 33/43] tcg/aarch64: " Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 35/43] tcg/i386: Convert to tcg-constr.c.inc Richard Henderson
` (8 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Begin conversion of constraints to pre-validated, read-only entities.
To begin, create a simple method by which sets of TCGTargetOpDef
structures may be declared and used. This simplifies each host's
tcg_target_op_def function and ensures that we have a collected
set of constraints.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-constr.c.inc | 108 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 108 insertions(+)
create mode 100644 tcg/tcg-constr.c.inc
diff --git a/tcg/tcg-constr.c.inc b/tcg/tcg-constr.c.inc
new file mode 100644
index 0000000000..f7490a096e
--- /dev/null
+++ b/tcg/tcg-constr.c.inc
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * TCG backend data: operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+/*
+ * Define structures for each set of constraints.
+ */
+
+#define C_PFX1(P, A) P##A
+#define C_PFX2(P, A, B) P##A##_##B
+#define C_PFX3(P, A, B, C) P##A##_##B##_##C
+#define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D
+#define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E
+#define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F
+
+#define C_O0_I1(I1) \
+ static const TCGTargetOpDef C_PFX1(c_o0_i1_, I1) \
+ = { .args_ct_str = { #I1 } };
+
+#define C_O0_I2(I1, I2) \
+ static const TCGTargetOpDef C_PFX2(c_o0_i2_, I1, I2) \
+ = { .args_ct_str = { #I1, #I2 } };
+
+#define C_O0_I3(I1, I2, I3) \
+ static const TCGTargetOpDef C_PFX3(c_o0_i3_, I1, I2, I3) \
+ = { .args_ct_str = { #I1, #I2, #I3 } };
+
+#define C_O0_I4(I1, I2, I3, I4) \
+ static const TCGTargetOpDef C_PFX4(c_o0_i4_, I1, I2, I3, I4) \
+ = { .args_ct_str = { #I1, #I2, #I3, #I4 } };
+
+#define C_O1_I1(O1, I1) \
+ static const TCGTargetOpDef C_PFX2(c_o1_i1_, O1, I1) \
+ = { .args_ct_str = { #O1, #I1 } };
+
+#define C_O1_I2(O1, I1, I2) \
+ static const TCGTargetOpDef C_PFX3(c_o1_i2_, O1, I1, I2) \
+ = { .args_ct_str = { #O1, #I1, #I2 } };
+
+#define C_O1_I3(O1, I1, I2, I3) \
+ static const TCGTargetOpDef C_PFX4(c_o1_i3_, O1, I1, I2, I3) \
+ = { .args_ct_str = { #O1, #I1, #I2, #I3 } };
+
+#define C_O1_I4(O1, I1, I2, I3, I4) \
+ static const TCGTargetOpDef C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4) \
+ = { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } };
+
+#define C_N1_I2(O1, I1, I2) \
+ static const TCGTargetOpDef C_PFX3(c_n1_i2_, O1, I1, I2) \
+ = { .args_ct_str = { "&" #O1, #I1, #I2 } };
+
+#define C_O2_I1(O1, O2, I1) \
+ static const TCGTargetOpDef C_PFX3(c_o2_i1_, O1, O2, I1) \
+ = { .args_ct_str = { #O1, #O2, #I1 } };
+
+#define C_O2_I2(O1, O2, I1, I2) \
+ static const TCGTargetOpDef C_PFX4(c_o2_i2_, O1, O2, I1, I2) \
+ = { .args_ct_str = { #O1, #O2, #I1, #I2 } };
+
+#define C_O2_I3(O1, O2, I1, I2, I3) \
+ static const TCGTargetOpDef C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3) \
+ = { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } };
+
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) \
+ static const TCGTargetOpDef C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) \
+ = { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } };
+
+#include "tcg-target-constr.h"
+
+
+/*
+ * Redefine the macros so that they now reference those structures.
+ * These values should be returned from tcg_target_op_def().
+ */
+
+#undef C_O0_I1
+#undef C_O0_I2
+#undef C_O0_I3
+#undef C_O0_I4
+#undef C_O1_I1
+#undef C_O1_I2
+#undef C_O1_I3
+#undef C_O1_I4
+#undef C_N1_I2
+#undef C_O2_I1
+#undef C_O2_I2
+#undef C_O2_I3
+#undef C_O2_I4
+
+#define C_O0_I1(I1) &C_PFX1(c_o0_i1_, I1)
+#define C_O0_I2(I1, I2) &C_PFX2(c_o0_i2_, I1, I2)
+#define C_O0_I3(I1, I2, I3) &C_PFX3(c_o0_i3_, I1, I2, I3)
+#define C_O0_I4(I1, I2, I3, I4) &C_PFX4(c_o0_i4_, I1, I2, I3, I4)
+
+#define C_O1_I1(O1, I1) &C_PFX2(c_o1_i1_, O1, I1)
+#define C_O1_I2(O1, I1, I2) &C_PFX3(c_o1_i2_, O1, I1, I2)
+#define C_O1_I3(O1, I1, I2, I3) &C_PFX4(c_o1_i3_, O1, I1, I2, I3)
+#define C_O1_I4(O1, I1, I2, I3, I4) &C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4)
+
+#define C_N1_I2(O1, I1, I2) &C_PFX3(c_n1_i2_, O1, I1, I2)
+
+#define C_O2_I1(O1, O2, I1) &C_PFX3(c_o2_i1_, O1, O2, I1)
+#define C_O2_I2(O1, O2, I1, I2) &C_PFX4(c_o2_i2_, O1, O2, I1, I2)
+#define C_O2_I3(O1, O2, I1, I2, I3) &C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3)
+#define C_O2_I4(O1, O2, I1, I2, I3, I4) \
+ &C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4)
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 35/43] tcg/i386: Convert to tcg-constr.c.inc
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (33 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 34/43] tcg: Add tcg-constr.c.inc Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 36/43] tcg/aarch64: " Richard Henderson
` (7 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target-constr.h | 55 +++++++++++
tcg/i386/tcg-target.c.inc | 187 +++++++++++++----------------------
2 files changed, 121 insertions(+), 121 deletions(-)
create mode 100644 tcg/i386/tcg-target-constr.h
diff --git a/tcg/i386/tcg-target-constr.h b/tcg/i386/tcg-target-constr.h
new file mode 100644
index 0000000000..91d394612e
--- /dev/null
+++ b/tcg/i386/tcg-target-constr.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * i386 target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+
+C_O0_I2(qi, r)
+C_O0_I2(ri, r)
+C_O0_I2(re, r)
+C_O0_I2(r, re)
+C_O0_I2(L, L)
+C_O0_I2(x, r)
+
+C_O0_I3(L, L, L)
+
+C_O0_I4(L, L, L, L)
+C_O0_I4(r, r, ri, ri)
+
+C_O1_I1(r, 0)
+C_O1_I1(r, q)
+C_O1_I1(r, r)
+C_O1_I1(r, L)
+C_O1_I1(x, r)
+C_O1_I1(x, x)
+
+C_O1_I2(r, r, re)
+C_O1_I2(r, 0, r)
+C_O1_I2(r, 0, re)
+C_O1_I2(r, 0, reZ)
+C_O1_I2(r, 0, rI)
+C_O1_I2(r, 0, ri)
+C_O1_I2(r, 0, ci)
+C_O1_I2(r, r, ri)
+C_O1_I2(Q, 0, Q)
+C_O1_I2(q, r, re)
+C_O1_I2(r, L, L)
+C_O1_I2(x, x, x)
+C_N1_I2(r, r, r)
+C_N1_I2(r, r, rW)
+
+C_O1_I3(x, x, x, x)
+
+C_O1_I4(r, r, re, r, 0)
+C_O1_I4(r, r, r, ri, ri)
+
+C_O2_I1(r, r, L)
+
+C_O2_I2(r, r, L, L)
+C_O2_I2(a, d, a, r)
+
+C_O2_I3(a, d, 0, 1, r)
+
+C_O2_I4(r, r, 0, 1, re, re)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 36a90e7ef3..1dac1b33d1 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2983,39 +2983,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
}
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef ri_r = { .args_ct_str = { "ri", "r" } };
- static const TCGTargetOpDef re_r = { .args_ct_str = { "re", "r" } };
- static const TCGTargetOpDef qi_r = { .args_ct_str = { "qi", "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_q = { .args_ct_str = { "r", "q" } };
- static const TCGTargetOpDef r_re = { .args_ct_str = { "r", "re" } };
- static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
- static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
- static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
- static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef L_L_L_L
- = { .args_ct_str = { "L", "L", "L", "L" } };
- static const TCGTargetOpDef x_x = { .args_ct_str = { "x", "x" } };
- static const TCGTargetOpDef x_x_x = { .args_ct_str = { "x", "x", "x" } };
- static const TCGTargetOpDef x_x_x_x
- = { .args_ct_str = { "x", "x", "x", "x" } };
- static const TCGTargetOpDef x_r = { .args_ct_str = { "x", "r" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
@@ -3029,22 +3004,25 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
- return &qi_r;
+ return C_O0_I2(qi, r);
+
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
- return &ri_r;
+ return C_O0_I2(ri, r);
+
case INDEX_op_st_i64:
- return &re_r;
+ return C_O0_I2(re, r);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
- return &r_r_re;
+ return C_O1_I2(r, r, re);
+
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_mul_i32:
@@ -3053,24 +3031,15 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
- return &r_0_re;
+ return C_O1_I2(r, 0, re);
case INDEX_op_and_i32:
case INDEX_op_and_i64:
- {
- static const TCGTargetOpDef and
- = { .args_ct_str = { "r", "0", "reZ" } };
- return ∧
- }
- break;
+ return C_O1_I2(r, 0, reZ);
+
case INDEX_op_andc_i32:
case INDEX_op_andc_i64:
- {
- static const TCGTargetOpDef andc
- = { .args_ct_str = { "r", "r", "rI" } };
- return &andc;
- }
- break;
+ return C_O1_I2(r, 0, rI);
case INDEX_op_shl_i32:
case INDEX_op_shl_i64:
@@ -3078,16 +3047,17 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shr_i64:
case INDEX_op_sar_i32:
case INDEX_op_sar_i64:
- return have_bmi2 ? &r_r_ri : &r_0_ci;
+ return have_bmi2 ? C_O1_I2(r, r, ri) : C_O1_I2(r, 0, ci);
+
case INDEX_op_rotl_i32:
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
- return &r_0_ci;
+ return C_O1_I2(r, 0, ci);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &r_re;
+ return C_O0_I2(r, re);
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
@@ -3099,13 +3069,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_not_i32:
case INDEX_op_not_i64:
case INDEX_op_extrh_i64_i32:
- return &r_0;
+ return C_O1_I1(r, 0);
case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64:
case INDEX_op_ext8u_i32:
case INDEX_op_ext8u_i64:
- return &r_q;
+ return C_O1_I1(r, q);
+
case INDEX_op_ext16s_i32:
case INDEX_op_ext16s_i64:
case INDEX_op_ext16u_i32:
@@ -3120,108 +3091,80 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_sextract_i32:
case INDEX_op_ctpop_i32:
case INDEX_op_ctpop_i64:
- return &r_r;
+ return C_O1_I1(r, r);
+
case INDEX_op_extract2_i32:
case INDEX_op_extract2_i64:
- return &r_0_r;
+ return C_O1_I2(r, 0, r);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- {
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "Q", "0", "Q" } };
- return &dep;
- }
+ return C_O1_I2(Q, 0, Q);
+
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
- {
- static const TCGTargetOpDef setc
- = { .args_ct_str = { "q", "r", "re" } };
- return &setc;
- }
+ return C_O1_I2(q, r, re);
+
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- {
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "re", "r", "0" } };
- return &movc;
- }
+ return C_O1_I4(r, r, re, r, 0);
+
case INDEX_op_div2_i32:
case INDEX_op_div2_i64:
case INDEX_op_divu2_i32:
case INDEX_op_divu2_i64:
- {
- static const TCGTargetOpDef div2
- = { .args_ct_str = { "a", "d", "0", "1", "r" } };
- return &div2;
- }
+ return C_O2_I3(a, d, 0, 1, r);
+
case INDEX_op_mulu2_i32:
case INDEX_op_mulu2_i64:
case INDEX_op_muls2_i32:
case INDEX_op_muls2_i64:
- {
- static const TCGTargetOpDef mul2
- = { .args_ct_str = { "a", "d", "a", "r" } };
- return &mul2;
- }
+ return C_O2_I2(a, d, a, r);
+
case INDEX_op_add2_i32:
case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
case INDEX_op_sub2_i64:
- {
- static const TCGTargetOpDef arith2
- = { .args_ct_str = { "r", "r", "0", "1", "re", "re" } };
- return &arith2;
- }
+ return C_O2_I4(r, r, 0, 1, re, re);
+
case INDEX_op_ctz_i32:
case INDEX_op_ctz_i64:
- {
- static const TCGTargetOpDef ctz[2] = {
- { .args_ct_str = { "&r", "r", "r" } },
- { .args_ct_str = { "&r", "r", "rW" } },
- };
- return &ctz[have_bmi1];
- }
+ return have_bmi1 ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
+
case INDEX_op_clz_i32:
case INDEX_op_clz_i64:
- {
- static const TCGTargetOpDef clz[2] = {
- { .args_ct_str = { "&r", "r", "r" } },
- { .args_ct_str = { "&r", "r", "rW" } },
- };
- return &clz[have_lzcnt];
- }
+ return have_lzcnt ? C_N1_I2(r, r, rW) : C_N1_I2(r, r, r);
case INDEX_op_qemu_ld_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
+
case INDEX_op_qemu_st_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L : &L_L_L;
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O0_I2(L, L) : C_O0_I3(L, L, L));
+
case INDEX_op_qemu_ld_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
- : &r_r_L_L);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
+ : C_O2_I2(r, r, L, L));
+
case INDEX_op_qemu_st_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &L_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &L_L_L
- : &L_L_L_L);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(L, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(L, L, L)
+ : C_O0_I4(L, L, L, L));
case INDEX_op_brcond2_i32:
- {
- static const TCGTargetOpDef b2
- = { .args_ct_str = { "r", "r", "ri", "ri" } };
- return &b2;
- }
+ return C_O0_I4(r, r, ri, ri);
+
case INDEX_op_setcond2_i32:
- {
- static const TCGTargetOpDef s2
- = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
- return &s2;
- }
+ return C_O1_I4(r, r, r, ri, ri);
case INDEX_op_ld_vec:
- case INDEX_op_st_vec:
case INDEX_op_dupm_vec:
- return &x_r;
+ return C_O1_I1(x, r);
+
+ case INDEX_op_st_vec:
+ return C_O0_I2(x, r);
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
@@ -3256,16 +3199,18 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_dup2_vec:
#endif
- return &x_x_x;
+ return C_O1_I2(x, x, x);
+
case INDEX_op_abs_vec:
case INDEX_op_dup_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
case INDEX_op_x86_psrldq_vec:
- return &x_x;
+ return C_O1_I1(x, x);
+
case INDEX_op_x86_vpblendvb_vec:
- return &x_x_x_x;
+ return C_O1_I3(x, x, x, x);
default:
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 36/43] tcg/aarch64: Convert to tcg-constr.c.inc
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (34 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 35/43] tcg/i386: Convert to tcg-constr.c.inc Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 37/43] tcg/arm: " Richard Henderson
` (6 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target-constr.h | 31 ++++++++++++
tcg/aarch64/tcg-target.c.inc | 85 +++++++++++----------------------
2 files changed, 60 insertions(+), 56 deletions(-)
create mode 100644 tcg/aarch64/tcg-target-constr.h
diff --git a/tcg/aarch64/tcg-target-constr.h b/tcg/aarch64/tcg-target-constr.h
new file mode 100644
index 0000000000..dcf46a7457
--- /dev/null
+++ b/tcg/aarch64/tcg-target-constr.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * AArch64 target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(lZ, l)
+C_O0_I2(r, rA)
+C_O0_I2(rZ, r)
+C_O0_I2(w, r)
+C_O1_I1(r, l)
+C_O1_I1(r, r)
+C_O1_I1(w, r)
+C_O1_I1(w, w)
+C_O1_I1(w, wr)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, rA)
+C_O1_I2(r, r, rAL)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rL)
+C_O1_I2(r, rZ, rZ)
+C_O1_I2(w, 0, w)
+C_O1_I2(w, w, w)
+C_O1_I2(w, w, wN)
+C_O1_I2(w, w, wO)
+C_O1_I2(w, w, wZ)
+C_O1_I3(w, w, w, w)
+C_O1_I4(r, r, rA, rZ, rZ)
+C_O2_I4(r, r, rZ, rZ, rA, rMZ)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index d9d397075a..e352f7f56b 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -2577,42 +2577,14 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
va_end(va);
}
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef w_w = { .args_ct_str = { "w", "w" } };
- static const TCGTargetOpDef w_r = { .args_ct_str = { "w", "r" } };
- static const TCGTargetOpDef w_wr = { .args_ct_str = { "w", "wr" } };
- static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
- static const TCGTargetOpDef r_rA = { .args_ct_str = { "r", "rA" } };
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef lZ_l = { .args_ct_str = { "lZ", "l" } };
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
- static const TCGTargetOpDef w_w_w = { .args_ct_str = { "w", "w", "w" } };
- static const TCGTargetOpDef w_0_w = { .args_ct_str = { "w", "0", "w" } };
- static const TCGTargetOpDef w_w_wO = { .args_ct_str = { "w", "w", "wO" } };
- static const TCGTargetOpDef w_w_wN = { .args_ct_str = { "w", "w", "wN" } };
- static const TCGTargetOpDef w_w_wZ = { .args_ct_str = { "w", "w", "wZ" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rA = { .args_ct_str = { "r", "r", "rA" } };
- static const TCGTargetOpDef r_r_rL = { .args_ct_str = { "r", "r", "rL" } };
- static const TCGTargetOpDef r_r_rAL
- = { .args_ct_str = { "r", "r", "rAL" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef ext2
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rA", "rMZ" } };
- static const TCGTargetOpDef w_w_w_w
- = { .args_ct_str = { "w", "w", "w", "w" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
@@ -2651,7 +2623,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_extract_i64:
case INDEX_op_sextract_i32:
case INDEX_op_sextract_i64:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
@@ -2660,7 +2632,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &rZ_r;
+ return C_O0_I2(rZ, r);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
@@ -2668,7 +2640,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_sub_i64:
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
- return &r_r_rA;
+ return C_O1_I2(r, r, rA);
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
@@ -2682,7 +2654,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_remu_i64:
case INDEX_op_muluh_i64:
case INDEX_op_mulsh_i64:
- return &r_r_r;
+ return C_O1_I2(r, r, r);
case INDEX_op_and_i32:
case INDEX_op_and_i64:
@@ -2696,7 +2668,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_orc_i64:
case INDEX_op_eqv_i32:
case INDEX_op_eqv_i64:
- return &r_r_rL;
+ return C_O1_I2(r, r, rL);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
@@ -2708,42 +2680,42 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_sar_i64:
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i64:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
case INDEX_op_clz_i64:
case INDEX_op_ctz_i64:
- return &r_r_rAL;
+ return C_O1_I2(r, r, rAL);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &r_rA;
+ return C_O0_I2(r, rA);
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- return &movc;
+ return C_O1_I4(r, r, rA, rZ, rZ);
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
- return &r_l;
+ return C_O1_I1(r, l);
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
- return &lZ_l;
+ return C_O0_I2(lZ, l);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- return &dep;
+ return C_O1_I2(r, 0, rZ);
case INDEX_op_extract2_i32:
case INDEX_op_extract2_i64:
- return &ext2;
+ return C_O1_I2(r, rZ, rZ);
case INDEX_op_add2_i32:
case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
case INDEX_op_sub2_i64:
- return &add2;
+ return C_O2_I4(r, r, rZ, rZ, rA, rMZ);
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
@@ -2761,32 +2733,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
case INDEX_op_aa64_sshl_vec:
- return &w_w_w;
+ return C_O1_I2(w, w, w);
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
case INDEX_op_abs_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
- return &w_w;
+ return C_O1_I1(w, w);
case INDEX_op_ld_vec:
- case INDEX_op_st_vec:
case INDEX_op_dupm_vec:
- return &w_r;
+ return C_O1_I1(w, r);
+ case INDEX_op_st_vec:
+ return C_O0_I2(w, r);
case INDEX_op_dup_vec:
- return &w_wr;
+ return C_O1_I1(w, wr);
case INDEX_op_or_vec:
case INDEX_op_andc_vec:
- return &w_w_wO;
+ return C_O1_I2(w, w, wO);
case INDEX_op_and_vec:
case INDEX_op_orc_vec:
- return &w_w_wN;
+ return C_O1_I2(w, w, wN);
case INDEX_op_cmp_vec:
- return &w_w_wZ;
+ return C_O1_I2(w, w, wZ);
case INDEX_op_bitsel_vec:
- return &w_w_w_w;
+ return C_O1_I3(w, w, w, w);
case INDEX_op_aa64_sli_vec:
- return &w_0_w;
+ return C_O1_I2(w, 0, w);
default:
return NULL;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 37/43] tcg/arm: Convert to tcg-constr.c.inc
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (35 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 36/43] tcg/aarch64: " Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 38/43] tcg/mips: " Richard Henderson
` (5 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target-constr.h | 30 ++++++++++++
tcg/arm/tcg-target.c.inc | 93 +++++++++++++------------------------
2 files changed, 63 insertions(+), 60 deletions(-)
create mode 100644 tcg/arm/tcg-target-constr.h
diff --git a/tcg/arm/tcg-target-constr.h b/tcg/arm/tcg-target-constr.h
new file mode 100644
index 0000000000..c59be2da11
--- /dev/null
+++ b/tcg/arm/tcg-target-constr.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * ARM32 target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(r, r)
+C_O0_I2(r, rIN)
+C_O0_I2(s, s)
+C_O0_I3(s, s, s)
+C_O0_I4(r, r, rI, rI)
+C_O0_I4(s, s, s, s)
+C_O1_I1(r, l)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, l, l)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rIK)
+C_O1_I2(r, r, rIN)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, r, r, rI, rI)
+C_O1_I4(r, r, rIN, rIK, 0)
+C_O2_I1(r, r, l)
+C_O2_I2(r, r, l, l)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, r, r, rIN, rIK)
+C_O2_I4(r, r, rI, rI, rIN, rIK)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 30d30874c7..70a9e798e3 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -2071,57 +2071,20 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef s_s = { .args_ct_str = { "s", "s" } };
- static const TCGTargetOpDef r_l = { .args_ct_str = { "r", "l" } };
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
- static const TCGTargetOpDef r_r_l = { .args_ct_str = { "r", "r", "l" } };
- static const TCGTargetOpDef r_l_l = { .args_ct_str = { "r", "l", "l" } };
- static const TCGTargetOpDef s_s_s = { .args_ct_str = { "s", "s", "s" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_r_rIN
- = { .args_ct_str = { "r", "r", "rIN" } };
- static const TCGTargetOpDef r_r_rIK
- = { .args_ct_str = { "r", "r", "rIK" } };
- static const TCGTargetOpDef r_r_r_r
- = { .args_ct_str = { "r", "r", "r", "r" } };
- static const TCGTargetOpDef r_r_l_l
- = { .args_ct_str = { "r", "r", "l", "l" } };
- static const TCGTargetOpDef s_s_s_s
- = { .args_ct_str = { "s", "s", "s", "s" } };
- static const TCGTargetOpDef br
- = { .args_ct_str = { "r", "rIN" } };
- static const TCGTargetOpDef ext2
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "rIN", "rIK", "0" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "r", "r", "rIN", "rIK" } };
- static const TCGTargetOpDef sub2
- = { .args_ct_str = { "r", "r", "rI", "rI", "rIN", "rIK" } };
- static const TCGTargetOpDef br2
- = { .args_ct_str = { "r", "r", "rI", "rI" } };
- static const TCGTargetOpDef setc2
- = { .args_ct_str = { "r", "r", "r", "rI", "rI" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
case INDEX_op_neg_i32:
case INDEX_op_not_i32:
case INDEX_op_bswap16_i32:
@@ -2131,59 +2094,69 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ext16u_i32:
case INDEX_op_extract_i32:
case INDEX_op_sextract_i32:
- return &r_r;
+ return C_O1_I1(r, r);
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ return C_O0_I2(r, r);
case INDEX_op_add_i32:
case INDEX_op_sub_i32:
case INDEX_op_setcond_i32:
- return &r_r_rIN;
+ return C_O1_I2(r, r, rIN);
+
case INDEX_op_and_i32:
case INDEX_op_andc_i32:
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
- return &r_r_rIK;
+ return C_O1_I2(r, r, rIK);
+
case INDEX_op_mul_i32:
case INDEX_op_div_i32:
case INDEX_op_divu_i32:
- return &r_r_r;
+ return C_O1_I2(r, r, r);
+
case INDEX_op_mulu2_i32:
case INDEX_op_muls2_i32:
- return &r_r_r_r;
+ return C_O2_I2(r, r, r, r);
+
case INDEX_op_or_i32:
case INDEX_op_xor_i32:
- return &r_r_rI;
+ return C_O1_I2(r, r, rI);
+
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
case INDEX_op_rotl_i32:
case INDEX_op_rotr_i32:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
case INDEX_op_brcond_i32:
- return &br;
+ return C_O0_I2(r, rIN);
case INDEX_op_deposit_i32:
- return &dep;
+ return C_O1_I2(r, 0, rZ);
case INDEX_op_extract2_i32:
- return &ext2;
+ return C_O1_I2(r, rZ, rZ);
case INDEX_op_movcond_i32:
- return &movc;
+ return C_O1_I4(r, r, rIN, rIK, 0);
case INDEX_op_add2_i32:
- return &add2;
+ return C_O2_I4(r, r, r, r, rIN, rIK);
case INDEX_op_sub2_i32:
- return &sub2;
+ return C_O2_I4(r, r, rI, rI, rIN, rIK);
case INDEX_op_brcond2_i32:
- return &br2;
+ return C_O0_I4(r, r, rI, rI);
case INDEX_op_setcond2_i32:
- return &setc2;
+ return C_O1_I4(r, r, r, rI, rI);
case INDEX_op_qemu_ld_i32:
- return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
+ return TARGET_LONG_BITS == 32 ? C_O1_I1(r, l) : C_O1_I2(r, l, l);
case INDEX_op_qemu_ld_i64:
- return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
+ return TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, l) : C_O2_I2(r, r, l, l);
case INDEX_op_qemu_st_i32:
- return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
+ return TARGET_LONG_BITS == 32 ? C_O0_I2(s, s) : C_O0_I3(s, s, s);
case INDEX_op_qemu_st_i64:
- return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
+ return TARGET_LONG_BITS == 32 ? C_O0_I3(s, s, s) : C_O0_I4(s, s, s, s);
default:
return NULL;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 38/43] tcg/mips: Convert to tcg-constr.c.inc
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (36 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 37/43] tcg/arm: " Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 39/43] tcg/ppc: " Richard Henderson
` (4 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target-constr.h | 31 ++++++++++++
tcg/mips/tcg-target.c.inc | 95 ++++++++++++------------------------
2 files changed, 61 insertions(+), 65 deletions(-)
create mode 100644 tcg/mips/tcg-target-constr.h
diff --git a/tcg/mips/tcg-target-constr.h b/tcg/mips/tcg-target-constr.h
new file mode 100644
index 0000000000..831e2d8a01
--- /dev/null
+++ b/tcg/mips/tcg-target-constr.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * MIPS target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(rZ, r)
+C_O0_I2(rZ, rZ)
+C_O0_I2(SZ, S)
+C_O0_I3(SZ, S, S)
+C_O0_I3(SZ, SZ, S)
+C_O0_I4(rZ, rZ, rZ, rZ)
+C_O0_I4(SZ, SZ, S, S)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rIK)
+C_O1_I2(r, r, rJ)
+C_O1_I2(r, r, rWZ)
+C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, rZ, rZ, rZ, 0)
+C_O1_I4(r, rZ, rZ, rZ, rZ)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, rZ, rZ, rN, rN)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 3e282c1bde..9e78a79eb6 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -2158,52 +2158,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } };
- static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } };
- static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } };
- static const TCGTargetOpDef SZ_SZ_S
- = { .args_ct_str = { "SZ", "SZ", "S" } };
- static const TCGTargetOpDef SZ_SZ_S_S
- = { .args_ct_str = { "SZ", "SZ", "S", "S" } };
- static const TCGTargetOpDef r_rZ_rN
- = { .args_ct_str = { "r", "rZ", "rN" } };
- static const TCGTargetOpDef r_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_rIK
- = { .args_ct_str = { "r", "r", "rIK" } };
- static const TCGTargetOpDef r_r_rWZ
- = { .args_ct_str = { "r", "r", "rWZ" } };
- static const TCGTargetOpDef r_r_r_r
- = { .args_ct_str = { "r", "r", "r", "r" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } };
- static const TCGTargetOpDef movc_r6
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } };
- static const TCGTargetOpDef br2
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef setc2
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
@@ -2236,7 +2198,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_extract_i64:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
@@ -2245,14 +2207,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &rZ_r;
+ return C_O0_I2(rZ, r);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
- return &r_r_rJ;
+ return C_O1_I2(r, r, rJ);
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
- return &r_rZ_rN;
+ return C_O1_I2(r, rZ, rN);
case INDEX_op_mul_i32:
case INDEX_op_mulsh_i32:
case INDEX_op_muluh_i32:
@@ -2271,20 +2233,20 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_remu_i64:
case INDEX_op_nor_i64:
case INDEX_op_setcond_i64:
- return &r_rZ_rZ;
+ return C_O1_I2(r, rZ, rZ);
case INDEX_op_muls2_i32:
case INDEX_op_mulu2_i32:
case INDEX_op_muls2_i64:
case INDEX_op_mulu2_i64:
- return &r_r_r_r;
+ return C_O2_I2(r, r, r, r);
case INDEX_op_and_i32:
case INDEX_op_and_i64:
- return &r_r_rIK;
+ return C_O1_I2(r, r, rIK);
case INDEX_op_or_i32:
case INDEX_op_xor_i32:
case INDEX_op_or_i64:
case INDEX_op_xor_i64:
- return &r_r_rI;
+ return C_O1_I2(r, r, rI);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
@@ -2295,41 +2257,44 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_sar_i64:
case INDEX_op_rotr_i64:
case INDEX_op_rotl_i64:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
case INDEX_op_clz_i32:
case INDEX_op_clz_i64:
- return &r_r_rWZ;
+ return C_O1_I2(r, r, rWZ);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- return &dep;
+ return C_O1_I2(r, 0, rZ);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &rZ_rZ;
+ return C_O0_I2(rZ, rZ);
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- return use_mips32r6_instructions ? &movc_r6 : &movc;
-
+ return (use_mips32r6_instructions
+ ? C_O1_I4(r, rZ, rZ, rZ, rZ)
+ : C_O1_I4(r, rZ, rZ, rZ, 0));
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- return &add2;
+ return C_O2_I4(r, r, rZ, rZ, rN, rN);
case INDEX_op_setcond2_i32:
- return &setc2;
+ return C_O1_I4(r, rZ, rZ, rZ, rZ);
case INDEX_op_brcond2_i32:
- return &br2;
+ return C_O0_I4(rZ, rZ, rZ, rZ);
case INDEX_op_qemu_ld_i32:
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &r_L : &r_L_L);
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
case INDEX_op_qemu_st_i32:
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &SZ_S : &SZ_S_S);
+ ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S));
case INDEX_op_qemu_ld_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L)
+ : C_O2_I2(r, r, L, L));
case INDEX_op_qemu_st_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &SZ_S
- : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S)
+ : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S)
+ : C_O0_I4(SZ, SZ, S, S));
default:
return NULL;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 39/43] tcg/ppc: Convert to tcg-constr.c.inc
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (37 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 38/43] tcg/mips: " Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 40/43] tcg/riscv: " Richard Henderson
` (3 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target-constr.h | 37 ++++++++++
tcg/ppc/tcg-target.c.inc | 135 +++++++++++++++---------------------
2 files changed, 94 insertions(+), 78 deletions(-)
create mode 100644 tcg/ppc/tcg-target-constr.h
diff --git a/tcg/ppc/tcg-target-constr.h b/tcg/ppc/tcg-target-constr.h
new file mode 100644
index 0000000000..9a38f8ed89
--- /dev/null
+++ b/tcg/ppc/tcg-target-constr.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * PowerPC target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O0_I2(S, S)
+C_O0_I2(v, r)
+C_O0_I3(S, S, S)
+C_O0_I4(r, r, ri, ri)
+C_O0_I4(S, S, S, S)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I1(v, r)
+C_O1_I1(v, v)
+C_O1_I1(v, vr)
+C_O1_I2(r, 0, rZ)
+C_O1_I2(r, L, L)
+C_O1_I2(r, rI, ri)
+C_O1_I2(r, rI, rT)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, r, rT)
+C_O1_I2(r, r, rU)
+C_O1_I2(r, r, rZW)
+C_O1_I2(v, v, v)
+C_O1_I3(v, v, v, v)
+C_O1_I4(r, r, ri, rZ, rZ)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I1(L, L, L)
+C_O2_I2(L, L, L, L)
+C_O2_I4(r, r, rI, rZM, r, r)
+C_O2_I4(r, r, r, r, rI, rZM)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 155c42ed24..e34a02ee04 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -3495,62 +3495,20 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
va_end(va);
}
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef S_S = { .args_ct_str = { "S", "S" } };
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
- static const TCGTargetOpDef r_r_r = { .args_ct_str = { "r", "r", "r" } };
- static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef L_L_L = { .args_ct_str = { "L", "L", "L" } };
- static const TCGTargetOpDef S_S_S = { .args_ct_str = { "S", "S", "S" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_r_rT = { .args_ct_str = { "r", "r", "rT" } };
- static const TCGTargetOpDef r_r_rU = { .args_ct_str = { "r", "r", "rU" } };
- static const TCGTargetOpDef r_rI_ri
- = { .args_ct_str = { "r", "rI", "ri" } };
- static const TCGTargetOpDef r_rI_rT
- = { .args_ct_str = { "r", "rI", "rT" } };
- static const TCGTargetOpDef r_r_rZW
- = { .args_ct_str = { "r", "r", "rZW" } };
- static const TCGTargetOpDef L_L_L_L
- = { .args_ct_str = { "L", "L", "L", "L" } };
- static const TCGTargetOpDef S_S_S_S
- = { .args_ct_str = { "S", "S", "S", "S" } };
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "ri", "rZ", "rZ" } };
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "0", "rZ" } };
- static const TCGTargetOpDef br2
- = { .args_ct_str = { "r", "r", "ri", "ri" } };
- static const TCGTargetOpDef setc2
- = { .args_ct_str = { "r", "r", "r", "ri", "ri" } };
- static const TCGTargetOpDef add2
- = { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
- static const TCGTargetOpDef sub2
- = { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
- static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
- static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
- static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
- static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
- static const TCGTargetOpDef v_v_v_v
- = { .args_ct_str = { "v", "v", "v", "v" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
case INDEX_op_ld16u_i32:
case INDEX_op_ld16s_i32:
case INDEX_op_ld_i32:
- case INDEX_op_st8_i32:
- case INDEX_op_st16_i32:
- case INDEX_op_st_i32:
case INDEX_op_ctpop_i32:
case INDEX_op_neg_i32:
case INDEX_op_not_i32:
@@ -3566,10 +3524,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
- case INDEX_op_st8_i64:
- case INDEX_op_st16_i64:
- case INDEX_op_st32_i64:
- case INDEX_op_st_i64:
case INDEX_op_ctpop_i64:
case INDEX_op_neg_i64:
case INDEX_op_not_i64:
@@ -3582,7 +3536,16 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_bswap32_i64:
case INDEX_op_bswap64_i64:
case INDEX_op_extract_i64:
- return &r_r;
+ return C_O1_I1(r, r);
+
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return C_O0_I2(r, r);
case INDEX_op_add_i32:
case INDEX_op_and_i32:
@@ -3605,10 +3568,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i64:
case INDEX_op_setcond_i64:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
+
case INDEX_op_mul_i32:
case INDEX_op_mul_i64:
- return &r_r_rI;
+ return C_O1_I2(r, r, rI);
+
case INDEX_op_div_i32:
case INDEX_op_divu_i32:
case INDEX_op_nand_i32:
@@ -3623,55 +3588,63 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_divu_i64:
case INDEX_op_mulsh_i64:
case INDEX_op_muluh_i64:
- return &r_r_r;
+ return C_O1_I2(r, r, r);
+
case INDEX_op_sub_i32:
- return &r_rI_ri;
+ return C_O1_I2(r, rI, ri);
case INDEX_op_add_i64:
- return &r_r_rT;
+ return C_O1_I2(r, r, rT);
case INDEX_op_or_i64:
case INDEX_op_xor_i64:
- return &r_r_rU;
+ return C_O1_I2(r, r, rU);
case INDEX_op_sub_i64:
- return &r_rI_rT;
+ return C_O1_I2(r, rI, rT);
case INDEX_op_clz_i32:
case INDEX_op_ctz_i32:
case INDEX_op_clz_i64:
case INDEX_op_ctz_i64:
- return &r_r_rZW;
+ return C_O1_I2(r, r, rZW);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &r_ri;
+ return C_O0_I2(r, ri);
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- return &movc;
+ return C_O1_I4(r, r, ri, rZ, rZ);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- return &dep;
+ return C_O1_I2(r, 0, rZ);
case INDEX_op_brcond2_i32:
- return &br2;
+ return C_O0_I4(r, r, ri, ri);
case INDEX_op_setcond2_i32:
- return &setc2;
+ return C_O1_I4(r, r, r, ri, ri);
case INDEX_op_add2_i64:
case INDEX_op_add2_i32:
- return &add2;
+ return C_O2_I4(r, r, r, r, rI, rZM);
case INDEX_op_sub2_i64:
case INDEX_op_sub2_i32:
- return &sub2;
+ return C_O2_I4(r, r, rI, rZM, r, r);
case INDEX_op_qemu_ld_i32:
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &r_L : &r_L_L);
+ ? C_O1_I1(r, L)
+ : C_O1_I2(r, L, L));
+
case INDEX_op_qemu_st_i32:
return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32
- ? &S_S : &S_S_S);
+ ? C_O0_I2(S, S)
+ : C_O0_I3(S, S, S));
+
case INDEX_op_qemu_ld_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS == 32 ? &L_L_L : &L_L_L_L);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L)
+ : C_O2_I2(L, L, L, L));
+
case INDEX_op_qemu_st_i64:
- return (TCG_TARGET_REG_BITS == 64 ? &S_S
- : TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S)
+ : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S)
+ : C_O0_I4(S, S, S, S));
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
@@ -3701,19 +3674,25 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ppc_mulou_vec:
case INDEX_op_ppc_pkum_vec:
case INDEX_op_dup2_vec:
- return &v_v_v;
+ return C_O1_I2(v, v, v);
+
case INDEX_op_not_vec:
case INDEX_op_neg_vec:
- return &v_v;
+ return C_O1_I1(v, v);
+
case INDEX_op_dup_vec:
- return have_isa_3_00 ? &v_vr : &v_v;
+ return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v);
+
case INDEX_op_ld_vec:
- case INDEX_op_st_vec:
case INDEX_op_dupm_vec:
- return &v_r;
+ return C_O1_I1(v, r);
+
+ case INDEX_op_st_vec:
+ return C_O0_I2(v, r);
+
case INDEX_op_bitsel_vec:
case INDEX_op_ppc_msum_vec:
- return &v_v_v_v;
+ return C_O1_I3(v, v, v, v);
default:
return NULL;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 40/43] tcg/riscv: Convert to tcg-constr.c.inc
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (38 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 39/43] tcg/ppc: " Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 41/43] tcg/s390: " Richard Henderson
` (2 subsequent siblings)
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target-constr.h | 25 +++++++++++
tcg/riscv/tcg-target.c.inc | 82 ++++++++++-------------------------
2 files changed, 49 insertions(+), 58 deletions(-)
create mode 100644 tcg/riscv/tcg-target-constr.h
diff --git a/tcg/riscv/tcg-target-constr.h b/tcg/riscv/tcg-target-constr.h
new file mode 100644
index 0000000000..aeff74034c
--- /dev/null
+++ b/tcg/riscv/tcg-target-constr.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * RISC-V target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(LZ, L)
+C_O0_I2(rZ, r)
+C_O0_I2(rZ, rZ)
+C_O0_I3(LZ, L, L)
+C_O0_I3(LZ, LZ, L)
+C_O0_I4(LZ, LZ, L, L)
+C_O0_I4(rZ, rZ, rZ, rZ)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, rZ, rZ, rZ, rZ)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+C_O2_I4(r, r, rZ, rZ, rM, rM)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index aaef1c5eed..042a41e1f4 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1608,50 +1608,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r
- = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r
- = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef rZ_r
- = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef rZ_rZ
- = { .args_ct_str = { "rZ", "rZ" } };
- static const TCGTargetOpDef rZ_rZ_rZ_rZ
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_ri
- = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI
- = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_rZ_rN
- = { .args_ct_str = { "r", "rZ", "rN" } };
- static const TCGTargetOpDef r_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef r_L
- = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef r_r_L
- = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef r_L_L
- = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef LZ_L
- = { .args_ct_str = { "LZ", "L" } };
- static const TCGTargetOpDef LZ_L_L
- = { .args_ct_str = { "LZ", "L", "L" } };
- static const TCGTargetOpDef LZ_LZ_L
- = { .args_ct_str = { "LZ", "LZ", "L" } };
- static const TCGTargetOpDef LZ_LZ_L_L
- = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
- static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
@@ -1683,7 +1647,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
@@ -1692,7 +1656,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &rZ_r;
+ return C_O0_I2(rZ, r);
case INDEX_op_add_i32:
case INDEX_op_and_i32:
@@ -1702,11 +1666,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_and_i64:
case INDEX_op_or_i64:
case INDEX_op_xor_i64:
- return &r_r_rI;
+ return C_O1_I2(r, r, rI);
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
- return &r_rZ_rN;
+ return C_O1_I2(r, rZ, rN);
case INDEX_op_mul_i32:
case INDEX_op_mulsh_i32:
@@ -1724,7 +1688,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_rem_i64:
case INDEX_op_remu_i64:
case INDEX_op_setcond_i64:
- return &r_rZ_rZ;
+ return C_O1_I2(r, rZ, rZ);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
@@ -1732,36 +1696,38 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shl_i64:
case INDEX_op_shr_i64:
case INDEX_op_sar_i64:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &rZ_rZ;
+ return C_O0_I2(rZ, rZ);
case INDEX_op_add2_i32:
case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
case INDEX_op_sub2_i64:
- return &r_r_rZ_rZ_rM_rM;
+ return C_O2_I4(r, r, rZ, rZ, rM, rM);
case INDEX_op_brcond2_i32:
- return &rZ_rZ_rZ_rZ;
+ return C_O0_I4(rZ, rZ, rZ, rZ);
case INDEX_op_setcond2_i32:
- return &r_rZ_rZ_rZ_rZ;
+ return C_O1_I4(r, rZ, rZ, rZ, rZ);
case INDEX_op_qemu_ld_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
case INDEX_op_qemu_st_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
case INDEX_op_qemu_ld_i64:
- return TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
- : &r_r_L_L;
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
+ : C_O2_I2(r, r, L, L));
case INDEX_op_qemu_st_i64:
- return TCG_TARGET_REG_BITS == 64 ? &LZ_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
- : &LZ_LZ_L_L;
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
+ : C_O0_I4(LZ, LZ, L, L));
default:
return NULL;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 41/43] tcg/s390: Convert to tcg-constr.c.inc
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (39 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 40/43] tcg/riscv: " Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 42/43] tcg/sparc: " Richard Henderson
2020-09-09 0:16 ` [PATCH 43/43] tcg/tci: " Richard Henderson
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390/tcg-target-constr.h | 24 +++++++
tcg/s390/tcg-target.c.inc | 119 +++++++++++++++--------------------
2 files changed, 76 insertions(+), 67 deletions(-)
create mode 100644 tcg/s390/tcg-target-constr.h
diff --git a/tcg/s390/tcg-target-constr.h b/tcg/s390/tcg-target-constr.h
new file mode 100644
index 0000000000..06c1f4a944
--- /dev/null
+++ b/tcg/s390/tcg-target-constr.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * S390 target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(L, L)
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, ri)
+C_O1_I2(r, 0, rI)
+C_O1_I2(r, 0, rJ)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, rZ, r)
+C_O1_I4(r, r, ri, r, 0)
+C_O1_I4(r, r, ri, rI, 0)
+C_O2_I2(b, a, 0, r)
+C_O2_I3(b, a, 0, 1, r)
+C_O2_I4(r, r, 0, 1, rA, r)
+C_O2_I4(r, r, 0, 1, ri, r)
+C_O2_I4(r, r, 0, 1, r, r)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 824a07aa7a..c628194421 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -2312,27 +2312,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
- static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
- static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
- static const TCGTargetOpDef a2_r
- = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
- static const TCGTargetOpDef a2_ri
- = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
- static const TCGTargetOpDef a2_rA
- = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
@@ -2346,6 +2333,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
+ return C_O1_I1(r, r);
+
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
case INDEX_op_st16_i32:
@@ -2353,11 +2342,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &r_r;
+ return C_O0_I2(r, r);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
- return &r_r_ri;
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotr_i64:
+ case INDEX_op_clz_i64:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ return C_O1_I2(r, r, ri);
+
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_and_i32:
@@ -2366,35 +2366,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
+ return (s390_facilities & FACILITY_DISTINCT_OPS
+ ? C_O1_I2(r, r, ri)
+ : C_O1_I2(r, 0, ri));
case INDEX_op_mul_i32:
/* If we have the general-instruction-extensions, then we have
MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
+ return (s390_facilities & FACILITY_GEN_INST_EXT
+ ? C_O1_I2(r, 0, ri)
+ : C_O1_I2(r, 0, rI));
+
case INDEX_op_mul_i64:
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
+ return (s390_facilities & FACILITY_GEN_INST_EXT
+ ? C_O1_I2(r, 0, rJ)
+ : C_O1_I2(r, 0, rI));
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
-
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- return &r_r_ri;
-
- case INDEX_op_rotl_i32:
- case INDEX_op_rotl_i64:
- case INDEX_op_rotr_i32:
- case INDEX_op_rotr_i64:
- return &r_r_ri;
+ return (s390_facilities & FACILITY_DISTINCT_OPS
+ ? C_O1_I2(r, r, ri)
+ : C_O1_I2(r, 0, ri));
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &r_ri;
+ return C_O0_I2(r, ri);
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
@@ -2417,58 +2415,45 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
- return &r_r;
-
- case INDEX_op_clz_i64:
- case INDEX_op_setcond_i32:
- case INDEX_op_setcond_i64:
- return &r_r_ri;
+ return C_O1_I1(r, r);
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
- return &r_L;
+ return C_O1_I1(r, L);
case INDEX_op_qemu_st_i64:
case INDEX_op_qemu_st_i32:
- return &L_L;
+ return C_O0_I2(L, L);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- {
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "rZ", "r" } };
- return &dep;
- }
+ return C_O1_I2(r, rZ, r);
+
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- {
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "ri", "r", "0" } };
- static const TCGTargetOpDef movc_l
- = { .args_ct_str = { "r", "r", "ri", "rI", "0" } };
- return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);
- }
+ return (s390_facilities & FACILITY_LOAD_ON_COND2
+ ? C_O1_I4(r, r, ri, rI, 0)
+ : C_O1_I4(r, r, ri, r, 0));
+
case INDEX_op_div2_i32:
case INDEX_op_div2_i64:
case INDEX_op_divu2_i32:
case INDEX_op_divu2_i64:
- {
- static const TCGTargetOpDef div2
- = { .args_ct_str = { "b", "a", "0", "1", "r" } };
- return &div2;
- }
+ return C_O2_I3(b, a, 0, 1, r);
+
case INDEX_op_mulu2_i64:
- {
- static const TCGTargetOpDef mul2
- = { .args_ct_str = { "b", "a", "0", "r" } };
- return &mul2;
- }
+ return C_O2_I2(b, a, 0, r);
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
+ return (s390_facilities & FACILITY_EXT_IMM
+ ? C_O2_I4(r, r, 0, 1, ri, r)
+ : C_O2_I4(r, r, 0, 1, r, r));
+
case INDEX_op_add2_i64:
case INDEX_op_sub2_i64:
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
+ return (s390_facilities & FACILITY_EXT_IMM
+ ? C_O2_I4(r, r, 0, 1, rA, r)
+ : C_O2_I4(r, r, 0, 1, r, r));
default:
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 42/43] tcg/sparc: Convert to tcg-constr.c.inc
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (40 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 41/43] tcg/s390: " Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
2020-09-09 0:16 ` [PATCH 43/43] tcg/tci: " Richard Henderson
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/sparc/tcg-target-constr.h | 27 +++++++++++++
tcg/sparc/tcg-target.c.inc | 74 ++++++++++++-----------------------
2 files changed, 51 insertions(+), 50 deletions(-)
create mode 100644 tcg/sparc/tcg-target-constr.h
diff --git a/tcg/sparc/tcg-target-constr.h b/tcg/sparc/tcg-target-constr.h
new file mode 100644
index 0000000000..28aec2ae0f
--- /dev/null
+++ b/tcg/sparc/tcg-target-constr.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Sparc target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(rZ, r)
+C_O0_I2(RZ, r)
+C_O0_I2(rZ, rJ)
+C_O0_I2(RZ, RJ)
+C_O0_I2(sZ, A)
+C_O0_I2(SZ, A)
+C_O1_I1(r, A)
+C_O1_I1(R, A)
+C_O1_I1(r, r)
+C_O1_I1(r, R)
+C_O1_I1(R, r)
+C_O1_I1(R, R)
+C_O1_I2(R, R, R)
+C_O1_I2(r, rZ, rJ)
+C_O1_I2(R, RZ, RJ)
+C_O1_I4(r, rZ, rJ, rI, 0)
+C_O1_I4(R, RZ, RJ, RI, 0)
+C_O2_I2(r, r, rZ, rJ)
+C_O2_I4(R, R, RZ, RZ, RJ, RI)
+C_O2_I4(r, r, rZ, rZ, rJ, rJ)
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index af480115c5..aa426a1c90 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -1592,40 +1592,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef R_r = { .args_ct_str = { "R", "r" } };
- static const TCGTargetOpDef r_R = { .args_ct_str = { "r", "R" } };
- static const TCGTargetOpDef R_R = { .args_ct_str = { "R", "R" } };
- static const TCGTargetOpDef r_A = { .args_ct_str = { "r", "A" } };
- static const TCGTargetOpDef R_A = { .args_ct_str = { "R", "A" } };
- static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef RZ_r = { .args_ct_str = { "RZ", "r" } };
- static const TCGTargetOpDef sZ_A = { .args_ct_str = { "sZ", "A" } };
- static const TCGTargetOpDef SZ_A = { .args_ct_str = { "SZ", "A" } };
- static const TCGTargetOpDef rZ_rJ = { .args_ct_str = { "rZ", "rJ" } };
- static const TCGTargetOpDef RZ_RJ = { .args_ct_str = { "RZ", "RJ" } };
- static const TCGTargetOpDef R_R_R = { .args_ct_str = { "R", "R", "R" } };
- static const TCGTargetOpDef r_rZ_rJ
- = { .args_ct_str = { "r", "rZ", "rJ" } };
- static const TCGTargetOpDef R_RZ_RJ
- = { .args_ct_str = { "R", "RZ", "RJ" } };
- static const TCGTargetOpDef r_r_rZ_rJ
- = { .args_ct_str = { "r", "r", "rZ", "rJ" } };
- static const TCGTargetOpDef movc_32
- = { .args_ct_str = { "r", "rZ", "rJ", "rI", "0" } };
- static const TCGTargetOpDef movc_64
- = { .args_ct_str = { "R", "RZ", "RJ", "RI", "0" } };
- static const TCGTargetOpDef add2_32
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rJ", "rJ" } };
- static const TCGTargetOpDef add2_64
- = { .args_ct_str = { "R", "R", "RZ", "RZ", "RJ", "RI" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
@@ -1634,12 +1608,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld_i32:
case INDEX_op_neg_i32:
case INDEX_op_not_i32:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
case INDEX_op_st_i32:
- return &rZ_r;
+ return C_O0_I2(rZ, r);
case INDEX_op_add_i32:
case INDEX_op_mul_i32:
@@ -1655,18 +1629,18 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
case INDEX_op_setcond_i32:
- return &r_rZ_rJ;
+ return C_O1_I2(r, rZ, rJ);
case INDEX_op_brcond_i32:
- return &rZ_rJ;
+ return C_O0_I2(rZ, rJ);
case INDEX_op_movcond_i32:
- return &movc_32;
+ return C_O1_I4(r, rZ, rJ, rI, 0);
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- return &add2_32;
+ return C_O2_I4(r, r, rZ, rZ, rJ, rJ);
case INDEX_op_mulu2_i32:
case INDEX_op_muls2_i32:
- return &r_r_rZ_rJ;
+ return C_O2_I2(r, r, rZ, rJ);
case INDEX_op_ld8u_i64:
case INDEX_op_ld8s_i64:
@@ -1677,13 +1651,13 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld_i64:
case INDEX_op_ext_i32_i64:
case INDEX_op_extu_i32_i64:
- return &R_r;
+ return C_O1_I1(R, r);
case INDEX_op_st8_i64:
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &RZ_r;
+ return C_O0_I2(RZ, r);
case INDEX_op_add_i64:
case INDEX_op_mul_i64:
@@ -1699,36 +1673,36 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shr_i64:
case INDEX_op_sar_i64:
case INDEX_op_setcond_i64:
- return &R_RZ_RJ;
+ return C_O1_I2(R, RZ, RJ);
case INDEX_op_neg_i64:
case INDEX_op_not_i64:
case INDEX_op_ext32s_i64:
case INDEX_op_ext32u_i64:
- return &R_R;
+ return C_O1_I1(R, R);
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
- return &r_R;
+ return C_O1_I1(r, R);
case INDEX_op_brcond_i64:
- return &RZ_RJ;
+ return C_O0_I2(RZ, RJ);
case INDEX_op_movcond_i64:
- return &movc_64;
+ return C_O1_I4(R, RZ, RJ, RI, 0);
case INDEX_op_add2_i64:
case INDEX_op_sub2_i64:
- return &add2_64;
+ return C_O2_I4(R, R, RZ, RZ, RJ, RI);
case INDEX_op_muluh_i64:
- return &R_R_R;
+ return C_O1_I2(R, R, R);
case INDEX_op_qemu_ld_i32:
- return &r_A;
+ return C_O1_I1(r, A);
case INDEX_op_qemu_ld_i64:
- return &R_A;
+ return C_O1_I1(R, A);
case INDEX_op_qemu_st_i32:
- return &sZ_A;
+ return C_O0_I2(sZ, A);
case INDEX_op_qemu_st_i64:
- return &SZ_A;
+ return C_O0_I2(SZ, A);
default:
return NULL;
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 43/43] tcg/tci: Convert to tcg-constr.c.inc
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
` (41 preceding siblings ...)
2020-09-09 0:16 ` [PATCH 42/43] tcg/sparc: " Richard Henderson
@ 2020-09-09 0:16 ` Richard Henderson
42 siblings, 0 replies; 48+ messages in thread
From: Richard Henderson @ 2020-09-09 0:16 UTC (permalink / raw)
To: qemu-devel
This does require finishing the conversion to tcg_target_op_def.
Remove quite a lot of ifdefs, since we can reference opcodes
even if they are not implemented.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target-constr.h | 28 +++
tcg/tci/tcg-target.c.inc | 360 ++++++++++++++----------------------
2 files changed, 163 insertions(+), 225 deletions(-)
create mode 100644 tcg/tci/tcg-target-constr.h
diff --git a/tcg/tci/tcg-target-constr.h b/tcg/tci/tcg-target-constr.h
new file mode 100644
index 0000000000..6658e905e6
--- /dev/null
+++ b/tcg/tci/tcg-target-constr.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * TCI target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O0_I2(r, S)
+C_O0_I3(r, r, S)
+C_O0_I3(r, S, S)
+C_O0_I4(r, r, S, S)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, r)
+C_O1_I2(r, L, L)
+C_O1_I2(r, ri, ri)
+C_O1_I2(r, r, r)
+C_O1_I2(r, r, ri)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+
+#if TCG_TARGET_REG_BITS == 32
+C_O0_I4(r, r, ri, ri)
+C_O1_I4(r, r, r, ri, ri)
+C_O2_I2(r, r, r, r)
+C_O2_I4(r, r, r, r, r, r)
+#endif
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 25ed868505..350cb498d7 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -37,236 +37,146 @@
/* Bitfield n...m (in 32 bit value). */
#define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
-/* Macros used in tcg_target_op_defs. */
-#define R "r"
-#define RI "ri"
-#if TCG_TARGET_REG_BITS == 32
-# define R64 "r", "r"
-#else
-# define R64 "r"
-#endif
-#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
-# define L "L", "L"
-# define S "S", "S"
-#else
-# define L "L"
-# define S "S"
-#endif
-
-/* TODO: documentation. */
-static const TCGTargetOpDef tcg_target_op_defs[] = {
- { INDEX_op_exit_tb, { NULL } },
- { INDEX_op_goto_tb, { NULL } },
- { INDEX_op_br, { NULL } },
-
- { INDEX_op_ld8u_i32, { R, R } },
- { INDEX_op_ld8s_i32, { R, R } },
- { INDEX_op_ld16u_i32, { R, R } },
- { INDEX_op_ld16s_i32, { R, R } },
- { INDEX_op_ld_i32, { R, R } },
- { INDEX_op_st8_i32, { R, R } },
- { INDEX_op_st16_i32, { R, R } },
- { INDEX_op_st_i32, { R, R } },
-
- { INDEX_op_add_i32, { R, RI, RI } },
- { INDEX_op_sub_i32, { R, RI, RI } },
- { INDEX_op_mul_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i32
- { INDEX_op_div_i32, { R, R, R } },
- { INDEX_op_divu_i32, { R, R, R } },
- { INDEX_op_rem_i32, { R, R, R } },
- { INDEX_op_remu_i32, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i32
- { INDEX_op_div2_i32, { R, R, "0", "1", R } },
- { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
-#endif
- /* TODO: Does R, RI, RI result in faster code than R, R, RI?
- If both operands are constants, we can optimize. */
- { INDEX_op_and_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_andc_i32
- { INDEX_op_andc_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_eqv_i32
- { INDEX_op_eqv_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nand_i32
- { INDEX_op_nand_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nor_i32
- { INDEX_op_nor_i32, { R, RI, RI } },
-#endif
- { INDEX_op_or_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_orc_i32
- { INDEX_op_orc_i32, { R, RI, RI } },
-#endif
- { INDEX_op_xor_i32, { R, RI, RI } },
- { INDEX_op_shl_i32, { R, RI, RI } },
- { INDEX_op_shr_i32, { R, RI, RI } },
- { INDEX_op_sar_i32, { R, RI, RI } },
-#if TCG_TARGET_HAS_rot_i32
- { INDEX_op_rotl_i32, { R, RI, RI } },
- { INDEX_op_rotr_i32, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_deposit_i32
- { INDEX_op_deposit_i32, { R, "0", R } },
-#endif
-
- { INDEX_op_brcond_i32, { R, RI } },
-
- { INDEX_op_setcond_i32, { R, R, RI } },
-#if TCG_TARGET_REG_BITS == 64
- { INDEX_op_setcond_i64, { R, R, RI } },
-#endif /* TCG_TARGET_REG_BITS == 64 */
-
-#if TCG_TARGET_REG_BITS == 32
- /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
- { INDEX_op_add2_i32, { R, R, R, R, R, R } },
- { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
- { INDEX_op_brcond2_i32, { R, R, RI, RI } },
- { INDEX_op_mulu2_i32, { R, R, R, R } },
- { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
-#endif
-
-#if TCG_TARGET_HAS_not_i32
- { INDEX_op_not_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_neg_i32
- { INDEX_op_neg_i32, { R, R } },
-#endif
-
-#if TCG_TARGET_REG_BITS == 64
- { INDEX_op_ld8u_i64, { R, R } },
- { INDEX_op_ld8s_i64, { R, R } },
- { INDEX_op_ld16u_i64, { R, R } },
- { INDEX_op_ld16s_i64, { R, R } },
- { INDEX_op_ld32u_i64, { R, R } },
- { INDEX_op_ld32s_i64, { R, R } },
- { INDEX_op_ld_i64, { R, R } },
-
- { INDEX_op_st8_i64, { R, R } },
- { INDEX_op_st16_i64, { R, R } },
- { INDEX_op_st32_i64, { R, R } },
- { INDEX_op_st_i64, { R, R } },
-
- { INDEX_op_add_i64, { R, RI, RI } },
- { INDEX_op_sub_i64, { R, RI, RI } },
- { INDEX_op_mul_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_div_i64
- { INDEX_op_div_i64, { R, R, R } },
- { INDEX_op_divu_i64, { R, R, R } },
- { INDEX_op_rem_i64, { R, R, R } },
- { INDEX_op_remu_i64, { R, R, R } },
-#elif TCG_TARGET_HAS_div2_i64
- { INDEX_op_div2_i64, { R, R, "0", "1", R } },
- { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
-#endif
- { INDEX_op_and_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_andc_i64
- { INDEX_op_andc_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_eqv_i64
- { INDEX_op_eqv_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nand_i64
- { INDEX_op_nand_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_nor_i64
- { INDEX_op_nor_i64, { R, RI, RI } },
-#endif
- { INDEX_op_or_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_orc_i64
- { INDEX_op_orc_i64, { R, RI, RI } },
-#endif
- { INDEX_op_xor_i64, { R, RI, RI } },
- { INDEX_op_shl_i64, { R, RI, RI } },
- { INDEX_op_shr_i64, { R, RI, RI } },
- { INDEX_op_sar_i64, { R, RI, RI } },
-#if TCG_TARGET_HAS_rot_i64
- { INDEX_op_rotl_i64, { R, RI, RI } },
- { INDEX_op_rotr_i64, { R, RI, RI } },
-#endif
-#if TCG_TARGET_HAS_deposit_i64
- { INDEX_op_deposit_i64, { R, "0", R } },
-#endif
- { INDEX_op_brcond_i64, { R, RI } },
-
-#if TCG_TARGET_HAS_ext8s_i64
- { INDEX_op_ext8s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16s_i64
- { INDEX_op_ext16s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext32s_i64
- { INDEX_op_ext32s_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext8u_i64
- { INDEX_op_ext8u_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16u_i64
- { INDEX_op_ext16u_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext32u_i64
- { INDEX_op_ext32u_i64, { R, R } },
-#endif
- { INDEX_op_ext_i32_i64, { R, R } },
- { INDEX_op_extu_i32_i64, { R, R } },
-#if TCG_TARGET_HAS_bswap16_i64
- { INDEX_op_bswap16_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap32_i64
- { INDEX_op_bswap32_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap64_i64
- { INDEX_op_bswap64_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_not_i64
- { INDEX_op_not_i64, { R, R } },
-#endif
-#if TCG_TARGET_HAS_neg_i64
- { INDEX_op_neg_i64, { R, R } },
-#endif
-#endif /* TCG_TARGET_REG_BITS == 64 */
-
- { INDEX_op_qemu_ld_i32, { R, L } },
- { INDEX_op_qemu_ld_i64, { R64, L } },
-
- { INDEX_op_qemu_st_i32, { R, S } },
- { INDEX_op_qemu_st_i64, { R64, S } },
-
-#if TCG_TARGET_HAS_ext8s_i32
- { INDEX_op_ext8s_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16s_i32
- { INDEX_op_ext16s_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext8u_i32
- { INDEX_op_ext8u_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_ext16u_i32
- { INDEX_op_ext16u_i32, { R, R } },
-#endif
-
-#if TCG_TARGET_HAS_bswap16_i32
- { INDEX_op_bswap16_i32, { R, R } },
-#endif
-#if TCG_TARGET_HAS_bswap32_i32
- { INDEX_op_bswap32_i32, { R, R } },
-#endif
-
- { INDEX_op_mb, { } },
- { -1 },
-};
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- int i, n = ARRAY_SIZE(tcg_target_op_defs);
+ switch (op) {
+ case INDEX_op_ld8u_i32:
+ case INDEX_op_ld8s_i32:
+ case INDEX_op_ld16u_i32:
+ case INDEX_op_ld16s_i32:
+ case INDEX_op_ld_i32:
+ case INDEX_op_ld8u_i64:
+ case INDEX_op_ld8s_i64:
+ case INDEX_op_ld16u_i64:
+ case INDEX_op_ld16s_i64:
+ case INDEX_op_ld32u_i64:
+ case INDEX_op_ld32s_i64:
+ case INDEX_op_ld_i64:
+ case INDEX_op_not_i32:
+ case INDEX_op_not_i64:
+ case INDEX_op_neg_i32:
+ case INDEX_op_neg_i64:
+ case INDEX_op_ext8s_i32:
+ case INDEX_op_ext8s_i64:
+ case INDEX_op_ext16s_i32:
+ case INDEX_op_ext16s_i64:
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
+ case INDEX_op_ext16u_i32:
+ case INDEX_op_ext16u_i64:
+ case INDEX_op_ext32s_i64:
+ case INDEX_op_ext32u_i64:
+ case INDEX_op_ext_i32_i64:
+ case INDEX_op_extu_i32_i64:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
+ return C_O1_I1(r, r);
- for (i = 0; i < n; ++i) {
- if (tcg_target_op_defs[i].op == op) {
- return &tcg_target_op_defs[i];
- }
+ case INDEX_op_st8_i32:
+ case INDEX_op_st16_i32:
+ case INDEX_op_st_i32:
+ case INDEX_op_st8_i64:
+ case INDEX_op_st16_i64:
+ case INDEX_op_st32_i64:
+ case INDEX_op_st_i64:
+ return C_O0_I2(r, r);
+
+ case INDEX_op_div_i32:
+ case INDEX_op_div_i64:
+ case INDEX_op_divu_i32:
+ case INDEX_op_divu_i64:
+ case INDEX_op_rem_i32:
+ case INDEX_op_rem_i64:
+ case INDEX_op_remu_i32:
+ case INDEX_op_remu_i64:
+ return C_O1_I2(r, r, r);
+
+ case INDEX_op_add_i32:
+ case INDEX_op_add_i64:
+ case INDEX_op_sub_i32:
+ case INDEX_op_sub_i64:
+ case INDEX_op_mul_i32:
+ case INDEX_op_mul_i64:
+ case INDEX_op_and_i32:
+ case INDEX_op_and_i64:
+ case INDEX_op_andc_i32:
+ case INDEX_op_andc_i64:
+ case INDEX_op_eqv_i32:
+ case INDEX_op_eqv_i64:
+ case INDEX_op_nand_i32:
+ case INDEX_op_nand_i64:
+ case INDEX_op_nor_i32:
+ case INDEX_op_nor_i64:
+ case INDEX_op_or_i32:
+ case INDEX_op_or_i64:
+ case INDEX_op_orc_i32:
+ case INDEX_op_orc_i64:
+ case INDEX_op_xor_i32:
+ case INDEX_op_xor_i64:
+ case INDEX_op_shl_i32:
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i32:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i32:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotr_i64:
+ /* TODO: Does R, RI, RI result in faster code than R, R, RI? */
+ return C_O1_I2(r, ri, ri);
+
+ case INDEX_op_deposit_i32:
+ case INDEX_op_deposit_i64:
+ return C_O1_I2(r, 0, r);
+
+ case INDEX_op_brcond_i32:
+ case INDEX_op_brcond_i64:
+ return C_O0_I2(r, ri);
+
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ return C_O1_I2(r, r, ri);
+
+#if TCG_TARGET_REG_BITS == 32
+ /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
+ case INDEX_op_add2_i32:
+ case INDEX_op_sub2_i32:
+ return C_O2_I4(r, r, r, r, r, r);
+ case INDEX_op_brcond2_i32:
+ return C_O0_I4(r, r, ri, ri);
+ case INDEX_op_mulu2_i32:
+ return C_O2_I2(r, r, r, r);
+ case INDEX_op_setcond2_i32
+ return C_O1_I4(r, r, r, ri, ri);
+#endif
+
+ case INDEX_op_qemu_ld_i32:
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O1_I1(r, L)
+ : C_O1_I2(r, L, L));
+ case INDEX_op_qemu_ld_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
+ : C_O2_I2(r, r, L, L));
+ case INDEX_op_qemu_st_i32:
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O0_I2(r, S)
+ : C_O0_I3(r, S, S));
+ case INDEX_op_qemu_st_i64:
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, S)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(r, r, S)
+ : C_O0_I4(r, r, S, S));
+
+ default:
+ return NULL;
}
- return NULL;
}
static const int tcg_target_reg_alloc_order[] = {
--
2.25.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PATCH 02/43] tcg: Drop union from TCGArgConstraint
2020-09-09 0:16 ` [PATCH 02/43] tcg: Drop union from TCGArgConstraint Richard Henderson
@ 2020-09-09 17:43 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 48+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-09 17:43 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 9/9/20 2:16 AM, Richard Henderson wrote:
> The union is unused; let "regs" appear in the main structure
> without the "u.regs" wrapping.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg.h | 4 +---
> tcg/tcg.c | 22 +++++++++++-----------
> tcg/aarch64/tcg-target.c.inc | 14 +++++++-------
> tcg/arm/tcg-target.c.inc | 26 +++++++++++++-------------
> tcg/i386/tcg-target.c.inc | 26 +++++++++++++-------------
> tcg/mips/tcg-target.c.inc | 18 +++++++++---------
> tcg/ppc/tcg-target.c.inc | 24 ++++++++++++------------
> tcg/riscv/tcg-target.c.inc | 14 +++++++-------
> tcg/s390/tcg-target.c.inc | 18 +++++++++---------
> tcg/sparc/tcg-target.c.inc | 16 ++++++++--------
> tcg/tci/tcg-target.c.inc | 2 +-
> 11 files changed, 91 insertions(+), 93 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 06/43] tcg: Remove TCGOpDef.used
2020-09-09 0:16 ` [PATCH 06/43] tcg: Remove TCGOpDef.used Richard Henderson
@ 2020-09-09 17:45 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 48+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-09 17:45 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 9/9/20 2:16 AM, Richard Henderson wrote:
> The last user of this field disappeared in f69d277ece4.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg.h | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
> index e8629b58c8..8804a8c4a2 100644
> --- a/include/tcg/tcg.h
> +++ b/include/tcg/tcg.h
> @@ -1015,9 +1015,6 @@ typedef struct TCGOpDef {
> uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
> uint8_t flags;
> TCGArgConstraint *args_ct;
> -#if defined(CONFIG_DEBUG_TCG)
> - int used;
> -#endif
> } TCGOpDef;
>
> extern TCGOpDef tcg_op_defs[];
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec
2020-09-09 0:16 ` [PATCH 10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec Richard Henderson
@ 2020-09-09 17:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 48+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-09 17:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel
On 9/9/20 2:16 AM, Richard Henderson wrote:
> The cmp_vec opcode is mandatory; this symbol is unused.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> tcg/aarch64/tcg-target.h | 1 -
> tcg/i386/tcg-target.h | 1 -
> tcg/ppc/tcg-target.h | 1 -
> 3 files changed, 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 13/43] tcg: Consolidate 3 bits into enum TCGTempKind
2020-09-09 0:16 ` [PATCH 13/43] tcg: Consolidate 3 bits into enum TCGTempKind Richard Henderson
@ 2020-09-09 17:52 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 48+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-09 17:52 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: Alex Bennée
On 9/9/20 2:16 AM, Richard Henderson wrote:
> The temp_fixed, temp_global, temp_local bits are all related.
> Combine them into a single enumeration.
>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Already reviewed:
https://www.mail-archive.com/qemu-devel@nongnu.org/msg701705.html
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> include/tcg/tcg.h | 20 +++++---
> tcg/optimize.c | 8 +--
> tcg/tcg.c | 122 ++++++++++++++++++++++++++++------------------
> 3 files changed, 90 insertions(+), 60 deletions(-)
>
> diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
> index 8804a8c4a2..f157092b51 100644
> --- a/include/tcg/tcg.h
> +++ b/include/tcg/tcg.h
> @@ -483,23 +483,27 @@ typedef enum TCGTempVal {
> TEMP_VAL_CONST,
> } TCGTempVal;
>
> +typedef enum TCGTempKind {
> + /* Temp is dead at the end of all basic blocks. */
> + TEMP_NORMAL,
> + /* Temp is saved across basic blocks but dead at the end of TBs. */
> + TEMP_LOCAL,
> + /* Temp is saved across both basic blocks and translation blocks. */
> + TEMP_GLOBAL,
> + /* Temp is in a fixed register. */
> + TEMP_FIXED,
> +} TCGTempKind;
> +
> typedef struct TCGTemp {
> TCGReg reg:8;
> TCGTempVal val_type:8;
> TCGType base_type:8;
> TCGType type:8;
> - unsigned int fixed_reg:1;
> + TCGTempKind kind:3;
3 bits for TEMP_CONST later.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> unsigned int indirect_reg:1;
> unsigned int indirect_base:1;
> unsigned int mem_coherent:1;
> unsigned int mem_allocated:1;
> - /* If true, the temp is saved across both basic blocks and
> - translation blocks. */
> - unsigned int temp_global:1;
> - /* If true, the temp is saved across basic blocks but dead
> - at the end of translation blocks. If false, the temp is
> - dead at the end of basic blocks. */
> - unsigned int temp_local:1;
> unsigned int temp_allocated:1;
>
^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2020-09-09 17:53 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
2020-09-09 0:16 ` [PATCH 01/43] tcg: Adjust simd_desc size encoding Richard Henderson
2020-09-09 0:16 ` [PATCH 02/43] tcg: Drop union from TCGArgConstraint Richard Henderson
2020-09-09 17:43 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 03/43] tcg: Move sorted_args into TCGArgConstraint.sort_index Richard Henderson
2020-09-09 0:16 ` [PATCH 04/43] tcg: Remove TCG_CT_REG Richard Henderson
2020-09-09 0:16 ` [PATCH 05/43] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields Richard Henderson
2020-09-09 0:16 ` [PATCH 06/43] tcg: Remove TCGOpDef.used Richard Henderson
2020-09-09 17:45 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 07/43] tcg/i386: Fix dupi for avx2 32-bit hosts Richard Henderson
2020-09-09 0:16 ` [PATCH 08/43] tcg: Fix generation of dupi_vec for 32-bit host Richard Henderson
2020-09-09 0:16 ` [PATCH 09/43] tcg/optimize: Fold dup2_vec Richard Henderson
2020-09-09 0:16 ` [PATCH 10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec Richard Henderson
2020-09-09 17:47 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 11/43] tcg: Use tcg_out_dupi_vec from temp_load Richard Henderson
2020-09-09 0:16 ` [PATCH 12/43] tcg: Increase tcg_out_dupi_vec immediate to int64_t Richard Henderson
2020-09-09 0:16 ` [PATCH 13/43] tcg: Consolidate 3 bits into enum TCGTempKind Richard Henderson
2020-09-09 17:52 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 14/43] tcg: Add temp_readonly Richard Henderson
2020-09-09 0:16 ` [PATCH 15/43] tcg: Expand TCGTemp.val to 64-bits Richard Henderson
2020-09-09 0:16 ` [PATCH 16/43] tcg: Rename struct tcg_temp_info to TempOptInfo Richard Henderson
2020-09-09 0:16 ` [PATCH 17/43] tcg: Expand TempOptInfo to 64-bits Richard Henderson
2020-09-09 0:16 ` [PATCH 18/43] tcg: Introduce TYPE_CONST temporaries Richard Henderson
2020-09-09 0:16 ` [PATCH 19/43] tcg/optimize: Improve find_better_copy Richard Henderson
2020-09-09 0:16 ` [PATCH 20/43] tcg/optimize: Adjust TempOptInfo allocation Richard Henderson
2020-09-09 0:16 ` [PATCH 21/43] tcg/optimize: Use tcg_constant_internal with constant folding Richard Henderson
2020-09-09 0:16 ` [PATCH 22/43] tcg: Convert tcg_gen_dupi_vec to TCG_CONST Richard Henderson
2020-09-09 0:16 ` [PATCH 23/43] tcg: Use tcg_constant_i32 with icount expander Richard Henderson
2020-09-09 0:16 ` [PATCH 24/43] tcg: Use tcg_constant_{i32,i64} with tcg int expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 25/43] tcg: Use tcg_constant_{i32,i64} with tcg plugins Richard Henderson
2020-09-09 0:16 ` [PATCH 26/43] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 27/43] tcg/tci: Add special tci_movi_{i32,i64} opcodes Richard Henderson
2020-09-09 0:16 ` [PATCH 28/43] tcg: Remove movi and dupi opcodes Richard Henderson
2020-09-09 0:16 ` [PATCH 29/43] tcg: Add tcg_reg_alloc_dup2 Richard Henderson
2020-09-09 0:16 ` [PATCH 30/43] tcg/i386: Use tcg_constant_vec with tcg vec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 31/43] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec Richard Henderson
2020-09-09 0:16 ` [PATCH 32/43] tcg/ppc: Use tcg_constant_vec with tcg vec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 33/43] tcg/aarch64: " Richard Henderson
2020-09-09 0:16 ` [PATCH 34/43] tcg: Add tcg-constr.c.inc Richard Henderson
2020-09-09 0:16 ` [PATCH 35/43] tcg/i386: Convert to tcg-constr.c.inc Richard Henderson
2020-09-09 0:16 ` [PATCH 36/43] tcg/aarch64: " Richard Henderson
2020-09-09 0:16 ` [PATCH 37/43] tcg/arm: " Richard Henderson
2020-09-09 0:16 ` [PATCH 38/43] tcg/mips: " Richard Henderson
2020-09-09 0:16 ` [PATCH 39/43] tcg/ppc: " Richard Henderson
2020-09-09 0:16 ` [PATCH 40/43] tcg/riscv: " Richard Henderson
2020-09-09 0:16 ` [PATCH 41/43] tcg/s390: " Richard Henderson
2020-09-09 0:16 ` [PATCH 42/43] tcg/sparc: " Richard Henderson
2020-09-09 0:16 ` [PATCH 43/43] tcg/tci: " Richard Henderson
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