From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 40/43] tcg/riscv: Convert to tcg-constr.c.inc
Date: Tue, 8 Sep 2020 17:16:44 -0700 [thread overview]
Message-ID: <20200909001647.532249-41-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target-constr.h | 25 +++++++++++
tcg/riscv/tcg-target.c.inc | 82 ++++++++++-------------------------
2 files changed, 49 insertions(+), 58 deletions(-)
create mode 100644 tcg/riscv/tcg-target-constr.h
diff --git a/tcg/riscv/tcg-target-constr.h b/tcg/riscv/tcg-target-constr.h
new file mode 100644
index 0000000000..aeff74034c
--- /dev/null
+++ b/tcg/riscv/tcg-target-constr.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * RISC-V target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(LZ, L)
+C_O0_I2(rZ, r)
+C_O0_I2(rZ, rZ)
+C_O0_I3(LZ, L, L)
+C_O0_I3(LZ, LZ, L)
+C_O0_I4(LZ, LZ, L, L)
+C_O0_I4(rZ, rZ, rZ, rZ)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, L, L)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
+C_O1_I2(r, rZ, rN)
+C_O1_I2(r, rZ, rZ)
+C_O1_I4(r, rZ, rZ, rZ, rZ)
+C_O2_I1(r, r, L)
+C_O2_I2(r, r, L, L)
+C_O2_I4(r, r, rZ, rZ, rM, rM)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index aaef1c5eed..042a41e1f4 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1608,50 +1608,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r
- = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r
- = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef rZ_r
- = { .args_ct_str = { "rZ", "r" } };
- static const TCGTargetOpDef rZ_rZ
- = { .args_ct_str = { "rZ", "rZ" } };
- static const TCGTargetOpDef rZ_rZ_rZ_rZ
- = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef r_r_ri
- = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_r_rI
- = { .args_ct_str = { "r", "r", "rI" } };
- static const TCGTargetOpDef r_rZ_rN
- = { .args_ct_str = { "r", "rZ", "rN" } };
- static const TCGTargetOpDef r_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ" } };
- static const TCGTargetOpDef r_rZ_rZ_rZ_rZ
- = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } };
- static const TCGTargetOpDef r_L
- = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef r_r_L
- = { .args_ct_str = { "r", "r", "L" } };
- static const TCGTargetOpDef r_L_L
- = { .args_ct_str = { "r", "L", "L" } };
- static const TCGTargetOpDef r_r_L_L
- = { .args_ct_str = { "r", "r", "L", "L" } };
- static const TCGTargetOpDef LZ_L
- = { .args_ct_str = { "LZ", "L" } };
- static const TCGTargetOpDef LZ_L_L
- = { .args_ct_str = { "LZ", "L", "L" } };
- static const TCGTargetOpDef LZ_LZ_L
- = { .args_ct_str = { "LZ", "LZ", "L" } };
- static const TCGTargetOpDef LZ_LZ_L_L
- = { .args_ct_str = { "LZ", "LZ", "L", "L" } };
- static const TCGTargetOpDef r_r_rZ_rZ_rM_rM
- = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8s_i32:
@@ -1683,7 +1647,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
- return &r_r;
+ return C_O1_I1(r, r);
case INDEX_op_st8_i32:
case INDEX_op_st16_i32:
@@ -1692,7 +1656,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &rZ_r;
+ return C_O0_I2(rZ, r);
case INDEX_op_add_i32:
case INDEX_op_and_i32:
@@ -1702,11 +1666,11 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_and_i64:
case INDEX_op_or_i64:
case INDEX_op_xor_i64:
- return &r_r_rI;
+ return C_O1_I2(r, r, rI);
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
- return &r_rZ_rN;
+ return C_O1_I2(r, rZ, rN);
case INDEX_op_mul_i32:
case INDEX_op_mulsh_i32:
@@ -1724,7 +1688,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_rem_i64:
case INDEX_op_remu_i64:
case INDEX_op_setcond_i64:
- return &r_rZ_rZ;
+ return C_O1_I2(r, rZ, rZ);
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
@@ -1732,36 +1696,38 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shl_i64:
case INDEX_op_shr_i64:
case INDEX_op_sar_i64:
- return &r_r_ri;
+ return C_O1_I2(r, r, ri);
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &rZ_rZ;
+ return C_O0_I2(rZ, rZ);
case INDEX_op_add2_i32:
case INDEX_op_add2_i64:
case INDEX_op_sub2_i32:
case INDEX_op_sub2_i64:
- return &r_r_rZ_rZ_rM_rM;
+ return C_O2_I4(r, r, rZ, rZ, rM, rM);
case INDEX_op_brcond2_i32:
- return &rZ_rZ_rZ_rZ;
+ return C_O0_I4(rZ, rZ, rZ, rZ);
case INDEX_op_setcond2_i32:
- return &r_rZ_rZ_rZ_rZ;
+ return C_O1_I4(r, rZ, rZ, rZ, rZ);
case INDEX_op_qemu_ld_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L;
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O1_I1(r, L) : C_O1_I2(r, L, L));
case INDEX_op_qemu_st_i32:
- return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L;
+ return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
+ ? C_O0_I2(LZ, L) : C_O0_I3(LZ, L, L));
case INDEX_op_qemu_ld_i64:
- return TCG_TARGET_REG_BITS == 64 ? &r_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L
- : &r_r_L_L;
+ return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, L)
+ : C_O2_I2(r, r, L, L));
case INDEX_op_qemu_st_i64:
- return TCG_TARGET_REG_BITS == 64 ? &LZ_L
- : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L
- : &LZ_LZ_L_L;
+ return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(LZ, L)
+ : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(LZ, LZ, L)
+ : C_O0_I4(LZ, LZ, L, L));
default:
return NULL;
--
2.25.1
next prev parent reply other threads:[~2020-09-09 0:30 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
2020-09-09 0:16 ` [PATCH 01/43] tcg: Adjust simd_desc size encoding Richard Henderson
2020-09-09 0:16 ` [PATCH 02/43] tcg: Drop union from TCGArgConstraint Richard Henderson
2020-09-09 17:43 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 03/43] tcg: Move sorted_args into TCGArgConstraint.sort_index Richard Henderson
2020-09-09 0:16 ` [PATCH 04/43] tcg: Remove TCG_CT_REG Richard Henderson
2020-09-09 0:16 ` [PATCH 05/43] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields Richard Henderson
2020-09-09 0:16 ` [PATCH 06/43] tcg: Remove TCGOpDef.used Richard Henderson
2020-09-09 17:45 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 07/43] tcg/i386: Fix dupi for avx2 32-bit hosts Richard Henderson
2020-09-09 0:16 ` [PATCH 08/43] tcg: Fix generation of dupi_vec for 32-bit host Richard Henderson
2020-09-09 0:16 ` [PATCH 09/43] tcg/optimize: Fold dup2_vec Richard Henderson
2020-09-09 0:16 ` [PATCH 10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec Richard Henderson
2020-09-09 17:47 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 11/43] tcg: Use tcg_out_dupi_vec from temp_load Richard Henderson
2020-09-09 0:16 ` [PATCH 12/43] tcg: Increase tcg_out_dupi_vec immediate to int64_t Richard Henderson
2020-09-09 0:16 ` [PATCH 13/43] tcg: Consolidate 3 bits into enum TCGTempKind Richard Henderson
2020-09-09 17:52 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 14/43] tcg: Add temp_readonly Richard Henderson
2020-09-09 0:16 ` [PATCH 15/43] tcg: Expand TCGTemp.val to 64-bits Richard Henderson
2020-09-09 0:16 ` [PATCH 16/43] tcg: Rename struct tcg_temp_info to TempOptInfo Richard Henderson
2020-09-09 0:16 ` [PATCH 17/43] tcg: Expand TempOptInfo to 64-bits Richard Henderson
2020-09-09 0:16 ` [PATCH 18/43] tcg: Introduce TYPE_CONST temporaries Richard Henderson
2020-09-09 0:16 ` [PATCH 19/43] tcg/optimize: Improve find_better_copy Richard Henderson
2020-09-09 0:16 ` [PATCH 20/43] tcg/optimize: Adjust TempOptInfo allocation Richard Henderson
2020-09-09 0:16 ` [PATCH 21/43] tcg/optimize: Use tcg_constant_internal with constant folding Richard Henderson
2020-09-09 0:16 ` [PATCH 22/43] tcg: Convert tcg_gen_dupi_vec to TCG_CONST Richard Henderson
2020-09-09 0:16 ` [PATCH 23/43] tcg: Use tcg_constant_i32 with icount expander Richard Henderson
2020-09-09 0:16 ` [PATCH 24/43] tcg: Use tcg_constant_{i32,i64} with tcg int expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 25/43] tcg: Use tcg_constant_{i32,i64} with tcg plugins Richard Henderson
2020-09-09 0:16 ` [PATCH 26/43] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 27/43] tcg/tci: Add special tci_movi_{i32,i64} opcodes Richard Henderson
2020-09-09 0:16 ` [PATCH 28/43] tcg: Remove movi and dupi opcodes Richard Henderson
2020-09-09 0:16 ` [PATCH 29/43] tcg: Add tcg_reg_alloc_dup2 Richard Henderson
2020-09-09 0:16 ` [PATCH 30/43] tcg/i386: Use tcg_constant_vec with tcg vec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 31/43] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec Richard Henderson
2020-09-09 0:16 ` [PATCH 32/43] tcg/ppc: Use tcg_constant_vec with tcg vec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 33/43] tcg/aarch64: " Richard Henderson
2020-09-09 0:16 ` [PATCH 34/43] tcg: Add tcg-constr.c.inc Richard Henderson
2020-09-09 0:16 ` [PATCH 35/43] tcg/i386: Convert to tcg-constr.c.inc Richard Henderson
2020-09-09 0:16 ` [PATCH 36/43] tcg/aarch64: " Richard Henderson
2020-09-09 0:16 ` [PATCH 37/43] tcg/arm: " Richard Henderson
2020-09-09 0:16 ` [PATCH 38/43] tcg/mips: " Richard Henderson
2020-09-09 0:16 ` [PATCH 39/43] tcg/ppc: " Richard Henderson
2020-09-09 0:16 ` Richard Henderson [this message]
2020-09-09 0:16 ` [PATCH 41/43] tcg/s390: " Richard Henderson
2020-09-09 0:16 ` [PATCH 42/43] tcg/sparc: " Richard Henderson
2020-09-09 0:16 ` [PATCH 43/43] tcg/tci: " Richard Henderson
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