From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 41/43] tcg/s390: Convert to tcg-constr.c.inc
Date: Tue, 8 Sep 2020 17:16:45 -0700 [thread overview]
Message-ID: <20200909001647.532249-42-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390/tcg-target-constr.h | 24 +++++++
tcg/s390/tcg-target.c.inc | 119 +++++++++++++++--------------------
2 files changed, 76 insertions(+), 67 deletions(-)
create mode 100644 tcg/s390/tcg-target-constr.h
diff --git a/tcg/s390/tcg-target-constr.h b/tcg/s390/tcg-target-constr.h
new file mode 100644
index 0000000000..06c1f4a944
--- /dev/null
+++ b/tcg/s390/tcg-target-constr.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * S390 target-specific operand constaints.
+ * Copyright (c) 2020 Linaro
+ */
+
+C_O0_I1(r)
+C_O0_I2(L, L)
+C_O0_I2(r, r)
+C_O0_I2(r, ri)
+C_O1_I1(r, L)
+C_O1_I1(r, r)
+C_O1_I2(r, 0, ri)
+C_O1_I2(r, 0, rI)
+C_O1_I2(r, 0, rJ)
+C_O1_I2(r, r, ri)
+C_O1_I2(r, rZ, r)
+C_O1_I4(r, r, ri, r, 0)
+C_O1_I4(r, r, ri, rI, 0)
+C_O2_I2(b, a, 0, r)
+C_O2_I3(b, a, 0, 1, r)
+C_O2_I4(r, r, 0, 1, rA, r)
+C_O2_I4(r, r, 0, 1, ri, r)
+C_O2_I4(r, r, 0, 1, r, r)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 824a07aa7a..c628194421 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -2312,27 +2312,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
}
+/* Define all constraint sets. */
+#include "../tcg-constr.c.inc"
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
- static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
- static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } };
- static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
- static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } };
- static const TCGTargetOpDef r_ri = { .args_ct_str = { "r", "ri" } };
- static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
- static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } };
- static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } };
- static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } };
- static const TCGTargetOpDef a2_r
- = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } };
- static const TCGTargetOpDef a2_ri
- = { .args_ct_str = { "r", "r", "0", "1", "ri", "r" } };
- static const TCGTargetOpDef a2_rA
- = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } };
-
switch (op) {
case INDEX_op_goto_ptr:
- return &r;
+ return C_O0_I1(r);
case INDEX_op_ld8u_i32:
case INDEX_op_ld8u_i64:
@@ -2346,6 +2333,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ld32u_i64:
case INDEX_op_ld32s_i64:
case INDEX_op_ld_i64:
+ return C_O1_I1(r, r);
+
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
case INDEX_op_st16_i32:
@@ -2353,11 +2342,22 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
case INDEX_op_st_i64:
- return &r_r;
+ return C_O0_I2(r, r);
case INDEX_op_add_i32:
case INDEX_op_add_i64:
- return &r_r_ri;
+ case INDEX_op_shl_i64:
+ case INDEX_op_shr_i64:
+ case INDEX_op_sar_i64:
+ case INDEX_op_rotl_i32:
+ case INDEX_op_rotl_i64:
+ case INDEX_op_rotr_i32:
+ case INDEX_op_rotr_i64:
+ case INDEX_op_clz_i64:
+ case INDEX_op_setcond_i32:
+ case INDEX_op_setcond_i64:
+ return C_O1_I2(r, r, ri);
+
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_and_i32:
@@ -2366,35 +2366,33 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_or_i64:
case INDEX_op_xor_i32:
case INDEX_op_xor_i64:
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
+ return (s390_facilities & FACILITY_DISTINCT_OPS
+ ? C_O1_I2(r, r, ri)
+ : C_O1_I2(r, 0, ri));
case INDEX_op_mul_i32:
/* If we have the general-instruction-extensions, then we have
MULTIPLY SINGLE IMMEDIATE with a signed 32-bit, otherwise we
have only MULTIPLY HALFWORD IMMEDIATE, with a signed 16-bit. */
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_ri : &r_0_rI);
+ return (s390_facilities & FACILITY_GEN_INST_EXT
+ ? C_O1_I2(r, 0, ri)
+ : C_O1_I2(r, 0, rI));
+
case INDEX_op_mul_i64:
- return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);
+ return (s390_facilities & FACILITY_GEN_INST_EXT
+ ? C_O1_I2(r, 0, rJ)
+ : C_O1_I2(r, 0, rI));
case INDEX_op_shl_i32:
case INDEX_op_shr_i32:
case INDEX_op_sar_i32:
- return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);
-
- case INDEX_op_shl_i64:
- case INDEX_op_shr_i64:
- case INDEX_op_sar_i64:
- return &r_r_ri;
-
- case INDEX_op_rotl_i32:
- case INDEX_op_rotl_i64:
- case INDEX_op_rotr_i32:
- case INDEX_op_rotr_i64:
- return &r_r_ri;
+ return (s390_facilities & FACILITY_DISTINCT_OPS
+ ? C_O1_I2(r, r, ri)
+ : C_O1_I2(r, 0, ri));
case INDEX_op_brcond_i32:
case INDEX_op_brcond_i64:
- return &r_ri;
+ return C_O0_I2(r, ri);
case INDEX_op_bswap16_i32:
case INDEX_op_bswap16_i64:
@@ -2417,58 +2415,45 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_extu_i32_i64:
case INDEX_op_extract_i32:
case INDEX_op_extract_i64:
- return &r_r;
-
- case INDEX_op_clz_i64:
- case INDEX_op_setcond_i32:
- case INDEX_op_setcond_i64:
- return &r_r_ri;
+ return C_O1_I1(r, r);
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
- return &r_L;
+ return C_O1_I1(r, L);
case INDEX_op_qemu_st_i64:
case INDEX_op_qemu_st_i32:
- return &L_L;
+ return C_O0_I2(L, L);
case INDEX_op_deposit_i32:
case INDEX_op_deposit_i64:
- {
- static const TCGTargetOpDef dep
- = { .args_ct_str = { "r", "rZ", "r" } };
- return &dep;
- }
+ return C_O1_I2(r, rZ, r);
+
case INDEX_op_movcond_i32:
case INDEX_op_movcond_i64:
- {
- static const TCGTargetOpDef movc
- = { .args_ct_str = { "r", "r", "ri", "r", "0" } };
- static const TCGTargetOpDef movc_l
- = { .args_ct_str = { "r", "r", "ri", "rI", "0" } };
- return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);
- }
+ return (s390_facilities & FACILITY_LOAD_ON_COND2
+ ? C_O1_I4(r, r, ri, rI, 0)
+ : C_O1_I4(r, r, ri, r, 0));
+
case INDEX_op_div2_i32:
case INDEX_op_div2_i64:
case INDEX_op_divu2_i32:
case INDEX_op_divu2_i64:
- {
- static const TCGTargetOpDef div2
- = { .args_ct_str = { "b", "a", "0", "1", "r" } };
- return &div2;
- }
+ return C_O2_I3(b, a, 0, 1, r);
+
case INDEX_op_mulu2_i64:
- {
- static const TCGTargetOpDef mul2
- = { .args_ct_str = { "b", "a", "0", "r" } };
- return &mul2;
- }
+ return C_O2_I2(b, a, 0, r);
case INDEX_op_add2_i32:
case INDEX_op_sub2_i32:
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_ri : &a2_r);
+ return (s390_facilities & FACILITY_EXT_IMM
+ ? C_O2_I4(r, r, 0, 1, ri, r)
+ : C_O2_I4(r, r, 0, 1, r, r));
+
case INDEX_op_add2_i64:
case INDEX_op_sub2_i64:
- return (s390_facilities & FACILITY_EXT_IMM ? &a2_rA : &a2_r);
+ return (s390_facilities & FACILITY_EXT_IMM
+ ? C_O2_I4(r, r, 0, 1, rA, r)
+ : C_O2_I4(r, r, 0, 1, r, r));
default:
break;
--
2.25.1
next prev parent reply other threads:[~2020-09-09 0:31 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
2020-09-09 0:16 ` [PATCH 01/43] tcg: Adjust simd_desc size encoding Richard Henderson
2020-09-09 0:16 ` [PATCH 02/43] tcg: Drop union from TCGArgConstraint Richard Henderson
2020-09-09 17:43 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 03/43] tcg: Move sorted_args into TCGArgConstraint.sort_index Richard Henderson
2020-09-09 0:16 ` [PATCH 04/43] tcg: Remove TCG_CT_REG Richard Henderson
2020-09-09 0:16 ` [PATCH 05/43] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields Richard Henderson
2020-09-09 0:16 ` [PATCH 06/43] tcg: Remove TCGOpDef.used Richard Henderson
2020-09-09 17:45 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 07/43] tcg/i386: Fix dupi for avx2 32-bit hosts Richard Henderson
2020-09-09 0:16 ` [PATCH 08/43] tcg: Fix generation of dupi_vec for 32-bit host Richard Henderson
2020-09-09 0:16 ` [PATCH 09/43] tcg/optimize: Fold dup2_vec Richard Henderson
2020-09-09 0:16 ` [PATCH 10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec Richard Henderson
2020-09-09 17:47 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 11/43] tcg: Use tcg_out_dupi_vec from temp_load Richard Henderson
2020-09-09 0:16 ` [PATCH 12/43] tcg: Increase tcg_out_dupi_vec immediate to int64_t Richard Henderson
2020-09-09 0:16 ` [PATCH 13/43] tcg: Consolidate 3 bits into enum TCGTempKind Richard Henderson
2020-09-09 17:52 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 14/43] tcg: Add temp_readonly Richard Henderson
2020-09-09 0:16 ` [PATCH 15/43] tcg: Expand TCGTemp.val to 64-bits Richard Henderson
2020-09-09 0:16 ` [PATCH 16/43] tcg: Rename struct tcg_temp_info to TempOptInfo Richard Henderson
2020-09-09 0:16 ` [PATCH 17/43] tcg: Expand TempOptInfo to 64-bits Richard Henderson
2020-09-09 0:16 ` [PATCH 18/43] tcg: Introduce TYPE_CONST temporaries Richard Henderson
2020-09-09 0:16 ` [PATCH 19/43] tcg/optimize: Improve find_better_copy Richard Henderson
2020-09-09 0:16 ` [PATCH 20/43] tcg/optimize: Adjust TempOptInfo allocation Richard Henderson
2020-09-09 0:16 ` [PATCH 21/43] tcg/optimize: Use tcg_constant_internal with constant folding Richard Henderson
2020-09-09 0:16 ` [PATCH 22/43] tcg: Convert tcg_gen_dupi_vec to TCG_CONST Richard Henderson
2020-09-09 0:16 ` [PATCH 23/43] tcg: Use tcg_constant_i32 with icount expander Richard Henderson
2020-09-09 0:16 ` [PATCH 24/43] tcg: Use tcg_constant_{i32,i64} with tcg int expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 25/43] tcg: Use tcg_constant_{i32,i64} with tcg plugins Richard Henderson
2020-09-09 0:16 ` [PATCH 26/43] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 27/43] tcg/tci: Add special tci_movi_{i32,i64} opcodes Richard Henderson
2020-09-09 0:16 ` [PATCH 28/43] tcg: Remove movi and dupi opcodes Richard Henderson
2020-09-09 0:16 ` [PATCH 29/43] tcg: Add tcg_reg_alloc_dup2 Richard Henderson
2020-09-09 0:16 ` [PATCH 30/43] tcg/i386: Use tcg_constant_vec with tcg vec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 31/43] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec Richard Henderson
2020-09-09 0:16 ` [PATCH 32/43] tcg/ppc: Use tcg_constant_vec with tcg vec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 33/43] tcg/aarch64: " Richard Henderson
2020-09-09 0:16 ` [PATCH 34/43] tcg: Add tcg-constr.c.inc Richard Henderson
2020-09-09 0:16 ` [PATCH 35/43] tcg/i386: Convert to tcg-constr.c.inc Richard Henderson
2020-09-09 0:16 ` [PATCH 36/43] tcg/aarch64: " Richard Henderson
2020-09-09 0:16 ` [PATCH 37/43] tcg/arm: " Richard Henderson
2020-09-09 0:16 ` [PATCH 38/43] tcg/mips: " Richard Henderson
2020-09-09 0:16 ` [PATCH 39/43] tcg/ppc: " Richard Henderson
2020-09-09 0:16 ` [PATCH 40/43] tcg/riscv: " Richard Henderson
2020-09-09 0:16 ` Richard Henderson [this message]
2020-09-09 0:16 ` [PATCH 42/43] tcg/sparc: " Richard Henderson
2020-09-09 0:16 ` [PATCH 43/43] tcg/tci: " Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200909001647.532249-42-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).