From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH 05/43] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields
Date: Tue, 8 Sep 2020 17:16:09 -0700 [thread overview]
Message-ID: <20200909001647.532249-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200909001647.532249-1-richard.henderson@linaro.org>
These are easier to set and test when they have their own fields.
Reduce the size of alias_index and sort_index to 4 bits, which is
sufficient for TCG_MAX_OP_ARGS. This leaves only the bits indicating
constants within the ct field.
Move all initialization to allocation time, rather than init
individual fields in process_op_defs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 14 +++++++-------
tcg/tcg.c | 28 ++++++++++++----------------
2 files changed, 19 insertions(+), 23 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 3168315bb8..e8629b58c8 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -976,15 +976,15 @@ int64_t tcg_cpu_exec_time(void);
void tcg_dump_info(void);
void tcg_dump_op_count(void);
-#define TCG_CT_ALIAS 0x80
-#define TCG_CT_IALIAS 0x40
-#define TCG_CT_NEWREG 0x20 /* output requires a new register */
-#define TCG_CT_CONST 0x02 /* any constant of register size */
+#define TCG_CT_CONST 1 /* any constant of register size */
typedef struct TCGArgConstraint {
- uint16_t ct;
- uint8_t alias_index;
- uint8_t sort_index;
+ unsigned ct : 16;
+ unsigned alias_index : 4;
+ unsigned sort_index : 4;
+ bool oalias : 1;
+ bool ialias : 1;
+ bool newreg : 1;
TCGRegSet regs;
} TCGArgConstraint;
diff --git a/tcg/tcg.c b/tcg/tcg.c
index a618497c94..ad4b7fb90f 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -958,7 +958,7 @@ void tcg_context_init(TCGContext *s)
total_args += n;
}
- args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
+ args_ct = g_new0(TCGArgConstraint, total_args);
for(op = 0; op < NB_OPS; op++) {
def = &tcg_op_defs[op];
@@ -2197,7 +2197,7 @@ static int get_constraint_priority(const TCGOpDef *def, int k)
const TCGArgConstraint *arg_ct = &def->args_ct[k];
int n;
- if (arg_ct->ct & TCG_CT_ALIAS) {
+ if (arg_ct->oalias) {
/* an alias is equivalent to a single register */
n = 1;
} else {
@@ -2260,8 +2260,6 @@ static void process_op_defs(TCGContext *s)
/* Incomplete TCGTargetOpDef entry. */
tcg_debug_assert(ct_str != NULL);
- def->args_ct[i].regs = 0;
- def->args_ct[i].ct = 0;
while (*ct_str != '\0') {
switch(*ct_str) {
case '0' ... '9':
@@ -2270,18 +2268,18 @@ static void process_op_defs(TCGContext *s)
tcg_debug_assert(ct_str == tdefs->args_ct_str[i]);
tcg_debug_assert(oarg < def->nb_oargs);
tcg_debug_assert(def->args_ct[oarg].regs != 0);
- /* TCG_CT_ALIAS is for the output arguments.
- The input is tagged with TCG_CT_IALIAS. */
def->args_ct[i] = def->args_ct[oarg];
- def->args_ct[oarg].ct |= TCG_CT_ALIAS;
+ /* The output sets oalias. */
+ def->args_ct[oarg].oalias = true;
def->args_ct[oarg].alias_index = i;
- def->args_ct[i].ct |= TCG_CT_IALIAS;
+ /* The input sets ialias. */
+ def->args_ct[i].ialias = true;
def->args_ct[i].alias_index = oarg;
}
ct_str++;
break;
case '&':
- def->args_ct[i].ct |= TCG_CT_NEWREG;
+ def->args_ct[i].newreg = true;
ct_str++;
break;
case 'i':
@@ -2848,7 +2846,7 @@ static void liveness_pass_1(TCGContext *s)
set = *pset;
set &= ct->regs;
- if (ct->ct & TCG_CT_IALIAS) {
+ if (ct->ialias) {
set &= op->output_pref[ct->alias_index];
}
/* If the combination is not possible, restart. */
@@ -3665,7 +3663,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
}
i_preferred_regs = o_preferred_regs = 0;
- if (arg_ct->ct & TCG_CT_IALIAS) {
+ if (arg_ct->ialias) {
o_preferred_regs = op->output_pref[arg_ct->alias_index];
if (ts->fixed_reg) {
/* if fixed register, we must allocate a new register
@@ -3688,8 +3686,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
reg = ts->reg;
for (k2 = 0 ; k2 < k ; k2++) {
i2 = def->args_ct[nb_oargs + k2].sort_index;
- if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
- reg == new_args[i2]) {
+ if (def->args_ct[i2].ialias && reg == new_args[i2]) {
goto allocate_in_reg;
}
}
@@ -3760,10 +3757,9 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
/* ENV should not be modified. */
tcg_debug_assert(!ts->fixed_reg);
- if ((arg_ct->ct & TCG_CT_ALIAS)
- && !const_args[arg_ct->alias_index]) {
+ if (arg_ct->oalias && !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index];
- } else if (arg_ct->ct & TCG_CT_NEWREG) {
+ } else if (arg_ct->newreg) {
reg = tcg_reg_alloc(s, arg_ct->regs,
i_allocated_regs | o_allocated_regs,
op->output_pref[k], ts->indirect_base);
--
2.25.1
next prev parent reply other threads:[~2020-09-09 0:19 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-09 0:16 [PATCH 00/43] tcg patch queue Richard Henderson
2020-09-09 0:16 ` [PATCH 01/43] tcg: Adjust simd_desc size encoding Richard Henderson
2020-09-09 0:16 ` [PATCH 02/43] tcg: Drop union from TCGArgConstraint Richard Henderson
2020-09-09 17:43 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 03/43] tcg: Move sorted_args into TCGArgConstraint.sort_index Richard Henderson
2020-09-09 0:16 ` [PATCH 04/43] tcg: Remove TCG_CT_REG Richard Henderson
2020-09-09 0:16 ` Richard Henderson [this message]
2020-09-09 0:16 ` [PATCH 06/43] tcg: Remove TCGOpDef.used Richard Henderson
2020-09-09 17:45 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 07/43] tcg/i386: Fix dupi for avx2 32-bit hosts Richard Henderson
2020-09-09 0:16 ` [PATCH 08/43] tcg: Fix generation of dupi_vec for 32-bit host Richard Henderson
2020-09-09 0:16 ` [PATCH 09/43] tcg/optimize: Fold dup2_vec Richard Henderson
2020-09-09 0:16 ` [PATCH 10/43] tcg: Remove TCG_TARGET_HAS_cmp_vec Richard Henderson
2020-09-09 17:47 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 11/43] tcg: Use tcg_out_dupi_vec from temp_load Richard Henderson
2020-09-09 0:16 ` [PATCH 12/43] tcg: Increase tcg_out_dupi_vec immediate to int64_t Richard Henderson
2020-09-09 0:16 ` [PATCH 13/43] tcg: Consolidate 3 bits into enum TCGTempKind Richard Henderson
2020-09-09 17:52 ` Philippe Mathieu-Daudé
2020-09-09 0:16 ` [PATCH 14/43] tcg: Add temp_readonly Richard Henderson
2020-09-09 0:16 ` [PATCH 15/43] tcg: Expand TCGTemp.val to 64-bits Richard Henderson
2020-09-09 0:16 ` [PATCH 16/43] tcg: Rename struct tcg_temp_info to TempOptInfo Richard Henderson
2020-09-09 0:16 ` [PATCH 17/43] tcg: Expand TempOptInfo to 64-bits Richard Henderson
2020-09-09 0:16 ` [PATCH 18/43] tcg: Introduce TYPE_CONST temporaries Richard Henderson
2020-09-09 0:16 ` [PATCH 19/43] tcg/optimize: Improve find_better_copy Richard Henderson
2020-09-09 0:16 ` [PATCH 20/43] tcg/optimize: Adjust TempOptInfo allocation Richard Henderson
2020-09-09 0:16 ` [PATCH 21/43] tcg/optimize: Use tcg_constant_internal with constant folding Richard Henderson
2020-09-09 0:16 ` [PATCH 22/43] tcg: Convert tcg_gen_dupi_vec to TCG_CONST Richard Henderson
2020-09-09 0:16 ` [PATCH 23/43] tcg: Use tcg_constant_i32 with icount expander Richard Henderson
2020-09-09 0:16 ` [PATCH 24/43] tcg: Use tcg_constant_{i32,i64} with tcg int expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 25/43] tcg: Use tcg_constant_{i32,i64} with tcg plugins Richard Henderson
2020-09-09 0:16 ` [PATCH 26/43] tcg: Use tcg_constant_{i32, i64, vec} with gvec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 27/43] tcg/tci: Add special tci_movi_{i32,i64} opcodes Richard Henderson
2020-09-09 0:16 ` [PATCH 28/43] tcg: Remove movi and dupi opcodes Richard Henderson
2020-09-09 0:16 ` [PATCH 29/43] tcg: Add tcg_reg_alloc_dup2 Richard Henderson
2020-09-09 0:16 ` [PATCH 30/43] tcg/i386: Use tcg_constant_vec with tcg vec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 31/43] tcg: Remove tcg_gen_dup{8,16,32,64}i_vec Richard Henderson
2020-09-09 0:16 ` [PATCH 32/43] tcg/ppc: Use tcg_constant_vec with tcg vec expanders Richard Henderson
2020-09-09 0:16 ` [PATCH 33/43] tcg/aarch64: " Richard Henderson
2020-09-09 0:16 ` [PATCH 34/43] tcg: Add tcg-constr.c.inc Richard Henderson
2020-09-09 0:16 ` [PATCH 35/43] tcg/i386: Convert to tcg-constr.c.inc Richard Henderson
2020-09-09 0:16 ` [PATCH 36/43] tcg/aarch64: " Richard Henderson
2020-09-09 0:16 ` [PATCH 37/43] tcg/arm: " Richard Henderson
2020-09-09 0:16 ` [PATCH 38/43] tcg/mips: " Richard Henderson
2020-09-09 0:16 ` [PATCH 39/43] tcg/ppc: " Richard Henderson
2020-09-09 0:16 ` [PATCH 40/43] tcg/riscv: " Richard Henderson
2020-09-09 0:16 ` [PATCH 41/43] tcg/s390: " Richard Henderson
2020-09-09 0:16 ` [PATCH 42/43] tcg/sparc: " Richard Henderson
2020-09-09 0:16 ` [PATCH 43/43] tcg/tci: " Richard Henderson
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