* [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices
2020-09-10 7:01 [PATCH 0/6] misc: Some inclusive terminology changes Philippe Mathieu-Daudé
@ 2020-09-10 7:01 ` Philippe Mathieu-Daudé
2020-09-10 7:03 ` Thomas Huth
` (2 more replies)
2020-09-10 7:01 ` [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink Philippe Mathieu-Daudé
` (6 subsequent siblings)
7 siblings, 3 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-10 7:01 UTC (permalink / raw)
To: qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Philippe Mathieu-Daudé, Jason Wang, Marcelo Tosatti,
Joel Stanley, qemu-trivial, qemu-arm, Cédric Le Goater,
Paolo Bonzini, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
In order to use inclusive terminology, rename max_slaves
as max_devices.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
include/hw/ssi/aspeed_smc.h | 2 +-
hw/ssi/aspeed_smc.c | 40 ++++++++++++++++++-------------------
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
index 6fbbb238f15..52ae34e38d1 100644
--- a/include/hw/ssi/aspeed_smc.h
+++ b/include/hw/ssi/aspeed_smc.h
@@ -42,7 +42,7 @@ typedef struct AspeedSMCController {
uint8_t r_timings;
uint8_t nregs_timings;
uint8_t conf_enable_w0;
- uint8_t max_slaves;
+ uint8_t max_devices;
const AspeedSegments *segments;
hwaddr flash_window_base;
uint32_t flash_window_size;
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 795784e5f36..8219272016c 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -259,7 +259,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
- .max_slaves = 1,
+ .max_devices = 1,
.segments = aspeed_segments_legacy,
.flash_window_base = ASPEED_SOC_SMC_FLASH_BASE,
.flash_window_size = 0x6000000,
@@ -275,7 +275,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
- .max_slaves = 5,
+ .max_devices = 5,
.segments = aspeed_segments_fmc,
.flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
.flash_window_size = 0x10000000,
@@ -293,7 +293,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_SPI_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = SPI_CONF_ENABLE_W0,
- .max_slaves = 1,
+ .max_devices = 1,
.segments = aspeed_segments_spi,
.flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
.flash_window_size = 0x10000000,
@@ -309,7 +309,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
- .max_slaves = 3,
+ .max_devices = 3,
.segments = aspeed_segments_ast2500_fmc,
.flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
.flash_window_size = 0x10000000,
@@ -327,7 +327,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
- .max_slaves = 2,
+ .max_devices = 2,
.segments = aspeed_segments_ast2500_spi1,
.flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
.flash_window_size = 0x8000000,
@@ -343,7 +343,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
- .max_slaves = 2,
+ .max_devices = 2,
.segments = aspeed_segments_ast2500_spi2,
.flash_window_base = ASPEED_SOC_SPI2_FLASH_BASE,
.flash_window_size = 0x8000000,
@@ -359,7 +359,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 1,
.conf_enable_w0 = CONF_ENABLE_W0,
- .max_slaves = 3,
+ .max_devices = 3,
.segments = aspeed_segments_ast2600_fmc,
.flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE,
.flash_window_size = 0x10000000,
@@ -377,7 +377,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 2,
.conf_enable_w0 = CONF_ENABLE_W0,
- .max_slaves = 2,
+ .max_devices = 2,
.segments = aspeed_segments_ast2600_spi1,
.flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE,
.flash_window_size = 0x10000000,
@@ -395,7 +395,7 @@ static const AspeedSMCController controllers[] = {
.r_timings = R_TIMINGS,
.nregs_timings = 3,
.conf_enable_w0 = CONF_ENABLE_W0,
- .max_slaves = 3,
+ .max_devices = 3,
.segments = aspeed_segments_ast2600_spi2,
.flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE,
.flash_window_size = 0x10000000,
@@ -476,7 +476,7 @@ static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
AspeedSegments seg;
int i;
- for (i = 0; i < s->ctrl->max_slaves; i++) {
+ for (i = 0; i < s->ctrl->max_devices; i++) {
if (i == cs) {
continue;
}
@@ -537,7 +537,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
*/
if ((s->ctrl->segments == aspeed_segments_ast2500_spi1 ||
s->ctrl->segments == aspeed_segments_ast2500_spi2) &&
- cs == s->ctrl->max_slaves &&
+ cs == s->ctrl->max_devices &&
seg.addr + seg.size != s->ctrl->segments[cs].addr +
s->ctrl->segments[cs].size) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -948,7 +948,7 @@ static void aspeed_smc_reset(DeviceState *d)
}
/* setup the default segment register values and regions for all */
- for (i = 0; i < s->ctrl->max_slaves; ++i) {
+ for (i = 0; i < s->ctrl->max_devices; ++i) {
aspeed_smc_flash_set_segment_region(s, i,
s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]));
}
@@ -995,8 +995,8 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
(s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) ||
(s->ctrl->has_dma && addr == R_DMA_LEN) ||
(s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
- (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
- (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
+ (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_devices) ||
+ (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_devices)) {
trace_aspeed_smc_read(addr, size, s->regs[addr]);
@@ -1270,7 +1270,7 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
int cs = addr - s->r_ctrl0;
aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
} else if (addr >= R_SEG_ADDR0 &&
- addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
+ addr < R_SEG_ADDR0 + s->ctrl->max_devices) {
int cs = addr - R_SEG_ADDR0;
if (value != s->regs[R_SEG_ADDR0 + cs]) {
@@ -1341,10 +1341,10 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
s->conf_enable_w0 = s->ctrl->conf_enable_w0;
/* Enforce some real HW limits */
- if (s->num_cs > s->ctrl->max_slaves) {
+ if (s->num_cs > s->ctrl->max_devices) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n",
- __func__, s->ctrl->max_slaves);
- s->num_cs = s->ctrl->max_slaves;
+ __func__, s->ctrl->max_devices);
+ s->num_cs = s->ctrl->max_devices;
}
/* DMA irq. Keep it first for the initialization in the SoC */
@@ -1376,7 +1376,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
s->ctrl->flash_window_size);
sysbus_init_mmio(sbd, &s->mmio_flash);
- s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_slaves);
+ s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_devices);
/*
* Let's create a sub memory region for each possible slave. All
@@ -1385,7 +1385,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
* module behind to handle the memory accesses. This depends on
* the board configuration.
*/
- for (i = 0; i < s->ctrl->max_slaves; ++i) {
+ for (i = 0; i < s->ctrl->max_devices; ++i) {
AspeedSMCFlash *fl = &s->flashes[i];
snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i);
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices
2020-09-10 7:01 ` [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices Philippe Mathieu-Daudé
@ 2020-09-10 7:03 ` Thomas Huth
2020-09-10 9:08 ` Paolo Bonzini
2020-09-10 19:25 ` Cédric Le Goater
2 siblings, 0 replies; 27+ messages in thread
From: Thomas Huth @ 2020-09-10 7:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Alistair Francis, Eduardo Habkost,
kvm, Michael S. Tsirkin, Andrew Jeffery, Jason Wang,
Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Paolo Bonzini, Edgar E. Iglesias,
Alex Bennée, Richard Henderson
On 10/09/2020 09.01, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename max_slaves
> as max_devices.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> include/hw/ssi/aspeed_smc.h | 2 +-
> hw/ssi/aspeed_smc.c | 40 ++++++++++++++++++-------------------
> 2 files changed, 21 insertions(+), 21 deletions(-)
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices
2020-09-10 7:01 ` [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices Philippe Mathieu-Daudé
2020-09-10 7:03 ` Thomas Huth
@ 2020-09-10 9:08 ` Paolo Bonzini
2020-09-10 19:25 ` Cédric Le Goater
2 siblings, 0 replies; 27+ messages in thread
From: Paolo Bonzini @ 2020-09-10 9:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Jason Wang, Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename max_slaves
> as max_devices.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
I think we should consider a wholesale replacement of SSISlave with
SSIPeripheral according to the proposal at
https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/.
Paolo
> ---
> include/hw/ssi/aspeed_smc.h | 2 +-
> hw/ssi/aspeed_smc.c | 40 ++++++++++++++++++-------------------
> 2 files changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
> index 6fbbb238f15..52ae34e38d1 100644
> --- a/include/hw/ssi/aspeed_smc.h
> +++ b/include/hw/ssi/aspeed_smc.h
> @@ -42,7 +42,7 @@ typedef struct AspeedSMCController {
> uint8_t r_timings;
> uint8_t nregs_timings;
> uint8_t conf_enable_w0;
> - uint8_t max_slaves;
> + uint8_t max_devices;
> const AspeedSegments *segments;
> hwaddr flash_window_base;
> uint32_t flash_window_size;
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index 795784e5f36..8219272016c 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -259,7 +259,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 1,
> + .max_devices = 1,
> .segments = aspeed_segments_legacy,
> .flash_window_base = ASPEED_SOC_SMC_FLASH_BASE,
> .flash_window_size = 0x6000000,
> @@ -275,7 +275,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 5,
> + .max_devices = 5,
> .segments = aspeed_segments_fmc,
> .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -293,7 +293,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_SPI_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = SPI_CONF_ENABLE_W0,
> - .max_slaves = 1,
> + .max_devices = 1,
> .segments = aspeed_segments_spi,
> .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -309,7 +309,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 3,
> + .max_devices = 3,
> .segments = aspeed_segments_ast2500_fmc,
> .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -327,7 +327,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 2,
> + .max_devices = 2,
> .segments = aspeed_segments_ast2500_spi1,
> .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
> .flash_window_size = 0x8000000,
> @@ -343,7 +343,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 2,
> + .max_devices = 2,
> .segments = aspeed_segments_ast2500_spi2,
> .flash_window_base = ASPEED_SOC_SPI2_FLASH_BASE,
> .flash_window_size = 0x8000000,
> @@ -359,7 +359,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 3,
> + .max_devices = 3,
> .segments = aspeed_segments_ast2600_fmc,
> .flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -377,7 +377,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 2,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 2,
> + .max_devices = 2,
> .segments = aspeed_segments_ast2600_spi1,
> .flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -395,7 +395,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 3,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 3,
> + .max_devices = 3,
> .segments = aspeed_segments_ast2600_spi2,
> .flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -476,7 +476,7 @@ static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
> AspeedSegments seg;
> int i;
>
> - for (i = 0; i < s->ctrl->max_slaves; i++) {
> + for (i = 0; i < s->ctrl->max_devices; i++) {
> if (i == cs) {
> continue;
> }
> @@ -537,7 +537,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
> */
> if ((s->ctrl->segments == aspeed_segments_ast2500_spi1 ||
> s->ctrl->segments == aspeed_segments_ast2500_spi2) &&
> - cs == s->ctrl->max_slaves &&
> + cs == s->ctrl->max_devices &&
> seg.addr + seg.size != s->ctrl->segments[cs].addr +
> s->ctrl->segments[cs].size) {
> qemu_log_mask(LOG_GUEST_ERROR,
> @@ -948,7 +948,7 @@ static void aspeed_smc_reset(DeviceState *d)
> }
>
> /* setup the default segment register values and regions for all */
> - for (i = 0; i < s->ctrl->max_slaves; ++i) {
> + for (i = 0; i < s->ctrl->max_devices; ++i) {
> aspeed_smc_flash_set_segment_region(s, i,
> s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]));
> }
> @@ -995,8 +995,8 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
> (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) ||
> (s->ctrl->has_dma && addr == R_DMA_LEN) ||
> (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
> - (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
> - (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
> + (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_devices) ||
> + (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_devices)) {
>
> trace_aspeed_smc_read(addr, size, s->regs[addr]);
>
> @@ -1270,7 +1270,7 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
> int cs = addr - s->r_ctrl0;
> aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
> } else if (addr >= R_SEG_ADDR0 &&
> - addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
> + addr < R_SEG_ADDR0 + s->ctrl->max_devices) {
> int cs = addr - R_SEG_ADDR0;
>
> if (value != s->regs[R_SEG_ADDR0 + cs]) {
> @@ -1341,10 +1341,10 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
> s->conf_enable_w0 = s->ctrl->conf_enable_w0;
>
> /* Enforce some real HW limits */
> - if (s->num_cs > s->ctrl->max_slaves) {
> + if (s->num_cs > s->ctrl->max_devices) {
> qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n",
> - __func__, s->ctrl->max_slaves);
> - s->num_cs = s->ctrl->max_slaves;
> + __func__, s->ctrl->max_devices);
> + s->num_cs = s->ctrl->max_devices;
> }
>
> /* DMA irq. Keep it first for the initialization in the SoC */
> @@ -1376,7 +1376,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
> s->ctrl->flash_window_size);
> sysbus_init_mmio(sbd, &s->mmio_flash);
>
> - s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_slaves);
> + s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_devices);
>
> /*
> * Let's create a sub memory region for each possible slave. All
> @@ -1385,7 +1385,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
> * module behind to handle the memory accesses. This depends on
> * the board configuration.
> */
> - for (i = 0; i < s->ctrl->max_slaves; ++i) {
> + for (i = 0; i < s->ctrl->max_devices; ++i) {
> AspeedSMCFlash *fl = &s->flashes[i];
>
> snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i);
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices
2020-09-10 7:01 ` [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices Philippe Mathieu-Daudé
2020-09-10 7:03 ` Thomas Huth
2020-09-10 9:08 ` Paolo Bonzini
@ 2020-09-10 19:25 ` Cédric Le Goater
2 siblings, 0 replies; 27+ messages in thread
From: Cédric Le Goater @ 2020-09-10 19:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Jason Wang, Marcelo Tosatti, qemu-trivial, qemu-arm, Joel Stanley,
Paolo Bonzini, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
On 9/10/20 9:01 AM, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename max_slaves
> as max_devices.>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
> ---
> include/hw/ssi/aspeed_smc.h | 2 +-
> hw/ssi/aspeed_smc.c | 40 ++++++++++++++++++-------------------
> 2 files changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h
> index 6fbbb238f15..52ae34e38d1 100644
> --- a/include/hw/ssi/aspeed_smc.h
> +++ b/include/hw/ssi/aspeed_smc.h
> @@ -42,7 +42,7 @@ typedef struct AspeedSMCController {
> uint8_t r_timings;
> uint8_t nregs_timings;
> uint8_t conf_enable_w0;
> - uint8_t max_slaves;
> + uint8_t max_devices;
> const AspeedSegments *segments;
> hwaddr flash_window_base;
> uint32_t flash_window_size;
> diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
> index 795784e5f36..8219272016c 100644
> --- a/hw/ssi/aspeed_smc.c
> +++ b/hw/ssi/aspeed_smc.c
> @@ -259,7 +259,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 1,
> + .max_devices = 1,
> .segments = aspeed_segments_legacy,
> .flash_window_base = ASPEED_SOC_SMC_FLASH_BASE,
> .flash_window_size = 0x6000000,
> @@ -275,7 +275,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 5,
> + .max_devices = 5,
> .segments = aspeed_segments_fmc,
> .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -293,7 +293,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_SPI_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = SPI_CONF_ENABLE_W0,
> - .max_slaves = 1,
> + .max_devices = 1,
> .segments = aspeed_segments_spi,
> .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -309,7 +309,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 3,
> + .max_devices = 3,
> .segments = aspeed_segments_ast2500_fmc,
> .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -327,7 +327,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 2,
> + .max_devices = 2,
> .segments = aspeed_segments_ast2500_spi1,
> .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE,
> .flash_window_size = 0x8000000,
> @@ -343,7 +343,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 2,
> + .max_devices = 2,
> .segments = aspeed_segments_ast2500_spi2,
> .flash_window_base = ASPEED_SOC_SPI2_FLASH_BASE,
> .flash_window_size = 0x8000000,
> @@ -359,7 +359,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 1,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 3,
> + .max_devices = 3,
> .segments = aspeed_segments_ast2600_fmc,
> .flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -377,7 +377,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 2,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 2,
> + .max_devices = 2,
> .segments = aspeed_segments_ast2600_spi1,
> .flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -395,7 +395,7 @@ static const AspeedSMCController controllers[] = {
> .r_timings = R_TIMINGS,
> .nregs_timings = 3,
> .conf_enable_w0 = CONF_ENABLE_W0,
> - .max_slaves = 3,
> + .max_devices = 3,
> .segments = aspeed_segments_ast2600_spi2,
> .flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE,
> .flash_window_size = 0x10000000,
> @@ -476,7 +476,7 @@ static bool aspeed_smc_flash_overlap(const AspeedSMCState *s,
> AspeedSegments seg;
> int i;
>
> - for (i = 0; i < s->ctrl->max_slaves; i++) {
> + for (i = 0; i < s->ctrl->max_devices; i++) {
> if (i == cs) {
> continue;
> }
> @@ -537,7 +537,7 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs,
> */
> if ((s->ctrl->segments == aspeed_segments_ast2500_spi1 ||
> s->ctrl->segments == aspeed_segments_ast2500_spi2) &&
> - cs == s->ctrl->max_slaves &&
> + cs == s->ctrl->max_devices &&
> seg.addr + seg.size != s->ctrl->segments[cs].addr +
> s->ctrl->segments[cs].size) {
> qemu_log_mask(LOG_GUEST_ERROR,
> @@ -948,7 +948,7 @@ static void aspeed_smc_reset(DeviceState *d)
> }
>
> /* setup the default segment register values and regions for all */
> - for (i = 0; i < s->ctrl->max_slaves; ++i) {
> + for (i = 0; i < s->ctrl->max_devices; ++i) {
> aspeed_smc_flash_set_segment_region(s, i,
> s->ctrl->segment_to_reg(s, &s->ctrl->segments[i]));
> }
> @@ -995,8 +995,8 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size)
> (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) ||
> (s->ctrl->has_dma && addr == R_DMA_LEN) ||
> (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) ||
> - (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) ||
> - (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) {
> + (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_devices) ||
> + (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_devices)) {
>
> trace_aspeed_smc_read(addr, size, s->regs[addr]);
>
> @@ -1270,7 +1270,7 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data,
> int cs = addr - s->r_ctrl0;
> aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
> } else if (addr >= R_SEG_ADDR0 &&
> - addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
> + addr < R_SEG_ADDR0 + s->ctrl->max_devices) {
> int cs = addr - R_SEG_ADDR0;
>
> if (value != s->regs[R_SEG_ADDR0 + cs]) {
> @@ -1341,10 +1341,10 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
> s->conf_enable_w0 = s->ctrl->conf_enable_w0;
>
> /* Enforce some real HW limits */
> - if (s->num_cs > s->ctrl->max_slaves) {
> + if (s->num_cs > s->ctrl->max_devices) {
> qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n",
> - __func__, s->ctrl->max_slaves);
> - s->num_cs = s->ctrl->max_slaves;
> + __func__, s->ctrl->max_devices);
> + s->num_cs = s->ctrl->max_devices;
> }
>
> /* DMA irq. Keep it first for the initialization in the SoC */
> @@ -1376,7 +1376,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
> s->ctrl->flash_window_size);
> sysbus_init_mmio(sbd, &s->mmio_flash);
>
> - s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_slaves);
> + s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_devices);
>
> /*
> * Let's create a sub memory region for each possible slave. All
> @@ -1385,7 +1385,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp)
> * module behind to handle the memory accesses. This depends on
> * the board configuration.
> */
> - for (i = 0; i < s->ctrl->max_slaves; ++i) {
> + for (i = 0; i < s->ctrl->max_devices; ++i) {
> AspeedSMCFlash *fl = &s->flashes[i];
>
> snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i);
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink
2020-09-10 7:01 [PATCH 0/6] misc: Some inclusive terminology changes Philippe Mathieu-Daudé
2020-09-10 7:01 ` [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices Philippe Mathieu-Daudé
@ 2020-09-10 7:01 ` Philippe Mathieu-Daudé
2020-09-10 7:06 ` Philippe Mathieu-Daudé
2020-09-11 7:28 ` Paolo Bonzini
2020-09-10 7:01 ` [PATCH 3/6] hw/dma/xilinx_axidma: " Philippe Mathieu-Daudé
` (5 subsequent siblings)
7 siblings, 2 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-10 7:01 UTC (permalink / raw)
To: qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Philippe Mathieu-Daudé, Jason Wang, Marcelo Tosatti,
Joel Stanley, qemu-trivial, qemu-arm, Cédric Le Goater,
Paolo Bonzini, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
In order to use inclusive terminology, rename 'slave stream'
as 'sink stream'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
include/hw/ssi/xilinx_spips.h | 2 +-
include/hw/stream.h | 46 +++++++++++++++++------------------
hw/core/stream.c | 20 +++++++--------
hw/dma/xilinx_axidma.c | 32 ++++++++++++------------
hw/net/xilinx_axienet.c | 20 +++++++--------
hw/ssi/xilinx_spips.c | 2 +-
6 files changed, 61 insertions(+), 61 deletions(-)
diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
index 6a39b55a7bd..fde8a3ebda6 100644
--- a/include/hw/ssi/xilinx_spips.h
+++ b/include/hw/ssi/xilinx_spips.h
@@ -97,7 +97,7 @@ typedef struct {
typedef struct {
XilinxQSPIPS parent_obj;
- StreamSlave *dma;
+ StreamSink *dma;
int gqspi_irqline;
uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX];
diff --git a/include/hw/stream.h b/include/hw/stream.h
index ed09e83683d..8ca161991ca 100644
--- a/include/hw/stream.h
+++ b/include/hw/stream.h
@@ -3,52 +3,52 @@
#include "qom/object.h"
-/* stream slave. Used until qdev provides a generic way. */
-#define TYPE_STREAM_SLAVE "stream-slave"
+/* stream sink. Used until qdev provides a generic way. */
+#define TYPE_STREAM_SINK "stream-slave"
-#define STREAM_SLAVE_CLASS(klass) \
- OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE)
-#define STREAM_SLAVE_GET_CLASS(obj) \
- OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE)
-#define STREAM_SLAVE(obj) \
- INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE)
+#define STREAM_SINK_CLASS(klass) \
+ OBJECT_CLASS_CHECK(StreamSinkClass, (klass), TYPE_STREAM_SINK)
+#define STREAM_SINK_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(StreamSinkClass, (obj), TYPE_STREAM_SINK)
+#define STREAM_SINK(obj) \
+ INTERFACE_CHECK(StreamSink, (obj), TYPE_STREAM_SINK)
-typedef struct StreamSlave StreamSlave;
+typedef struct StreamSink StreamSink;
typedef void (*StreamCanPushNotifyFn)(void *opaque);
-typedef struct StreamSlaveClass {
+typedef struct StreamSinkClass {
InterfaceClass parent;
/**
- * can push - determine if a stream slave is capable of accepting at least
+ * can push - determine if a stream sink is capable of accepting at least
* one byte of data. Returns false if cannot accept. If not implemented, the
- * slave is assumed to always be capable of receiving.
- * @notify: Optional callback that the slave will call when the slave is
+ * sink is assumed to always be capable of receiving.
+ * @notify: Optional callback that the sink will call when the sink is
* capable of receiving again. Only called if false is returned.
* @notify_opaque: opaque data to pass to notify call.
*/
- bool (*can_push)(StreamSlave *obj, StreamCanPushNotifyFn notify,
+ bool (*can_push)(StreamSink *obj, StreamCanPushNotifyFn notify,
void *notify_opaque);
/**
- * push - push data to a Stream slave. The number of bytes pushed is
- * returned. If the slave short returns, the master must wait before trying
- * again, the slave may continue to just return 0 waiting for the vm time to
+ * push - push data to a Stream sink. The number of bytes pushed is
+ * returned. If the sink short returns, the master must wait before trying
+ * again, the sink may continue to just return 0 waiting for the vm time to
* advance. The can_push() function can be used to trap the point in time
- * where the slave is ready to receive again, otherwise polling on a QEMU
+ * where the sink is ready to receive again, otherwise polling on a QEMU
* timer will work.
- * @obj: Stream slave to push to
+ * @obj: Stream sink to push to
* @buf: Data to write
* @len: Maximum number of bytes to write
* @eop: End of packet flag
*/
- size_t (*push)(StreamSlave *obj, unsigned char *buf, size_t len, bool eop);
-} StreamSlaveClass;
+ size_t (*push)(StreamSink *obj, unsigned char *buf, size_t len, bool eop);
+} StreamSinkClass;
size_t
-stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop);
+stream_push(StreamSink *sink, uint8_t *buf, size_t len, bool eop);
bool
-stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify,
+stream_can_push(StreamSink *sink, StreamCanPushNotifyFn notify,
void *notify_opaque);
diff --git a/hw/core/stream.c b/hw/core/stream.c
index a65ad1208d8..19477d0f2df 100644
--- a/hw/core/stream.c
+++ b/hw/core/stream.c
@@ -3,32 +3,32 @@
#include "qemu/module.h"
size_t
-stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop)
+stream_push(StreamSink *sink, uint8_t *buf, size_t len, bool eop)
{
- StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
+ StreamSinkClass *k = STREAM_SINK_GET_CLASS(sink);
return k->push(sink, buf, len, eop);
}
bool
-stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify,
+stream_can_push(StreamSink *sink, StreamCanPushNotifyFn notify,
void *notify_opaque)
{
- StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
+ StreamSinkClass *k = STREAM_SINK_GET_CLASS(sink);
return k->can_push ? k->can_push(sink, notify, notify_opaque) : true;
}
-static const TypeInfo stream_slave_info = {
- .name = TYPE_STREAM_SLAVE,
+static const TypeInfo stream_sink_info = {
+ .name = TYPE_STREAM_SINK,
.parent = TYPE_INTERFACE,
- .class_size = sizeof(StreamSlaveClass),
+ .class_size = sizeof(StreamSinkClass),
};
-static void stream_slave_register_types(void)
+static void stream_sink_register_types(void)
{
- type_register_static(&stream_slave_info);
+ type_register_static(&stream_sink_info);
}
-type_init(stream_slave_register_types)
+type_init(stream_sink_register_types)
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
index a4812e480a0..cf12a852ea1 100644
--- a/hw/dma/xilinx_axidma.c
+++ b/hw/dma/xilinx_axidma.c
@@ -131,8 +131,8 @@ struct XilinxAXIDMA {
AddressSpace as;
uint32_t freqhz;
- StreamSlave *tx_data_dev;
- StreamSlave *tx_control_dev;
+ StreamSink *tx_data_dev;
+ StreamSink *tx_control_dev;
XilinxAXIDMAStreamSlave rx_data_dev;
XilinxAXIDMAStreamSlave rx_control_dev;
@@ -264,8 +264,8 @@ static void stream_complete(struct Stream *s)
ptimer_transaction_commit(s->ptimer);
}
-static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
- StreamSlave *tx_control_dev)
+static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
+ StreamSink *tx_control_dev)
{
uint32_t prev_d;
uint32_t txlen;
@@ -387,7 +387,7 @@ static void xilinx_axidma_reset(DeviceState *dev)
}
static size_t
-xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
+xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
size_t len, bool eop)
{
XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
@@ -403,7 +403,7 @@ xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
}
static bool
-xilinx_axidma_data_stream_can_push(StreamSlave *obj,
+xilinx_axidma_data_stream_can_push(StreamSink *obj,
StreamCanPushNotifyFn notify,
void *notify_opaque)
{
@@ -420,7 +420,7 @@ xilinx_axidma_data_stream_can_push(StreamSlave *obj,
}
static size_t
-xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len,
+xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
bool eop)
{
XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
@@ -591,9 +591,9 @@ static void xilinx_axidma_init(Object *obj)
static Property axidma_properties[] = {
DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA,
- tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
+ tx_data_dev, TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA,
- tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
+ tx_control_dev, TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_END_OF_LIST(),
};
@@ -606,21 +606,21 @@ static void axidma_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, axidma_properties);
}
-static StreamSlaveClass xilinx_axidma_data_stream_class = {
+static StreamSinkClass xilinx_axidma_data_stream_class = {
.push = xilinx_axidma_data_stream_push,
.can_push = xilinx_axidma_data_stream_can_push,
};
-static StreamSlaveClass xilinx_axidma_control_stream_class = {
+static StreamSinkClass xilinx_axidma_control_stream_class = {
.push = xilinx_axidma_control_stream_push,
};
static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data)
{
- StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
+ StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
- ssc->push = ((StreamSlaveClass *)data)->push;
- ssc->can_push = ((StreamSlaveClass *)data)->can_push;
+ ssc->push = ((StreamSinkClass *)data)->push;
+ ssc->can_push = ((StreamSinkClass *)data)->can_push;
}
static const TypeInfo axidma_info = {
@@ -638,7 +638,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
.class_init = xilinx_axidma_stream_class_init,
.class_data = &xilinx_axidma_data_stream_class,
.interfaces = (InterfaceInfo[]) {
- { TYPE_STREAM_SLAVE },
+ { TYPE_STREAM_SINK },
{ }
}
};
@@ -650,7 +650,7 @@ static const TypeInfo xilinx_axidma_control_stream_info = {
.class_init = xilinx_axidma_stream_class_init,
.class_data = &xilinx_axidma_control_stream_class,
.interfaces = (InterfaceInfo[]) {
- { TYPE_STREAM_SLAVE },
+ { TYPE_STREAM_SINK },
{ }
}
};
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 2e89f236b4a..0c4ac727207 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -323,8 +323,8 @@ struct XilinxAXIEnet {
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq irq;
- StreamSlave *tx_data_dev;
- StreamSlave *tx_control_dev;
+ StreamSink *tx_data_dev;
+ StreamSink *tx_control_dev;
XilinxAXIEnetStreamSlave rx_data_dev;
XilinxAXIEnetStreamSlave rx_control_dev;
NICState *nic;
@@ -855,7 +855,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
}
static size_t
-xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
+xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
bool eop)
{
int i;
@@ -877,7 +877,7 @@ xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
}
static size_t
-xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,
+xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
bool eop)
{
XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
@@ -1005,9 +1005,9 @@ static Property xilinx_enet_properties[] = {
DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet,
- tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
+ tx_data_dev, TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet,
- tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
+ tx_control_dev, TYPE_STREAM_SINK, StreamSink *),
DEFINE_PROP_END_OF_LIST(),
};
@@ -1023,14 +1023,14 @@ static void xilinx_enet_class_init(ObjectClass *klass, void *data)
static void xilinx_enet_control_stream_class_init(ObjectClass *klass,
void *data)
{
- StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
+ StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
ssc->push = xilinx_axienet_control_stream_push;
}
static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data)
{
- StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
+ StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
ssc->push = xilinx_axienet_data_stream_push;
}
@@ -1049,7 +1049,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
.instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
.class_init = xilinx_enet_data_stream_class_init,
.interfaces = (InterfaceInfo[]) {
- { TYPE_STREAM_SLAVE },
+ { TYPE_STREAM_SINK },
{ }
}
};
@@ -1060,7 +1060,7 @@ static const TypeInfo xilinx_enet_control_stream_info = {
.instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
.class_init = xilinx_enet_control_stream_class_init,
.interfaces = (InterfaceInfo[]) {
- { TYPE_STREAM_SLAVE },
+ { TYPE_STREAM_SINK },
{ }
}
};
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index b9371dbf8d7..6109ba55107 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -1353,7 +1353,7 @@ static void xlnx_zynqmp_qspips_init(Object *obj)
{
XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj);
- object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE,
+ object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK,
(Object **)&rq->dma,
object_property_allow_set_link,
OBJ_PROP_LINK_STRONG);
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink
2020-09-10 7:01 ` [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink Philippe Mathieu-Daudé
@ 2020-09-10 7:06 ` Philippe Mathieu-Daudé
2020-09-11 7:28 ` Paolo Bonzini
1 sibling, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-10 7:06 UTC (permalink / raw)
To: qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Jason Wang, Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Paolo Bonzini, Edgar E. Iglesias,
Alex Bennée, Richard Henderson
On 9/10/20 9:01 AM, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename 'slave stream'
> as 'sink stream'.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
[...]
> diff --git a/include/hw/stream.h b/include/hw/stream.h
> index ed09e83683d..8ca161991ca 100644
> --- a/include/hw/stream.h
> +++ b/include/hw/stream.h
> @@ -3,52 +3,52 @@
>
> #include "qom/object.h"
>
> -/* stream slave. Used until qdev provides a generic way. */
> -#define TYPE_STREAM_SLAVE "stream-slave"
> +/* stream sink. Used until qdev provides a generic way. */
> +#define TYPE_STREAM_SINK "stream-slave"
>
> -#define STREAM_SLAVE_CLASS(klass) \
> - OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE)
> -#define STREAM_SLAVE_GET_CLASS(obj) \
> - OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE)
> -#define STREAM_SLAVE(obj) \
> - INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE)
> +#define STREAM_SINK_CLASS(klass) \
> + OBJECT_CLASS_CHECK(StreamSinkClass, (klass), TYPE_STREAM_SINK)
> +#define STREAM_SINK_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(StreamSinkClass, (obj), TYPE_STREAM_SINK)
> +#define STREAM_SINK(obj) \
> + INTERFACE_CHECK(StreamSink, (obj), TYPE_STREAM_SINK)
Hmm being an interface, is it better to name it TYPE_SINK_STREAM?
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink
2020-09-10 7:01 ` [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink Philippe Mathieu-Daudé
2020-09-10 7:06 ` Philippe Mathieu-Daudé
@ 2020-09-11 7:28 ` Paolo Bonzini
2020-09-11 7:30 ` Edgar E. Iglesias
1 sibling, 1 reply; 27+ messages in thread
From: Paolo Bonzini @ 2020-09-11 7:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Jason Wang, Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename 'slave stream'
> as 'sink stream'.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
From Edgar Iglesias:
Regarding streams, our stream module can be used to model a stream
channel such as AXI stream but also other similar stream protocols. We
actually don't use the AXI stream terminology [in hw/core/stream.c].
E.g, we use buf instead of DATA, EOP (end-of-packet) instead of LAST and
have a flow-control mechanism that doesn't refer to valid/ready. IMO,
since we're not matching specific protocol names, it would be fine to
switch to generic terms like Source and Sink.
Therefore,
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo
> ---
> include/hw/ssi/xilinx_spips.h | 2 +-
> include/hw/stream.h | 46 +++++++++++++++++------------------
> hw/core/stream.c | 20 +++++++--------
> hw/dma/xilinx_axidma.c | 32 ++++++++++++------------
> hw/net/xilinx_axienet.c | 20 +++++++--------
> hw/ssi/xilinx_spips.c | 2 +-
> 6 files changed, 61 insertions(+), 61 deletions(-)
>
> diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
> index 6a39b55a7bd..fde8a3ebda6 100644
> --- a/include/hw/ssi/xilinx_spips.h
> +++ b/include/hw/ssi/xilinx_spips.h
> @@ -97,7 +97,7 @@ typedef struct {
> typedef struct {
> XilinxQSPIPS parent_obj;
>
> - StreamSlave *dma;
> + StreamSink *dma;
> int gqspi_irqline;
>
> uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX];
> diff --git a/include/hw/stream.h b/include/hw/stream.h
> index ed09e83683d..8ca161991ca 100644
> --- a/include/hw/stream.h
> +++ b/include/hw/stream.h
> @@ -3,52 +3,52 @@
>
> #include "qom/object.h"
>
> -/* stream slave. Used until qdev provides a generic way. */
> -#define TYPE_STREAM_SLAVE "stream-slave"
> +/* stream sink. Used until qdev provides a generic way. */
> +#define TYPE_STREAM_SINK "stream-slave"
>
> -#define STREAM_SLAVE_CLASS(klass) \
> - OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE)
> -#define STREAM_SLAVE_GET_CLASS(obj) \
> - OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE)
> -#define STREAM_SLAVE(obj) \
> - INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE)
> +#define STREAM_SINK_CLASS(klass) \
> + OBJECT_CLASS_CHECK(StreamSinkClass, (klass), TYPE_STREAM_SINK)
> +#define STREAM_SINK_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(StreamSinkClass, (obj), TYPE_STREAM_SINK)
> +#define STREAM_SINK(obj) \
> + INTERFACE_CHECK(StreamSink, (obj), TYPE_STREAM_SINK)
>
> -typedef struct StreamSlave StreamSlave;
> +typedef struct StreamSink StreamSink;
>
> typedef void (*StreamCanPushNotifyFn)(void *opaque);
>
> -typedef struct StreamSlaveClass {
> +typedef struct StreamSinkClass {
> InterfaceClass parent;
> /**
> - * can push - determine if a stream slave is capable of accepting at least
> + * can push - determine if a stream sink is capable of accepting at least
> * one byte of data. Returns false if cannot accept. If not implemented, the
> - * slave is assumed to always be capable of receiving.
> - * @notify: Optional callback that the slave will call when the slave is
> + * sink is assumed to always be capable of receiving.
> + * @notify: Optional callback that the sink will call when the sink is
> * capable of receiving again. Only called if false is returned.
> * @notify_opaque: opaque data to pass to notify call.
> */
> - bool (*can_push)(StreamSlave *obj, StreamCanPushNotifyFn notify,
> + bool (*can_push)(StreamSink *obj, StreamCanPushNotifyFn notify,
> void *notify_opaque);
> /**
> - * push - push data to a Stream slave. The number of bytes pushed is
> - * returned. If the slave short returns, the master must wait before trying
> - * again, the slave may continue to just return 0 waiting for the vm time to
> + * push - push data to a Stream sink. The number of bytes pushed is
> + * returned. If the sink short returns, the master must wait before trying
> + * again, the sink may continue to just return 0 waiting for the vm time to
> * advance. The can_push() function can be used to trap the point in time
> - * where the slave is ready to receive again, otherwise polling on a QEMU
> + * where the sink is ready to receive again, otherwise polling on a QEMU
> * timer will work.
> - * @obj: Stream slave to push to
> + * @obj: Stream sink to push to
> * @buf: Data to write
> * @len: Maximum number of bytes to write
> * @eop: End of packet flag
> */
> - size_t (*push)(StreamSlave *obj, unsigned char *buf, size_t len, bool eop);
> -} StreamSlaveClass;
> + size_t (*push)(StreamSink *obj, unsigned char *buf, size_t len, bool eop);
> +} StreamSinkClass;
>
> size_t
> -stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop);
> +stream_push(StreamSink *sink, uint8_t *buf, size_t len, bool eop);
>
> bool
> -stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify,
> +stream_can_push(StreamSink *sink, StreamCanPushNotifyFn notify,
> void *notify_opaque);
>
>
> diff --git a/hw/core/stream.c b/hw/core/stream.c
> index a65ad1208d8..19477d0f2df 100644
> --- a/hw/core/stream.c
> +++ b/hw/core/stream.c
> @@ -3,32 +3,32 @@
> #include "qemu/module.h"
>
> size_t
> -stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop)
> +stream_push(StreamSink *sink, uint8_t *buf, size_t len, bool eop)
> {
> - StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
> + StreamSinkClass *k = STREAM_SINK_GET_CLASS(sink);
>
> return k->push(sink, buf, len, eop);
> }
>
> bool
> -stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify,
> +stream_can_push(StreamSink *sink, StreamCanPushNotifyFn notify,
> void *notify_opaque)
> {
> - StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
> + StreamSinkClass *k = STREAM_SINK_GET_CLASS(sink);
>
> return k->can_push ? k->can_push(sink, notify, notify_opaque) : true;
> }
>
> -static const TypeInfo stream_slave_info = {
> - .name = TYPE_STREAM_SLAVE,
> +static const TypeInfo stream_sink_info = {
> + .name = TYPE_STREAM_SINK,
> .parent = TYPE_INTERFACE,
> - .class_size = sizeof(StreamSlaveClass),
> + .class_size = sizeof(StreamSinkClass),
> };
>
>
> -static void stream_slave_register_types(void)
> +static void stream_sink_register_types(void)
> {
> - type_register_static(&stream_slave_info);
> + type_register_static(&stream_sink_info);
> }
>
> -type_init(stream_slave_register_types)
> +type_init(stream_sink_register_types)
> diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
> index a4812e480a0..cf12a852ea1 100644
> --- a/hw/dma/xilinx_axidma.c
> +++ b/hw/dma/xilinx_axidma.c
> @@ -131,8 +131,8 @@ struct XilinxAXIDMA {
> AddressSpace as;
>
> uint32_t freqhz;
> - StreamSlave *tx_data_dev;
> - StreamSlave *tx_control_dev;
> + StreamSink *tx_data_dev;
> + StreamSink *tx_control_dev;
> XilinxAXIDMAStreamSlave rx_data_dev;
> XilinxAXIDMAStreamSlave rx_control_dev;
>
> @@ -264,8 +264,8 @@ static void stream_complete(struct Stream *s)
> ptimer_transaction_commit(s->ptimer);
> }
>
> -static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
> - StreamSlave *tx_control_dev)
> +static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
> + StreamSink *tx_control_dev)
> {
> uint32_t prev_d;
> uint32_t txlen;
> @@ -387,7 +387,7 @@ static void xilinx_axidma_reset(DeviceState *dev)
> }
>
> static size_t
> -xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
> +xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
> size_t len, bool eop)
> {
> XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
> @@ -403,7 +403,7 @@ xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
> }
>
> static bool
> -xilinx_axidma_data_stream_can_push(StreamSlave *obj,
> +xilinx_axidma_data_stream_can_push(StreamSink *obj,
> StreamCanPushNotifyFn notify,
> void *notify_opaque)
> {
> @@ -420,7 +420,7 @@ xilinx_axidma_data_stream_can_push(StreamSlave *obj,
> }
>
> static size_t
> -xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len,
> +xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
> bool eop)
> {
> XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> @@ -591,9 +591,9 @@ static void xilinx_axidma_init(Object *obj)
> static Property axidma_properties[] = {
> DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
> DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA,
> - tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
> + tx_data_dev, TYPE_STREAM_SINK, StreamSink *),
> DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA,
> - tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
> + tx_control_dev, TYPE_STREAM_SINK, StreamSink *),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -606,21 +606,21 @@ static void axidma_class_init(ObjectClass *klass, void *data)
> device_class_set_props(dc, axidma_properties);
> }
>
> -static StreamSlaveClass xilinx_axidma_data_stream_class = {
> +static StreamSinkClass xilinx_axidma_data_stream_class = {
> .push = xilinx_axidma_data_stream_push,
> .can_push = xilinx_axidma_data_stream_can_push,
> };
>
> -static StreamSlaveClass xilinx_axidma_control_stream_class = {
> +static StreamSinkClass xilinx_axidma_control_stream_class = {
> .push = xilinx_axidma_control_stream_push,
> };
>
> static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data)
> {
> - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
> + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
>
> - ssc->push = ((StreamSlaveClass *)data)->push;
> - ssc->can_push = ((StreamSlaveClass *)data)->can_push;
> + ssc->push = ((StreamSinkClass *)data)->push;
> + ssc->can_push = ((StreamSinkClass *)data)->can_push;
> }
>
> static const TypeInfo axidma_info = {
> @@ -638,7 +638,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
> .class_init = xilinx_axidma_stream_class_init,
> .class_data = &xilinx_axidma_data_stream_class,
> .interfaces = (InterfaceInfo[]) {
> - { TYPE_STREAM_SLAVE },
> + { TYPE_STREAM_SINK },
> { }
> }
> };
> @@ -650,7 +650,7 @@ static const TypeInfo xilinx_axidma_control_stream_info = {
> .class_init = xilinx_axidma_stream_class_init,
> .class_data = &xilinx_axidma_control_stream_class,
> .interfaces = (InterfaceInfo[]) {
> - { TYPE_STREAM_SLAVE },
> + { TYPE_STREAM_SINK },
> { }
> }
> };
> diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> index 2e89f236b4a..0c4ac727207 100644
> --- a/hw/net/xilinx_axienet.c
> +++ b/hw/net/xilinx_axienet.c
> @@ -323,8 +323,8 @@ struct XilinxAXIEnet {
> SysBusDevice busdev;
> MemoryRegion iomem;
> qemu_irq irq;
> - StreamSlave *tx_data_dev;
> - StreamSlave *tx_control_dev;
> + StreamSink *tx_data_dev;
> + StreamSink *tx_control_dev;
> XilinxAXIEnetStreamSlave rx_data_dev;
> XilinxAXIEnetStreamSlave rx_control_dev;
> NICState *nic;
> @@ -855,7 +855,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
> }
>
> static size_t
> -xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
> +xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
> bool eop)
> {
> int i;
> @@ -877,7 +877,7 @@ xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
> }
>
> static size_t
> -xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,
> +xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
> bool eop)
> {
> XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
> @@ -1005,9 +1005,9 @@ static Property xilinx_enet_properties[] = {
> DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
> DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
> DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet,
> - tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
> + tx_data_dev, TYPE_STREAM_SINK, StreamSink *),
> DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet,
> - tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
> + tx_control_dev, TYPE_STREAM_SINK, StreamSink *),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> @@ -1023,14 +1023,14 @@ static void xilinx_enet_class_init(ObjectClass *klass, void *data)
> static void xilinx_enet_control_stream_class_init(ObjectClass *klass,
> void *data)
> {
> - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
> + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
>
> ssc->push = xilinx_axienet_control_stream_push;
> }
>
> static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data)
> {
> - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
> + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
>
> ssc->push = xilinx_axienet_data_stream_push;
> }
> @@ -1049,7 +1049,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
> .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> .class_init = xilinx_enet_data_stream_class_init,
> .interfaces = (InterfaceInfo[]) {
> - { TYPE_STREAM_SLAVE },
> + { TYPE_STREAM_SINK },
> { }
> }
> };
> @@ -1060,7 +1060,7 @@ static const TypeInfo xilinx_enet_control_stream_info = {
> .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> .class_init = xilinx_enet_control_stream_class_init,
> .interfaces = (InterfaceInfo[]) {
> - { TYPE_STREAM_SLAVE },
> + { TYPE_STREAM_SINK },
> { }
> }
> };
> diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
> index b9371dbf8d7..6109ba55107 100644
> --- a/hw/ssi/xilinx_spips.c
> +++ b/hw/ssi/xilinx_spips.c
> @@ -1353,7 +1353,7 @@ static void xlnx_zynqmp_qspips_init(Object *obj)
> {
> XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj);
>
> - object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE,
> + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK,
> (Object **)&rq->dma,
> object_property_allow_set_link,
> OBJ_PROP_LINK_STRONG);
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink
2020-09-11 7:28 ` Paolo Bonzini
@ 2020-09-11 7:30 ` Edgar E. Iglesias
0 siblings, 0 replies; 27+ messages in thread
From: Edgar E. Iglesias @ 2020-09-11 7:30 UTC (permalink / raw)
To: Paolo Bonzini
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Philippe Mathieu-Daudé, Jason Wang, Marcelo Tosatti,
qemu-devel, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Alex Bennée, Richard Henderson
On Fri, Sep 11, 2020 at 09:28:16AM +0200, Paolo Bonzini wrote:
> On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> > In order to use inclusive terminology, rename 'slave stream'
> > as 'sink stream'.
> >
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
> From Edgar Iglesias:
>
> Regarding streams, our stream module can be used to model a stream
> channel such as AXI stream but also other similar stream protocols. We
> actually don't use the AXI stream terminology [in hw/core/stream.c].
> E.g, we use buf instead of DATA, EOP (end-of-packet) instead of LAST and
> have a flow-control mechanism that doesn't refer to valid/ready. IMO,
> since we're not matching specific protocol names, it would be fine to
> switch to generic terms like Source and Sink.
>
> Therefore,
>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
>
Thanks Paolo,
Yes, looks good to me!
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
>
> > ---
> > include/hw/ssi/xilinx_spips.h | 2 +-
> > include/hw/stream.h | 46 +++++++++++++++++------------------
> > hw/core/stream.c | 20 +++++++--------
> > hw/dma/xilinx_axidma.c | 32 ++++++++++++------------
> > hw/net/xilinx_axienet.c | 20 +++++++--------
> > hw/ssi/xilinx_spips.c | 2 +-
> > 6 files changed, 61 insertions(+), 61 deletions(-)
> >
> > diff --git a/include/hw/ssi/xilinx_spips.h b/include/hw/ssi/xilinx_spips.h
> > index 6a39b55a7bd..fde8a3ebda6 100644
> > --- a/include/hw/ssi/xilinx_spips.h
> > +++ b/include/hw/ssi/xilinx_spips.h
> > @@ -97,7 +97,7 @@ typedef struct {
> > typedef struct {
> > XilinxQSPIPS parent_obj;
> >
> > - StreamSlave *dma;
> > + StreamSink *dma;
> > int gqspi_irqline;
> >
> > uint32_t regs[XLNX_ZYNQMP_SPIPS_R_MAX];
> > diff --git a/include/hw/stream.h b/include/hw/stream.h
> > index ed09e83683d..8ca161991ca 100644
> > --- a/include/hw/stream.h
> > +++ b/include/hw/stream.h
> > @@ -3,52 +3,52 @@
> >
> > #include "qom/object.h"
> >
> > -/* stream slave. Used until qdev provides a generic way. */
> > -#define TYPE_STREAM_SLAVE "stream-slave"
> > +/* stream sink. Used until qdev provides a generic way. */
> > +#define TYPE_STREAM_SINK "stream-slave"
> >
> > -#define STREAM_SLAVE_CLASS(klass) \
> > - OBJECT_CLASS_CHECK(StreamSlaveClass, (klass), TYPE_STREAM_SLAVE)
> > -#define STREAM_SLAVE_GET_CLASS(obj) \
> > - OBJECT_GET_CLASS(StreamSlaveClass, (obj), TYPE_STREAM_SLAVE)
> > -#define STREAM_SLAVE(obj) \
> > - INTERFACE_CHECK(StreamSlave, (obj), TYPE_STREAM_SLAVE)
> > +#define STREAM_SINK_CLASS(klass) \
> > + OBJECT_CLASS_CHECK(StreamSinkClass, (klass), TYPE_STREAM_SINK)
> > +#define STREAM_SINK_GET_CLASS(obj) \
> > + OBJECT_GET_CLASS(StreamSinkClass, (obj), TYPE_STREAM_SINK)
> > +#define STREAM_SINK(obj) \
> > + INTERFACE_CHECK(StreamSink, (obj), TYPE_STREAM_SINK)
> >
> > -typedef struct StreamSlave StreamSlave;
> > +typedef struct StreamSink StreamSink;
> >
> > typedef void (*StreamCanPushNotifyFn)(void *opaque);
> >
> > -typedef struct StreamSlaveClass {
> > +typedef struct StreamSinkClass {
> > InterfaceClass parent;
> > /**
> > - * can push - determine if a stream slave is capable of accepting at least
> > + * can push - determine if a stream sink is capable of accepting at least
> > * one byte of data. Returns false if cannot accept. If not implemented, the
> > - * slave is assumed to always be capable of receiving.
> > - * @notify: Optional callback that the slave will call when the slave is
> > + * sink is assumed to always be capable of receiving.
> > + * @notify: Optional callback that the sink will call when the sink is
> > * capable of receiving again. Only called if false is returned.
> > * @notify_opaque: opaque data to pass to notify call.
> > */
> > - bool (*can_push)(StreamSlave *obj, StreamCanPushNotifyFn notify,
> > + bool (*can_push)(StreamSink *obj, StreamCanPushNotifyFn notify,
> > void *notify_opaque);
> > /**
> > - * push - push data to a Stream slave. The number of bytes pushed is
> > - * returned. If the slave short returns, the master must wait before trying
> > - * again, the slave may continue to just return 0 waiting for the vm time to
> > + * push - push data to a Stream sink. The number of bytes pushed is
> > + * returned. If the sink short returns, the master must wait before trying
> > + * again, the sink may continue to just return 0 waiting for the vm time to
> > * advance. The can_push() function can be used to trap the point in time
> > - * where the slave is ready to receive again, otherwise polling on a QEMU
> > + * where the sink is ready to receive again, otherwise polling on a QEMU
> > * timer will work.
> > - * @obj: Stream slave to push to
> > + * @obj: Stream sink to push to
> > * @buf: Data to write
> > * @len: Maximum number of bytes to write
> > * @eop: End of packet flag
> > */
> > - size_t (*push)(StreamSlave *obj, unsigned char *buf, size_t len, bool eop);
> > -} StreamSlaveClass;
> > + size_t (*push)(StreamSink *obj, unsigned char *buf, size_t len, bool eop);
> > +} StreamSinkClass;
> >
> > size_t
> > -stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop);
> > +stream_push(StreamSink *sink, uint8_t *buf, size_t len, bool eop);
> >
> > bool
> > -stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify,
> > +stream_can_push(StreamSink *sink, StreamCanPushNotifyFn notify,
> > void *notify_opaque);
> >
> >
> > diff --git a/hw/core/stream.c b/hw/core/stream.c
> > index a65ad1208d8..19477d0f2df 100644
> > --- a/hw/core/stream.c
> > +++ b/hw/core/stream.c
> > @@ -3,32 +3,32 @@
> > #include "qemu/module.h"
> >
> > size_t
> > -stream_push(StreamSlave *sink, uint8_t *buf, size_t len, bool eop)
> > +stream_push(StreamSink *sink, uint8_t *buf, size_t len, bool eop)
> > {
> > - StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
> > + StreamSinkClass *k = STREAM_SINK_GET_CLASS(sink);
> >
> > return k->push(sink, buf, len, eop);
> > }
> >
> > bool
> > -stream_can_push(StreamSlave *sink, StreamCanPushNotifyFn notify,
> > +stream_can_push(StreamSink *sink, StreamCanPushNotifyFn notify,
> > void *notify_opaque)
> > {
> > - StreamSlaveClass *k = STREAM_SLAVE_GET_CLASS(sink);
> > + StreamSinkClass *k = STREAM_SINK_GET_CLASS(sink);
> >
> > return k->can_push ? k->can_push(sink, notify, notify_opaque) : true;
> > }
> >
> > -static const TypeInfo stream_slave_info = {
> > - .name = TYPE_STREAM_SLAVE,
> > +static const TypeInfo stream_sink_info = {
> > + .name = TYPE_STREAM_SINK,
> > .parent = TYPE_INTERFACE,
> > - .class_size = sizeof(StreamSlaveClass),
> > + .class_size = sizeof(StreamSinkClass),
> > };
> >
> >
> > -static void stream_slave_register_types(void)
> > +static void stream_sink_register_types(void)
> > {
> > - type_register_static(&stream_slave_info);
> > + type_register_static(&stream_sink_info);
> > }
> >
> > -type_init(stream_slave_register_types)
> > +type_init(stream_sink_register_types)
> > diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
> > index a4812e480a0..cf12a852ea1 100644
> > --- a/hw/dma/xilinx_axidma.c
> > +++ b/hw/dma/xilinx_axidma.c
> > @@ -131,8 +131,8 @@ struct XilinxAXIDMA {
> > AddressSpace as;
> >
> > uint32_t freqhz;
> > - StreamSlave *tx_data_dev;
> > - StreamSlave *tx_control_dev;
> > + StreamSink *tx_data_dev;
> > + StreamSink *tx_control_dev;
> > XilinxAXIDMAStreamSlave rx_data_dev;
> > XilinxAXIDMAStreamSlave rx_control_dev;
> >
> > @@ -264,8 +264,8 @@ static void stream_complete(struct Stream *s)
> > ptimer_transaction_commit(s->ptimer);
> > }
> >
> > -static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
> > - StreamSlave *tx_control_dev)
> > +static void stream_process_mem2s(struct Stream *s, StreamSink *tx_data_dev,
> > + StreamSink *tx_control_dev)
> > {
> > uint32_t prev_d;
> > uint32_t txlen;
> > @@ -387,7 +387,7 @@ static void xilinx_axidma_reset(DeviceState *dev)
> > }
> >
> > static size_t
> > -xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
> > +xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
> > size_t len, bool eop)
> > {
> > XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
> > @@ -403,7 +403,7 @@ xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
> > }
> >
> > static bool
> > -xilinx_axidma_data_stream_can_push(StreamSlave *obj,
> > +xilinx_axidma_data_stream_can_push(StreamSink *obj,
> > StreamCanPushNotifyFn notify,
> > void *notify_opaque)
> > {
> > @@ -420,7 +420,7 @@ xilinx_axidma_data_stream_can_push(StreamSlave *obj,
> > }
> >
> > static size_t
> > -xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len,
> > +xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
> > bool eop)
> > {
> > XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> > @@ -591,9 +591,9 @@ static void xilinx_axidma_init(Object *obj)
> > static Property axidma_properties[] = {
> > DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
> > DEFINE_PROP_LINK("axistream-connected", XilinxAXIDMA,
> > - tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
> > + tx_data_dev, TYPE_STREAM_SINK, StreamSink *),
> > DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIDMA,
> > - tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
> > + tx_control_dev, TYPE_STREAM_SINK, StreamSink *),
> > DEFINE_PROP_END_OF_LIST(),
> > };
> >
> > @@ -606,21 +606,21 @@ static void axidma_class_init(ObjectClass *klass, void *data)
> > device_class_set_props(dc, axidma_properties);
> > }
> >
> > -static StreamSlaveClass xilinx_axidma_data_stream_class = {
> > +static StreamSinkClass xilinx_axidma_data_stream_class = {
> > .push = xilinx_axidma_data_stream_push,
> > .can_push = xilinx_axidma_data_stream_can_push,
> > };
> >
> > -static StreamSlaveClass xilinx_axidma_control_stream_class = {
> > +static StreamSinkClass xilinx_axidma_control_stream_class = {
> > .push = xilinx_axidma_control_stream_push,
> > };
> >
> > static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data)
> > {
> > - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
> > + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
> >
> > - ssc->push = ((StreamSlaveClass *)data)->push;
> > - ssc->can_push = ((StreamSlaveClass *)data)->can_push;
> > + ssc->push = ((StreamSinkClass *)data)->push;
> > + ssc->can_push = ((StreamSinkClass *)data)->can_push;
> > }
> >
> > static const TypeInfo axidma_info = {
> > @@ -638,7 +638,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
> > .class_init = xilinx_axidma_stream_class_init,
> > .class_data = &xilinx_axidma_data_stream_class,
> > .interfaces = (InterfaceInfo[]) {
> > - { TYPE_STREAM_SLAVE },
> > + { TYPE_STREAM_SINK },
> > { }
> > }
> > };
> > @@ -650,7 +650,7 @@ static const TypeInfo xilinx_axidma_control_stream_info = {
> > .class_init = xilinx_axidma_stream_class_init,
> > .class_data = &xilinx_axidma_control_stream_class,
> > .interfaces = (InterfaceInfo[]) {
> > - { TYPE_STREAM_SLAVE },
> > + { TYPE_STREAM_SINK },
> > { }
> > }
> > };
> > diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> > index 2e89f236b4a..0c4ac727207 100644
> > --- a/hw/net/xilinx_axienet.c
> > +++ b/hw/net/xilinx_axienet.c
> > @@ -323,8 +323,8 @@ struct XilinxAXIEnet {
> > SysBusDevice busdev;
> > MemoryRegion iomem;
> > qemu_irq irq;
> > - StreamSlave *tx_data_dev;
> > - StreamSlave *tx_control_dev;
> > + StreamSink *tx_data_dev;
> > + StreamSink *tx_control_dev;
> > XilinxAXIEnetStreamSlave rx_data_dev;
> > XilinxAXIEnetStreamSlave rx_control_dev;
> > NICState *nic;
> > @@ -855,7 +855,7 @@ static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
> > }
> >
> > static size_t
> > -xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
> > +xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
> > bool eop)
> > {
> > int i;
> > @@ -877,7 +877,7 @@ xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
> > }
> >
> > static size_t
> > -xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,
> > +xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
> > bool eop)
> > {
> > XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
> > @@ -1005,9 +1005,9 @@ static Property xilinx_enet_properties[] = {
> > DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
> > DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
> > DEFINE_PROP_LINK("axistream-connected", XilinxAXIEnet,
> > - tx_data_dev, TYPE_STREAM_SLAVE, StreamSlave *),
> > + tx_data_dev, TYPE_STREAM_SINK, StreamSink *),
> > DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet,
> > - tx_control_dev, TYPE_STREAM_SLAVE, StreamSlave *),
> > + tx_control_dev, TYPE_STREAM_SINK, StreamSink *),
> > DEFINE_PROP_END_OF_LIST(),
> > };
> >
> > @@ -1023,14 +1023,14 @@ static void xilinx_enet_class_init(ObjectClass *klass, void *data)
> > static void xilinx_enet_control_stream_class_init(ObjectClass *klass,
> > void *data)
> > {
> > - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
> > + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
> >
> > ssc->push = xilinx_axienet_control_stream_push;
> > }
> >
> > static void xilinx_enet_data_stream_class_init(ObjectClass *klass, void *data)
> > {
> > - StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
> > + StreamSinkClass *ssc = STREAM_SINK_CLASS(klass);
> >
> > ssc->push = xilinx_axienet_data_stream_push;
> > }
> > @@ -1049,7 +1049,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
> > .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> > .class_init = xilinx_enet_data_stream_class_init,
> > .interfaces = (InterfaceInfo[]) {
> > - { TYPE_STREAM_SLAVE },
> > + { TYPE_STREAM_SINK },
> > { }
> > }
> > };
> > @@ -1060,7 +1060,7 @@ static const TypeInfo xilinx_enet_control_stream_info = {
> > .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> > .class_init = xilinx_enet_control_stream_class_init,
> > .interfaces = (InterfaceInfo[]) {
> > - { TYPE_STREAM_SLAVE },
> > + { TYPE_STREAM_SINK },
> > { }
> > }
> > };
> > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
> > index b9371dbf8d7..6109ba55107 100644
> > --- a/hw/ssi/xilinx_spips.c
> > +++ b/hw/ssi/xilinx_spips.c
> > @@ -1353,7 +1353,7 @@ static void xlnx_zynqmp_qspips_init(Object *obj)
> > {
> > XlnxZynqMPQSPIPS *rq = XLNX_ZYNQMP_QSPIPS(obj);
> >
> > - object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SLAVE,
> > + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK,
> > (Object **)&rq->dma,
> > object_property_allow_set_link,
> > OBJ_PROP_LINK_STRONG);
> >
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 3/6] hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink
2020-09-10 7:01 [PATCH 0/6] misc: Some inclusive terminology changes Philippe Mathieu-Daudé
2020-09-10 7:01 ` [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices Philippe Mathieu-Daudé
2020-09-10 7:01 ` [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink Philippe Mathieu-Daudé
@ 2020-09-10 7:01 ` Philippe Mathieu-Daudé
2020-09-11 7:28 ` Paolo Bonzini
2020-09-10 7:01 ` [PATCH 4/6] hw/net/xilinx_axienet: " Philippe Mathieu-Daudé
` (4 subsequent siblings)
7 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-10 7:01 UTC (permalink / raw)
To: qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Philippe Mathieu-Daudé, Jason Wang, Marcelo Tosatti,
Joel Stanley, qemu-trivial, qemu-arm, Cédric Le Goater,
Paolo Bonzini, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
In order to use inclusive terminology, rename 'slave stream'
as 'sink stream'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/dma/xilinx_axidma.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
index cf12a852ea1..19e14a2997e 100644
--- a/hw/dma/xilinx_axidma.c
+++ b/hw/dma/xilinx_axidma.c
@@ -46,11 +46,11 @@
OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
#define XILINX_AXI_DMA_DATA_STREAM(obj) \
- OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
+ OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\
TYPE_XILINX_AXI_DMA_DATA_STREAM)
#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
- OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
+ OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\
TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
#define R_DMACR (0x00 / 4)
@@ -63,7 +63,7 @@
#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
typedef struct XilinxAXIDMA XilinxAXIDMA;
-typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
+typedef struct XilinxAXIDMAStreamSink XilinxAXIDMAStreamSink;
enum {
DMACR_RUNSTOP = 1,
@@ -118,7 +118,7 @@ struct Stream {
unsigned char txbuf[16 * 1024];
};
-struct XilinxAXIDMAStreamSlave {
+struct XilinxAXIDMAStreamSink {
Object parent;
struct XilinxAXIDMA *dma;
@@ -133,8 +133,8 @@ struct XilinxAXIDMA {
uint32_t freqhz;
StreamSink *tx_data_dev;
StreamSink *tx_control_dev;
- XilinxAXIDMAStreamSlave rx_data_dev;
- XilinxAXIDMAStreamSlave rx_control_dev;
+ XilinxAXIDMAStreamSink rx_data_dev;
+ XilinxAXIDMAStreamSink rx_control_dev;
struct Stream streams[2];
@@ -390,7 +390,7 @@ static size_t
xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
size_t len, bool eop)
{
- XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
+ XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
struct Stream *s = &cs->dma->streams[1];
if (len != CONTROL_PAYLOAD_SIZE) {
@@ -407,7 +407,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
StreamCanPushNotifyFn notify,
void *notify_opaque)
{
- XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
+ XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
struct Stream *s = &ds->dma->streams[1];
if (!stream_running(s) || stream_idle(s)) {
@@ -423,7 +423,7 @@ static size_t
xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
bool eop)
{
- XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
+ XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
struct Stream *s = &ds->dma->streams[1];
size_t ret;
@@ -534,8 +534,8 @@ static const MemoryRegionOps axidma_ops = {
static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
{
XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
- XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
- XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
+ XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
+ XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(
&s->rx_control_dev);
int i;
@@ -634,7 +634,7 @@ static const TypeInfo axidma_info = {
static const TypeInfo xilinx_axidma_data_stream_info = {
.name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
.parent = TYPE_OBJECT,
- .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
+ .instance_size = sizeof(struct XilinxAXIDMAStreamSink),
.class_init = xilinx_axidma_stream_class_init,
.class_data = &xilinx_axidma_data_stream_class,
.interfaces = (InterfaceInfo[]) {
@@ -646,7 +646,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
static const TypeInfo xilinx_axidma_control_stream_info = {
.name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
.parent = TYPE_OBJECT,
- .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
+ .instance_size = sizeof(struct XilinxAXIDMAStreamSink),
.class_init = xilinx_axidma_stream_class_init,
.class_data = &xilinx_axidma_control_stream_class,
.interfaces = (InterfaceInfo[]) {
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 3/6] hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink
2020-09-10 7:01 ` [PATCH 3/6] hw/dma/xilinx_axidma: " Philippe Mathieu-Daudé
@ 2020-09-11 7:28 ` Paolo Bonzini
2020-09-11 7:31 ` Edgar E. Iglesias
0 siblings, 1 reply; 27+ messages in thread
From: Paolo Bonzini @ 2020-09-11 7:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Jason Wang, Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename 'slave stream'
> as 'sink stream'.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/dma/xilinx_axidma.c | 26 +++++++++++++-------------
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
> index cf12a852ea1..19e14a2997e 100644
> --- a/hw/dma/xilinx_axidma.c
> +++ b/hw/dma/xilinx_axidma.c
> @@ -46,11 +46,11 @@
> OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
>
> #define XILINX_AXI_DMA_DATA_STREAM(obj) \
> - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
> + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\
> TYPE_XILINX_AXI_DMA_DATA_STREAM)
>
> #define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
> - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
> + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\
> TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
>
> #define R_DMACR (0x00 / 4)
> @@ -63,7 +63,7 @@
> #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
>
> typedef struct XilinxAXIDMA XilinxAXIDMA;
> -typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
> +typedef struct XilinxAXIDMAStreamSink XilinxAXIDMAStreamSink;
>
> enum {
> DMACR_RUNSTOP = 1,
> @@ -118,7 +118,7 @@ struct Stream {
> unsigned char txbuf[16 * 1024];
> };
>
> -struct XilinxAXIDMAStreamSlave {
> +struct XilinxAXIDMAStreamSink {
> Object parent;
>
> struct XilinxAXIDMA *dma;
> @@ -133,8 +133,8 @@ struct XilinxAXIDMA {
> uint32_t freqhz;
> StreamSink *tx_data_dev;
> StreamSink *tx_control_dev;
> - XilinxAXIDMAStreamSlave rx_data_dev;
> - XilinxAXIDMAStreamSlave rx_control_dev;
> + XilinxAXIDMAStreamSink rx_data_dev;
> + XilinxAXIDMAStreamSink rx_control_dev;
>
> struct Stream streams[2];
>
> @@ -390,7 +390,7 @@ static size_t
> xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
> size_t len, bool eop)
> {
> - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
> + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
> struct Stream *s = &cs->dma->streams[1];
>
> if (len != CONTROL_PAYLOAD_SIZE) {
> @@ -407,7 +407,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
> StreamCanPushNotifyFn notify,
> void *notify_opaque)
> {
> - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> struct Stream *s = &ds->dma->streams[1];
>
> if (!stream_running(s) || stream_idle(s)) {
> @@ -423,7 +423,7 @@ static size_t
> xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
> bool eop)
> {
> - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> struct Stream *s = &ds->dma->streams[1];
> size_t ret;
>
> @@ -534,8 +534,8 @@ static const MemoryRegionOps axidma_ops = {
> static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
> {
> XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
> - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
> - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
> + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
> + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(
> &s->rx_control_dev);
> int i;
>
> @@ -634,7 +634,7 @@ static const TypeInfo axidma_info = {
> static const TypeInfo xilinx_axidma_data_stream_info = {
> .name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
> .parent = TYPE_OBJECT,
> - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
> + .instance_size = sizeof(struct XilinxAXIDMAStreamSink),
> .class_init = xilinx_axidma_stream_class_init,
> .class_data = &xilinx_axidma_data_stream_class,
> .interfaces = (InterfaceInfo[]) {
> @@ -646,7 +646,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
> static const TypeInfo xilinx_axidma_control_stream_info = {
> .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
> .parent = TYPE_OBJECT,
> - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
> + .instance_size = sizeof(struct XilinxAXIDMAStreamSink),
> .class_init = xilinx_axidma_stream_class_init,
> .class_data = &xilinx_axidma_control_stream_class,
> .interfaces = (InterfaceInfo[]) {
>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 3/6] hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink
2020-09-11 7:28 ` Paolo Bonzini
@ 2020-09-11 7:31 ` Edgar E. Iglesias
0 siblings, 0 replies; 27+ messages in thread
From: Edgar E. Iglesias @ 2020-09-11 7:31 UTC (permalink / raw)
To: Paolo Bonzini
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Philippe Mathieu-Daudé, Jason Wang, Marcelo Tosatti,
qemu-devel, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Alex Bennée, Richard Henderson
On Fri, Sep 11, 2020 at 09:28:34AM +0200, Paolo Bonzini wrote:
> On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> > In order to use inclusive terminology, rename 'slave stream'
> > as 'sink stream'.
> >
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > ---
> > hw/dma/xilinx_axidma.c | 26 +++++++++++++-------------
> > 1 file changed, 13 insertions(+), 13 deletions(-)
> >
> > diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
> > index cf12a852ea1..19e14a2997e 100644
> > --- a/hw/dma/xilinx_axidma.c
> > +++ b/hw/dma/xilinx_axidma.c
> > @@ -46,11 +46,11 @@
> > OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
> >
> > #define XILINX_AXI_DMA_DATA_STREAM(obj) \
> > - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
> > + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\
> > TYPE_XILINX_AXI_DMA_DATA_STREAM)
> >
> > #define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
> > - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
> > + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\
> > TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
> >
> > #define R_DMACR (0x00 / 4)
> > @@ -63,7 +63,7 @@
> > #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
> >
> > typedef struct XilinxAXIDMA XilinxAXIDMA;
> > -typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
> > +typedef struct XilinxAXIDMAStreamSink XilinxAXIDMAStreamSink;
> >
> > enum {
> > DMACR_RUNSTOP = 1,
> > @@ -118,7 +118,7 @@ struct Stream {
> > unsigned char txbuf[16 * 1024];
> > };
> >
> > -struct XilinxAXIDMAStreamSlave {
> > +struct XilinxAXIDMAStreamSink {
> > Object parent;
> >
> > struct XilinxAXIDMA *dma;
> > @@ -133,8 +133,8 @@ struct XilinxAXIDMA {
> > uint32_t freqhz;
> > StreamSink *tx_data_dev;
> > StreamSink *tx_control_dev;
> > - XilinxAXIDMAStreamSlave rx_data_dev;
> > - XilinxAXIDMAStreamSlave rx_control_dev;
> > + XilinxAXIDMAStreamSink rx_data_dev;
> > + XilinxAXIDMAStreamSink rx_control_dev;
> >
> > struct Stream streams[2];
> >
> > @@ -390,7 +390,7 @@ static size_t
> > xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
> > size_t len, bool eop)
> > {
> > - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
> > + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
> > struct Stream *s = &cs->dma->streams[1];
> >
> > if (len != CONTROL_PAYLOAD_SIZE) {
> > @@ -407,7 +407,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
> > StreamCanPushNotifyFn notify,
> > void *notify_opaque)
> > {
> > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> > struct Stream *s = &ds->dma->streams[1];
> >
> > if (!stream_running(s) || stream_idle(s)) {
> > @@ -423,7 +423,7 @@ static size_t
> > xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
> > bool eop)
> > {
> > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> > struct Stream *s = &ds->dma->streams[1];
> > size_t ret;
> >
> > @@ -534,8 +534,8 @@ static const MemoryRegionOps axidma_ops = {
> > static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
> > {
> > XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
> > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
> > - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
> > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
> > + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(
> > &s->rx_control_dev);
> > int i;
> >
> > @@ -634,7 +634,7 @@ static const TypeInfo axidma_info = {
> > static const TypeInfo xilinx_axidma_data_stream_info = {
> > .name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
> > .parent = TYPE_OBJECT,
> > - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
> > + .instance_size = sizeof(struct XilinxAXIDMAStreamSink),
> > .class_init = xilinx_axidma_stream_class_init,
> > .class_data = &xilinx_axidma_data_stream_class,
> > .interfaces = (InterfaceInfo[]) {
> > @@ -646,7 +646,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
> > static const TypeInfo xilinx_axidma_control_stream_info = {
> > .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
> > .parent = TYPE_OBJECT,
> > - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
> > + .instance_size = sizeof(struct XilinxAXIDMAStreamSink),
> > .class_init = xilinx_axidma_stream_class_init,
> > .class_data = &xilinx_axidma_control_stream_class,
> > .interfaces = (InterfaceInfo[]) {
> >
>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 4/6] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink
2020-09-10 7:01 [PATCH 0/6] misc: Some inclusive terminology changes Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2020-09-10 7:01 ` [PATCH 3/6] hw/dma/xilinx_axidma: " Philippe Mathieu-Daudé
@ 2020-09-10 7:01 ` Philippe Mathieu-Daudé
2020-09-11 7:28 ` Paolo Bonzini
2020-09-10 7:01 ` [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole' Philippe Mathieu-Daudé
` (3 subsequent siblings)
7 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-10 7:01 UTC (permalink / raw)
To: qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Philippe Mathieu-Daudé, Jason Wang, Marcelo Tosatti,
Joel Stanley, qemu-trivial, qemu-arm, Cédric Le Goater,
Paolo Bonzini, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
In order to use inclusive terminology, rename 'slave stream'
as 'sink stream'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/net/xilinx_axienet.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 0c4ac727207..4e48535f373 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -46,11 +46,11 @@
OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
#define XILINX_AXI_ENET_DATA_STREAM(obj) \
- OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
+ OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
TYPE_XILINX_AXI_ENET_DATA_STREAM)
#define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
- OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
+ OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
/* Advertisement control register. */
@@ -310,10 +310,10 @@ struct TEMAC {
void *parent;
};
-typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
+typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink;
typedef struct XilinxAXIEnet XilinxAXIEnet;
-struct XilinxAXIEnetStreamSlave {
+struct XilinxAXIEnetStreamSink {
Object parent;
struct XilinxAXIEnet *enet;
@@ -325,8 +325,8 @@ struct XilinxAXIEnet {
qemu_irq irq;
StreamSink *tx_data_dev;
StreamSink *tx_control_dev;
- XilinxAXIEnetStreamSlave rx_data_dev;
- XilinxAXIEnetStreamSlave rx_control_dev;
+ XilinxAXIEnetStreamSink rx_data_dev;
+ XilinxAXIEnetStreamSink rx_control_dev;
NICState *nic;
NICConf conf;
@@ -859,7 +859,7 @@ xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
bool eop)
{
int i;
- XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
+ XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
XilinxAXIEnet *s = cs->enet;
assert(eop);
@@ -880,7 +880,7 @@ static size_t
xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
bool eop)
{
- XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
+ XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
XilinxAXIEnet *s = ds->enet;
/* TX enable ? */
@@ -954,8 +954,8 @@ static NetClientInfo net_xilinx_enet_info = {
static void xilinx_enet_realize(DeviceState *dev, Error **errp)
{
XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
- XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
- XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
+ XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
+ XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(
&s->rx_control_dev);
object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
@@ -1046,7 +1046,7 @@ static const TypeInfo xilinx_enet_info = {
static const TypeInfo xilinx_enet_data_stream_info = {
.name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
.parent = TYPE_OBJECT,
- .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
+ .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
.class_init = xilinx_enet_data_stream_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SINK },
@@ -1057,7 +1057,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
static const TypeInfo xilinx_enet_control_stream_info = {
.name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
.parent = TYPE_OBJECT,
- .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
+ .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
.class_init = xilinx_enet_control_stream_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SINK },
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 4/6] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink
2020-09-10 7:01 ` [PATCH 4/6] hw/net/xilinx_axienet: " Philippe Mathieu-Daudé
@ 2020-09-11 7:28 ` Paolo Bonzini
2020-09-11 7:32 ` Edgar E. Iglesias
0 siblings, 1 reply; 27+ messages in thread
From: Paolo Bonzini @ 2020-09-11 7:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Jason Wang, Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename 'slave stream'
> as 'sink stream'.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/net/xilinx_axienet.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> index 0c4ac727207..4e48535f373 100644
> --- a/hw/net/xilinx_axienet.c
> +++ b/hw/net/xilinx_axienet.c
> @@ -46,11 +46,11 @@
> OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
>
> #define XILINX_AXI_ENET_DATA_STREAM(obj) \
> - OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
> + OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
> TYPE_XILINX_AXI_ENET_DATA_STREAM)
>
> #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
> - OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
> + OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
> TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
>
> /* Advertisement control register. */
> @@ -310,10 +310,10 @@ struct TEMAC {
> void *parent;
> };
>
> -typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
> +typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink;
> typedef struct XilinxAXIEnet XilinxAXIEnet;
>
> -struct XilinxAXIEnetStreamSlave {
> +struct XilinxAXIEnetStreamSink {
> Object parent;
>
> struct XilinxAXIEnet *enet;
> @@ -325,8 +325,8 @@ struct XilinxAXIEnet {
> qemu_irq irq;
> StreamSink *tx_data_dev;
> StreamSink *tx_control_dev;
> - XilinxAXIEnetStreamSlave rx_data_dev;
> - XilinxAXIEnetStreamSlave rx_control_dev;
> + XilinxAXIEnetStreamSink rx_data_dev;
> + XilinxAXIEnetStreamSink rx_control_dev;
> NICState *nic;
> NICConf conf;
>
> @@ -859,7 +859,7 @@ xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
> bool eop)
> {
> int i;
> - XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
> + XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
> XilinxAXIEnet *s = cs->enet;
>
> assert(eop);
> @@ -880,7 +880,7 @@ static size_t
> xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
> bool eop)
> {
> - XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
> + XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
> XilinxAXIEnet *s = ds->enet;
>
> /* TX enable ? */
> @@ -954,8 +954,8 @@ static NetClientInfo net_xilinx_enet_info = {
> static void xilinx_enet_realize(DeviceState *dev, Error **errp)
> {
> XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
> - XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
> - XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
> + XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
> + XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(
> &s->rx_control_dev);
>
> object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
> @@ -1046,7 +1046,7 @@ static const TypeInfo xilinx_enet_info = {
> static const TypeInfo xilinx_enet_data_stream_info = {
> .name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
> .parent = TYPE_OBJECT,
> - .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> + .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
> .class_init = xilinx_enet_data_stream_class_init,
> .interfaces = (InterfaceInfo[]) {
> { TYPE_STREAM_SINK },
> @@ -1057,7 +1057,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
> static const TypeInfo xilinx_enet_control_stream_info = {
> .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
> .parent = TYPE_OBJECT,
> - .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> + .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
> .class_init = xilinx_enet_control_stream_class_init,
> .interfaces = (InterfaceInfo[]) {
> { TYPE_STREAM_SINK },
>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 4/6] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink
2020-09-11 7:28 ` Paolo Bonzini
@ 2020-09-11 7:32 ` Edgar E. Iglesias
0 siblings, 0 replies; 27+ messages in thread
From: Edgar E. Iglesias @ 2020-09-11 7:32 UTC (permalink / raw)
To: Paolo Bonzini
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Philippe Mathieu-Daudé, Jason Wang, Marcelo Tosatti,
qemu-devel, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Alex Bennée, Richard Henderson
On Fri, Sep 11, 2020 at 09:28:38AM +0200, Paolo Bonzini wrote:
> On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> > In order to use inclusive terminology, rename 'slave stream'
> > as 'sink stream'.
> >
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > ---
> > hw/net/xilinx_axienet.c | 24 ++++++++++++------------
> > 1 file changed, 12 insertions(+), 12 deletions(-)
> >
> > diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
> > index 0c4ac727207..4e48535f373 100644
> > --- a/hw/net/xilinx_axienet.c
> > +++ b/hw/net/xilinx_axienet.c
> > @@ -46,11 +46,11 @@
> > OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
> >
> > #define XILINX_AXI_ENET_DATA_STREAM(obj) \
> > - OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
> > + OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
> > TYPE_XILINX_AXI_ENET_DATA_STREAM)
> >
> > #define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
> > - OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
> > + OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
> > TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
> >
> > /* Advertisement control register. */
> > @@ -310,10 +310,10 @@ struct TEMAC {
> > void *parent;
> > };
> >
> > -typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
> > +typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink;
> > typedef struct XilinxAXIEnet XilinxAXIEnet;
> >
> > -struct XilinxAXIEnetStreamSlave {
> > +struct XilinxAXIEnetStreamSink {
> > Object parent;
> >
> > struct XilinxAXIEnet *enet;
> > @@ -325,8 +325,8 @@ struct XilinxAXIEnet {
> > qemu_irq irq;
> > StreamSink *tx_data_dev;
> > StreamSink *tx_control_dev;
> > - XilinxAXIEnetStreamSlave rx_data_dev;
> > - XilinxAXIEnetStreamSlave rx_control_dev;
> > + XilinxAXIEnetStreamSink rx_data_dev;
> > + XilinxAXIEnetStreamSink rx_control_dev;
> > NICState *nic;
> > NICConf conf;
> >
> > @@ -859,7 +859,7 @@ xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
> > bool eop)
> > {
> > int i;
> > - XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
> > + XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
> > XilinxAXIEnet *s = cs->enet;
> >
> > assert(eop);
> > @@ -880,7 +880,7 @@ static size_t
> > xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
> > bool eop)
> > {
> > - XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
> > + XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
> > XilinxAXIEnet *s = ds->enet;
> >
> > /* TX enable ? */
> > @@ -954,8 +954,8 @@ static NetClientInfo net_xilinx_enet_info = {
> > static void xilinx_enet_realize(DeviceState *dev, Error **errp)
> > {
> > XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
> > - XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
> > - XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
> > + XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
> > + XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(
> > &s->rx_control_dev);
> >
> > object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
> > @@ -1046,7 +1046,7 @@ static const TypeInfo xilinx_enet_info = {
> > static const TypeInfo xilinx_enet_data_stream_info = {
> > .name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
> > .parent = TYPE_OBJECT,
> > - .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> > + .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
> > .class_init = xilinx_enet_data_stream_class_init,
> > .interfaces = (InterfaceInfo[]) {
> > { TYPE_STREAM_SINK },
> > @@ -1057,7 +1057,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
> > static const TypeInfo xilinx_enet_control_stream_info = {
> > .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
> > .parent = TYPE_OBJECT,
> > - .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
> > + .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
> > .class_init = xilinx_enet_control_stream_class_init,
> > .interfaces = (InterfaceInfo[]) {
> > { TYPE_STREAM_SINK },
> >
>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole'
2020-09-10 7:01 [PATCH 0/6] misc: Some inclusive terminology changes Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2020-09-10 7:01 ` [PATCH 4/6] hw/net/xilinx_axienet: " Philippe Mathieu-Daudé
@ 2020-09-10 7:01 ` Philippe Mathieu-Daudé
2020-09-10 7:15 ` Thomas Huth
2020-09-10 7:01 ` [PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken() Philippe Mathieu-Daudé
` (2 subsequent siblings)
7 siblings, 1 reply; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-10 7:01 UTC (permalink / raw)
To: qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Philippe Mathieu-Daudé, Jason Wang, Marcelo Tosatti,
Joel Stanley, qemu-trivial, qemu-arm, Cédric Le Goater,
Paolo Bonzini, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
In order to use inclusive terminology, rename "blackhole"
as "(memory)hole".
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
include/hw/pci-host/q35.h | 4 ++--
hw/pci-host/q35.c | 38 +++++++++++++++++++-------------------
tests/qtest/q35-test.c | 2 +-
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 070305f83df..0fb90aca18b 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -48,8 +48,8 @@ typedef struct MCHPCIState {
PAMMemoryRegion pam_regions[13];
MemoryRegion smram_region, open_high_smram;
MemoryRegion smram, low_smram, high_smram;
- MemoryRegion tseg_blackhole, tseg_window;
- MemoryRegion smbase_blackhole, smbase_window;
+ MemoryRegion tseg_hole, tseg_window;
+ MemoryRegion smbase_hole, smbase_window;
bool has_smram_at_smbase;
Range pci_hole;
uint64_t below_4g_mem_size;
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index b67cb9c29f8..21f58ccfa28 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -266,20 +266,20 @@ static const TypeInfo q35_host_info = {
* MCH D0:F0
*/
-static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size)
+static uint64_t memoryhole_read(void *ptr, hwaddr reg, unsigned size)
{
return 0xffffffff;
}
-static void blackhole_write(void *opaque, hwaddr addr, uint64_t val,
+static void memoryhole_write(void *opaque, hwaddr addr, uint64_t val,
unsigned width)
{
/* nothing */
}
-static const MemoryRegionOps blackhole_ops = {
- .read = blackhole_read,
- .write = blackhole_write,
+static const MemoryRegionOps memoryhole_ops = {
+ .read = memoryhole_read,
+ .write = memoryhole_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
@@ -393,12 +393,12 @@ static void mch_update_smram(MCHPCIState *mch)
} else {
tseg_size = 0;
}
- memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole);
- memory_region_set_enabled(&mch->tseg_blackhole, tseg_size);
- memory_region_set_size(&mch->tseg_blackhole, tseg_size);
+ memory_region_del_subregion(mch->system_memory, &mch->tseg_hole);
+ memory_region_set_enabled(&mch->tseg_hole, tseg_size);
+ memory_region_set_size(&mch->tseg_hole, tseg_size);
memory_region_add_subregion_overlap(mch->system_memory,
mch->below_4g_mem_size - tseg_size,
- &mch->tseg_blackhole, 1);
+ &mch->tseg_hole, 1);
memory_region_set_enabled(&mch->tseg_window, tseg_size);
memory_region_set_size(&mch->tseg_window, tseg_size);
@@ -456,7 +456,7 @@ static void mch_update_smbase_smram(MCHPCIState *mch)
} else {
lck = false;
}
- memory_region_set_enabled(&mch->smbase_blackhole, lck);
+ memory_region_set_enabled(&mch->smbase_hole, lck);
memory_region_set_enabled(&mch->smbase_window, lck);
memory_region_transaction_commit();
}
@@ -601,13 +601,13 @@ static void mch_realize(PCIDevice *d, Error **errp)
memory_region_set_enabled(&mch->high_smram, true);
memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram);
- memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch),
- &blackhole_ops, NULL,
- "tseg-blackhole", 0);
- memory_region_set_enabled(&mch->tseg_blackhole, false);
+ memory_region_init_io(&mch->tseg_hole, OBJECT(mch),
+ &memoryhole_ops, NULL,
+ "tseg-hole", 0);
+ memory_region_set_enabled(&mch->tseg_hole, false);
memory_region_add_subregion_overlap(mch->system_memory,
mch->below_4g_mem_size,
- &mch->tseg_blackhole, 1);
+ &mch->tseg_hole, 1);
memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window",
mch->ram_memory, mch->below_4g_mem_size, 0);
@@ -619,13 +619,13 @@ static void mch_realize(PCIDevice *d, Error **errp)
* This is not what hardware does, so it's QEMU specific hack.
* See commit message for details.
*/
- memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops,
- NULL, "smbase-blackhole",
+ memory_region_init_io(&mch->smbase_hole, OBJECT(mch), &memoryhole_ops,
+ NULL, "smbase-hole",
MCH_HOST_BRIDGE_SMBASE_SIZE);
- memory_region_set_enabled(&mch->smbase_blackhole, false);
+ memory_region_set_enabled(&mch->smbase_hole, false);
memory_region_add_subregion_overlap(mch->system_memory,
MCH_HOST_BRIDGE_SMBASE_ADDR,
- &mch->smbase_blackhole, 1);
+ &mch->smbase_hole, 1);
memory_region_init_alias(&mch->smbase_window, OBJECT(mch),
"smbase-window", mch->ram_memory,
diff --git a/tests/qtest/q35-test.c b/tests/qtest/q35-test.c
index b7cf1449906..7cddd0a7f61 100644
--- a/tests/qtest/q35-test.c
+++ b/tests/qtest/q35-test.c
@@ -231,7 +231,7 @@ static void test_smram_smbase_lock(void)
qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, i);
g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) == 0x02);
- /* RAM access should go into black hole */
+ /* RAM access should go into memory hole */
qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN);
g_assert_cmpint(qtest_readb(qts, SMBASE), ==, 0xff);
}
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole'
2020-09-10 7:01 ` [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole' Philippe Mathieu-Daudé
@ 2020-09-10 7:15 ` Thomas Huth
2020-09-10 7:30 ` Philippe Mathieu-Daudé
` (2 more replies)
0 siblings, 3 replies; 27+ messages in thread
From: Thomas Huth @ 2020-09-10 7:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Alistair Francis, Eduardo Habkost,
kvm, Michael S. Tsirkin, Andrew Jeffery, Jason Wang,
Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Paolo Bonzini, Edgar E. Iglesias,
Alex Bennée, Richard Henderson
On 10/09/2020 09.01, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename "blackhole"
> as "(memory)hole".
A black hole is a well-known astronomical term, which is simply named
that way since it absorbes all light. I doubt that anybody could get
upset by this term?
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> include/hw/pci-host/q35.h | 4 ++--
> hw/pci-host/q35.c | 38 +++++++++++++++++++-------------------
> tests/qtest/q35-test.c | 2 +-
> 3 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
> index 070305f83df..0fb90aca18b 100644
> --- a/include/hw/pci-host/q35.h
> +++ b/include/hw/pci-host/q35.h
> @@ -48,8 +48,8 @@ typedef struct MCHPCIState {
> PAMMemoryRegion pam_regions[13];
> MemoryRegion smram_region, open_high_smram;
> MemoryRegion smram, low_smram, high_smram;
> - MemoryRegion tseg_blackhole, tseg_window;
> - MemoryRegion smbase_blackhole, smbase_window;
> + MemoryRegion tseg_hole, tseg_window;
> + MemoryRegion smbase_hole, smbase_window;
Maybe rather use smbase_memhole and tseg_memhole?
Thomas
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole'
2020-09-10 7:15 ` Thomas Huth
@ 2020-09-10 7:30 ` Philippe Mathieu-Daudé
2020-09-10 9:11 ` Paolo Bonzini
2020-09-10 9:14 ` Daniel P. Berrangé
2 siblings, 0 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-10 7:30 UTC (permalink / raw)
To: Thomas Huth, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Alistair Francis, Eduardo Habkost,
kvm, Michael S. Tsirkin, Andrew Jeffery, Jason Wang,
Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Paolo Bonzini, Edgar E. Iglesias,
Alex Bennée, Richard Henderson
On 9/10/20 9:15 AM, Thomas Huth wrote:
> On 10/09/2020 09.01, Philippe Mathieu-Daudé wrote:
>> In order to use inclusive terminology, rename "blackhole"
>> as "(memory)hole".
>
> A black hole is a well-known astronomical term, which is simply named
> that way since it absorbes all light. I doubt that anybody could get
> upset by this term?
Let's put some light in our address space then :)
But you right, the NASA does not consider renaming this one:
https://www.space.com/nasa-stops-racist-nicknames-cosmic-objects.html
Note than for electronic busses design, master/slave are also
well-known terms, but they might be considered offensive.
I changed this one too because I'm not sure about its offensiveness
threshold.
>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> include/hw/pci-host/q35.h | 4 ++--
>> hw/pci-host/q35.c | 38 +++++++++++++++++++-------------------
>> tests/qtest/q35-test.c | 2 +-
>> 3 files changed, 22 insertions(+), 22 deletions(-)
>>
>> diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
>> index 070305f83df..0fb90aca18b 100644
>> --- a/include/hw/pci-host/q35.h
>> +++ b/include/hw/pci-host/q35.h
>> @@ -48,8 +48,8 @@ typedef struct MCHPCIState {
>> PAMMemoryRegion pam_regions[13];
>> MemoryRegion smram_region, open_high_smram;
>> MemoryRegion smram, low_smram, high_smram;
>> - MemoryRegion tseg_blackhole, tseg_window;
>> - MemoryRegion smbase_blackhole, smbase_window;
>> + MemoryRegion tseg_hole, tseg_window;
>> + MemoryRegion smbase_hole, smbase_window;
>
> Maybe rather use smbase_memhole and tseg_memhole?
OK.
>
> Thomas
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole'
2020-09-10 7:15 ` Thomas Huth
2020-09-10 7:30 ` Philippe Mathieu-Daudé
@ 2020-09-10 9:11 ` Paolo Bonzini
2020-09-10 9:14 ` Daniel P. Berrangé
2 siblings, 0 replies; 27+ messages in thread
From: Paolo Bonzini @ 2020-09-10 9:11 UTC (permalink / raw)
To: Thomas Huth, Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Alistair Francis, Eduardo Habkost,
kvm, Michael S. Tsirkin, Andrew Jeffery, Jason Wang,
Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
On 10/09/20 09:15, Thomas Huth wrote:
> On 10/09/2020 09.01, Philippe Mathieu-Daudé wrote:
>> In order to use inclusive terminology, rename "blackhole"
>> as "(memory)hole".
> A black hole is a well-known astronomical term, which is simply named
> that way since it absorbes all light. I doubt that anybody could get
> upset by this term?
>
Agreed. This is a memory region that absorbs all writes and always
reads as zero, the astronomical reference is obvious.
Paolo
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole'
2020-09-10 7:15 ` Thomas Huth
2020-09-10 7:30 ` Philippe Mathieu-Daudé
2020-09-10 9:11 ` Paolo Bonzini
@ 2020-09-10 9:14 ` Daniel P. Berrangé
2020-09-10 11:36 ` Paolo Bonzini
2 siblings, 1 reply; 27+ messages in thread
From: Daniel P. Berrangé @ 2020-09-10 9:14 UTC (permalink / raw)
To: Thomas Huth
Cc: Laurent Vivier, Peter Maydell, Marcelo Tosatti, Eduardo Habkost,
kvm, Michael S. Tsirkin, Andrew Jeffery, Alex Bennée,
Jason Wang, Alistair Francis, qemu-devel, qemu-trivial, qemu-arm,
Joel Stanley, Edgar E. Iglesias, Paolo Bonzini, Richard Henderson,
Philippe Mathieu-Daudé, Cédric Le Goater
On Thu, Sep 10, 2020 at 09:15:02AM +0200, Thomas Huth wrote:
> On 10/09/2020 09.01, Philippe Mathieu-Daudé wrote:
> > In order to use inclusive terminology, rename "blackhole"
> > as "(memory)hole".
>
> A black hole is a well-known astronomical term, which is simply named
> that way since it absorbes all light. I doubt that anybody could get
> upset by this term?
In this particular case I think the change is the right thing to do
simply because the astronomical analogy is not adding any value in
understanding. Calling it a "memoryhole" is more descriptive in what
is actually is.
>
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > ---
> > include/hw/pci-host/q35.h | 4 ++--
> > hw/pci-host/q35.c | 38 +++++++++++++++++++-------------------
> > tests/qtest/q35-test.c | 2 +-
> > 3 files changed, 22 insertions(+), 22 deletions(-)
> >
> > diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
> > index 070305f83df..0fb90aca18b 100644
> > --- a/include/hw/pci-host/q35.h
> > +++ b/include/hw/pci-host/q35.h
> > @@ -48,8 +48,8 @@ typedef struct MCHPCIState {
> > PAMMemoryRegion pam_regions[13];
> > MemoryRegion smram_region, open_high_smram;
> > MemoryRegion smram, low_smram, high_smram;
> > - MemoryRegion tseg_blackhole, tseg_window;
> > - MemoryRegion smbase_blackhole, smbase_window;
> > + MemoryRegion tseg_hole, tseg_window;
> > + MemoryRegion smbase_hole, smbase_window;
>
> Maybe rather use smbase_memhole and tseg_memhole?
>
> Thomas
>
>
Regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole'
2020-09-10 9:14 ` Daniel P. Berrangé
@ 2020-09-10 11:36 ` Paolo Bonzini
0 siblings, 0 replies; 27+ messages in thread
From: Paolo Bonzini @ 2020-09-10 11:36 UTC (permalink / raw)
To: Daniel P. Berrangé, Thomas Huth
Cc: Laurent Vivier, Peter Maydell, Marcelo Tosatti, Eduardo Habkost,
kvm, Michael S. Tsirkin, Andrew Jeffery, Alex Bennée,
Jason Wang, Alistair Francis, qemu-devel, qemu-trivial, qemu-arm,
Joel Stanley, Edgar E. Iglesias, Richard Henderson,
Philippe Mathieu-Daudé, Cédric Le Goater
On 10/09/20 11:14, Daniel P. Berrangé wrote:
> On Thu, Sep 10, 2020 at 09:15:02AM +0200, Thomas Huth wrote:
>> On 10/09/2020 09.01, Philippe Mathieu-Daudé wrote:
>>> In order to use inclusive terminology, rename "blackhole"
>>> as "(memory)hole".
>>
>> A black hole is a well-known astronomical term, which is simply named
>> that way since it absorbes all light. I doubt that anybody could get
>> upset by this term?
>
> In this particular case I think the change is the right thing to do
> simply because the astronomical analogy is not adding any value in
> understanding. Calling it a "memoryhole" is more descriptive in what
> is actually is.
Absolutely not. A memory hole ("memoryhole" is not an English word)
would be easily confused with a hole in the memory map, which this is
not. For example on x86 systems the "PCI hole" is a hole between the
end of low RAM and the bottom of the ROM that is reserved for memory
mapped devices. The "PCI hole" is explicitly left free by board code so
that the OS can put PCI BARs in there.
These black hole MemoryRegions, instead, are present in the memory map
and their purpose is to absorbs all writes and only sends back zeros,
hiding the contents of SMRAM and TSEG from the guest. Just like a black
hole they are "something that exists".
Therefore, both "memory hole" and "hole" as in Philippe's patch are
worse than the astronomical metaphor.
Paolo
>>
>>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>>> ---
>>> include/hw/pci-host/q35.h | 4 ++--
>>> hw/pci-host/q35.c | 38 +++++++++++++++++++-------------------
>>> tests/qtest/q35-test.c | 2 +-
>>> 3 files changed, 22 insertions(+), 22 deletions(-)
>>>
>>> diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
>>> index 070305f83df..0fb90aca18b 100644
>>> --- a/include/hw/pci-host/q35.h
>>> +++ b/include/hw/pci-host/q35.h
>>> @@ -48,8 +48,8 @@ typedef struct MCHPCIState {
>>> PAMMemoryRegion pam_regions[13];
>>> MemoryRegion smram_region, open_high_smram;
>>> MemoryRegion smram, low_smram, high_smram;
>>> - MemoryRegion tseg_blackhole, tseg_window;
>>> - MemoryRegion smbase_blackhole, smbase_window;
>>> + MemoryRegion tseg_hole, tseg_window;
>>> + MemoryRegion smbase_hole, smbase_window;
>>
>> Maybe rather use smbase_memhole and tseg_memhole?
>>
>> Thomas
>>
>>
>
> Regards,
> Daniel
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken()
2020-09-10 7:01 [PATCH 0/6] misc: Some inclusive terminology changes Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2020-09-10 7:01 ` [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole' Philippe Mathieu-Daudé
@ 2020-09-10 7:01 ` Philippe Mathieu-Daudé
2020-09-10 7:08 ` Thomas Huth
2020-09-10 10:13 ` Laurent Vivier
2020-09-10 7:38 ` [PATCH 0/6] misc: Some inclusive terminology changes Laurent Vivier
2020-09-17 19:02 ` Laurent Vivier
7 siblings, 2 replies; 27+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-09-10 7:01 UTC (permalink / raw)
To: qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Alistair Francis,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Philippe Mathieu-Daudé, Jason Wang, Marcelo Tosatti,
Joel Stanley, qemu-trivial, qemu-arm, Cédric Le Goater,
Paolo Bonzini, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
In order to use inclusive terminology, rename host_tsx_blacklisted()
as host_tsx_broken().
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
target/i386/kvm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 205b68bc0ce..3d640a8decf 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -302,7 +302,7 @@ static int get_para_features(KVMState *s)
return features;
}
-static bool host_tsx_blacklisted(void)
+static bool host_tsx_broken(void)
{
int family, model, stepping;\
char vendor[CPUID_VENDOR_SZ + 1];
@@ -408,7 +408,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
} else if (function == 6 && reg == R_EAX) {
ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
} else if (function == 7 && index == 0 && reg == R_EBX) {
- if (host_tsx_blacklisted()) {
+ if (host_tsx_broken()) {
ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
}
} else if (function == 7 && index == 0 && reg == R_EDX) {
--
2.26.2
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken()
2020-09-10 7:01 ` [PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken() Philippe Mathieu-Daudé
@ 2020-09-10 7:08 ` Thomas Huth
2020-09-10 9:08 ` Paolo Bonzini
2020-09-10 10:13 ` Laurent Vivier
1 sibling, 1 reply; 27+ messages in thread
From: Thomas Huth @ 2020-09-10 7:08 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Alistair Francis, Eduardo Habkost,
kvm, Michael S. Tsirkin, Andrew Jeffery, Jason Wang,
Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Paolo Bonzini, Edgar E. Iglesias,
Alex Bennée, Richard Henderson
On 10/09/2020 09.01, Philippe Mathieu-Daudé wrote:
> In order to use inclusive terminology, rename host_tsx_blacklisted()
> as host_tsx_broken().
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/i386/kvm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/kvm.c b/target/i386/kvm.c
> index 205b68bc0ce..3d640a8decf 100644
> --- a/target/i386/kvm.c
> +++ b/target/i386/kvm.c
> @@ -302,7 +302,7 @@ static int get_para_features(KVMState *s)
> return features;
> }
>
> -static bool host_tsx_blacklisted(void)
> +static bool host_tsx_broken(void)
> {
> int family, model, stepping;\
> char vendor[CPUID_VENDOR_SZ + 1];
> @@ -408,7 +408,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
> } else if (function == 6 && reg == R_EAX) {
> ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
> } else if (function == 7 && index == 0 && reg == R_EBX) {
> - if (host_tsx_blacklisted()) {
> + if (host_tsx_broken()) {
> ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
> }
> } else if (function == 7 && index == 0 && reg == R_EDX) {
>
Looking at commit 40e80ee4113, the term "broken" seems to be a good
replacement here.
Reviewed-by: Thomas Huth <thuth@redhat.com>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken()
2020-09-10 7:08 ` Thomas Huth
@ 2020-09-10 9:08 ` Paolo Bonzini
0 siblings, 0 replies; 27+ messages in thread
From: Paolo Bonzini @ 2020-09-10 9:08 UTC (permalink / raw)
To: Thomas Huth, Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Alistair Francis, Eduardo Habkost,
kvm, Michael S. Tsirkin, Andrew Jeffery, Jason Wang,
Marcelo Tosatti, Joel Stanley, qemu-trivial, qemu-arm,
Cédric Le Goater, Edgar E. Iglesias, Alex Bennée,
Richard Henderson
On 10/09/20 09:08, Thomas Huth wrote:
> On 10/09/2020 09.01, Philippe Mathieu-Daudé wrote:
>> In order to use inclusive terminology, rename host_tsx_blacklisted()
>> as host_tsx_broken().
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> target/i386/kvm.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/target/i386/kvm.c b/target/i386/kvm.c
>> index 205b68bc0ce..3d640a8decf 100644
>> --- a/target/i386/kvm.c
>> +++ b/target/i386/kvm.c
>> @@ -302,7 +302,7 @@ static int get_para_features(KVMState *s)
>> return features;
>> }
>>
>> -static bool host_tsx_blacklisted(void)
>> +static bool host_tsx_broken(void)
>> {
>> int family, model, stepping;\
>> char vendor[CPUID_VENDOR_SZ + 1];
>> @@ -408,7 +408,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
>> } else if (function == 6 && reg == R_EAX) {
>> ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
>> } else if (function == 7 && index == 0 && reg == R_EBX) {
>> - if (host_tsx_blacklisted()) {
>> + if (host_tsx_broken()) {
>> ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
>> }
>> } else if (function == 7 && index == 0 && reg == R_EDX) {
>>
>
> Looking at commit 40e80ee4113, the term "broken" seems to be a good
> replacement here.
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken()
2020-09-10 7:01 ` [PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken() Philippe Mathieu-Daudé
2020-09-10 7:08 ` Thomas Huth
@ 2020-09-10 10:13 ` Laurent Vivier
1 sibling, 0 replies; 27+ messages in thread
From: Laurent Vivier @ 2020-09-10 10:13 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Marcelo Tosatti,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Jason Wang, Alistair Francis, qemu-trivial, qemu-arm,
Joel Stanley, Edgar E. Iglesias, Paolo Bonzini, Richard Henderson,
Alex Bennée, Cédric Le Goater
Le 10/09/2020 à 09:01, Philippe Mathieu-Daudé a écrit :
> In order to use inclusive terminology, rename host_tsx_blacklisted()
> as host_tsx_broken().
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> target/i386/kvm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/i386/kvm.c b/target/i386/kvm.c
> index 205b68bc0ce..3d640a8decf 100644
> --- a/target/i386/kvm.c
> +++ b/target/i386/kvm.c
> @@ -302,7 +302,7 @@ static int get_para_features(KVMState *s)
> return features;
> }
>
> -static bool host_tsx_blacklisted(void)
> +static bool host_tsx_broken(void)
> {
> int family, model, stepping;\
> char vendor[CPUID_VENDOR_SZ + 1];
> @@ -408,7 +408,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
> } else if (function == 6 && reg == R_EAX) {
> ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
> } else if (function == 7 && index == 0 && reg == R_EBX) {
> - if (host_tsx_blacklisted()) {
> + if (host_tsx_broken()) {
> ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
> }
> } else if (function == 7 && index == 0 && reg == R_EDX) {
>
Applied to my trivial-patches branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 0/6] misc: Some inclusive terminology changes
2020-09-10 7:01 [PATCH 0/6] misc: Some inclusive terminology changes Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2020-09-10 7:01 ` [PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken() Philippe Mathieu-Daudé
@ 2020-09-10 7:38 ` Laurent Vivier
2020-09-17 19:02 ` Laurent Vivier
7 siblings, 0 replies; 27+ messages in thread
From: Laurent Vivier @ 2020-09-10 7:38 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Marcelo Tosatti,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Jason Wang, Alistair Francis, qemu-trivial, qemu-arm,
Joel Stanley, Edgar E. Iglesias, Paolo Bonzini, Richard Henderson,
Alex Bennée, Cédric Le Goater
Le 10/09/2020 à 09:01, Philippe Mathieu-Daudé a écrit :
> We don't have (yet?) inclusive terminology guidelines,
> but the PCI hole memory is not "black", the DMA sources
> don't stream to "slaves", and there isn't really a TSX
> "black" list, we only check for broken fields.
>
> As this terms can be considered offensive, and changing
> them is a no-brain operation, simply do it.
>
These changes are technically trivial but they are not from an ethical
point of view. I will add to the trivial branch only if they are acked
by their own maintainers.
Moreover, I think we should have a project level guideline before doing
that to be sure everyone agrees.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 0/6] misc: Some inclusive terminology changes
2020-09-10 7:01 [PATCH 0/6] misc: Some inclusive terminology changes Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2020-09-10 7:38 ` [PATCH 0/6] misc: Some inclusive terminology changes Laurent Vivier
@ 2020-09-17 19:02 ` Laurent Vivier
7 siblings, 0 replies; 27+ messages in thread
From: Laurent Vivier @ 2020-09-17 19:02 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Laurent Vivier, Peter Maydell, Thomas Huth, Marcelo Tosatti,
Eduardo Habkost, kvm, Michael S. Tsirkin, Andrew Jeffery,
Jason Wang, Alistair Francis, qemu-trivial, qemu-arm,
Joel Stanley, Edgar E. Iglesias, Paolo Bonzini, Richard Henderson,
Alex Bennée, Cédric Le Goater
Le 10/09/2020 à 09:01, Philippe Mathieu-Daudé a écrit :
> We don't have (yet?) inclusive terminology guidelines,
> but the PCI hole memory is not "black", the DMA sources
> don't stream to "slaves", and there isn't really a TSX
> "black" list, we only check for broken fields.
>
> As this terms can be considered offensive, and changing
> them is a no-brain operation, simply do it.
>
> Philippe Mathieu-Daudé (6):
> hw/ssi/aspeed_smc: Rename max_slaves as max_devices
> hw/core/stream: Rename StreamSlave as StreamSink
> hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink
> hw/net/xilinx_axienet: Rename StreamSlave as StreamSink
> hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole'
> target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken()
>
> include/hw/pci-host/q35.h | 4 +--
> include/hw/ssi/aspeed_smc.h | 2 +-
> include/hw/ssi/xilinx_spips.h | 2 +-
> include/hw/stream.h | 46 +++++++++++++--------------
> hw/core/stream.c | 20 ++++++------
> hw/dma/xilinx_axidma.c | 58 +++++++++++++++++------------------
> hw/net/xilinx_axienet.c | 44 +++++++++++++-------------
> hw/pci-host/q35.c | 38 +++++++++++------------
> hw/ssi/aspeed_smc.c | 40 ++++++++++++------------
> hw/ssi/xilinx_spips.c | 2 +-
> target/i386/kvm.c | 4 +--
> tests/qtest/q35-test.c | 2 +-
> 12 files changed, 131 insertions(+), 131 deletions(-)
>
Philippe,
Could you report your series: it doesn't apply cleanly on my branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 27+ messages in thread