From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Laurent Vivier" <lvivier@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Thomas Huth" <thuth@redhat.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Eduardo Habkost" <ehabkost@redhat.com>,
kvm@vger.kernel.org, "Michael S. Tsirkin" <mst@redhat.com>,
"Andrew Jeffery" <andrew@aj.id.au>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Jason Wang" <jasowang@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Joel Stanley" <joel@jms.id.au>,
qemu-trivial@nongnu.org, qemu-arm@nongnu.org,
"Cédric Le Goater" <clg@kaod.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: [PATCH 4/6] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink
Date: Thu, 10 Sep 2020 09:01:29 +0200 [thread overview]
Message-ID: <20200910070131.435543-5-philmd@redhat.com> (raw)
In-Reply-To: <20200910070131.435543-1-philmd@redhat.com>
In order to use inclusive terminology, rename 'slave stream'
as 'sink stream'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/net/xilinx_axienet.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 0c4ac727207..4e48535f373 100644
--- a/hw/net/xilinx_axienet.c
+++ b/hw/net/xilinx_axienet.c
@@ -46,11 +46,11 @@
OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
#define XILINX_AXI_ENET_DATA_STREAM(obj) \
- OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
+ OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
TYPE_XILINX_AXI_ENET_DATA_STREAM)
#define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
- OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
+ OBJECT_CHECK(XilinxAXIEnetStreamSink, (obj),\
TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
/* Advertisement control register. */
@@ -310,10 +310,10 @@ struct TEMAC {
void *parent;
};
-typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
+typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink;
typedef struct XilinxAXIEnet XilinxAXIEnet;
-struct XilinxAXIEnetStreamSlave {
+struct XilinxAXIEnetStreamSink {
Object parent;
struct XilinxAXIEnet *enet;
@@ -325,8 +325,8 @@ struct XilinxAXIEnet {
qemu_irq irq;
StreamSink *tx_data_dev;
StreamSink *tx_control_dev;
- XilinxAXIEnetStreamSlave rx_data_dev;
- XilinxAXIEnetStreamSlave rx_control_dev;
+ XilinxAXIEnetStreamSink rx_data_dev;
+ XilinxAXIEnetStreamSink rx_control_dev;
NICState *nic;
NICConf conf;
@@ -859,7 +859,7 @@ xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
bool eop)
{
int i;
- XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
+ XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
XilinxAXIEnet *s = cs->enet;
assert(eop);
@@ -880,7 +880,7 @@ static size_t
xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
bool eop)
{
- XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
+ XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
XilinxAXIEnet *s = ds->enet;
/* TX enable ? */
@@ -954,8 +954,8 @@ static NetClientInfo net_xilinx_enet_info = {
static void xilinx_enet_realize(DeviceState *dev, Error **errp)
{
XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
- XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
- XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
+ XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
+ XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(
&s->rx_control_dev);
object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
@@ -1046,7 +1046,7 @@ static const TypeInfo xilinx_enet_info = {
static const TypeInfo xilinx_enet_data_stream_info = {
.name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
.parent = TYPE_OBJECT,
- .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
+ .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
.class_init = xilinx_enet_data_stream_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SINK },
@@ -1057,7 +1057,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
static const TypeInfo xilinx_enet_control_stream_info = {
.name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
.parent = TYPE_OBJECT,
- .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
+ .instance_size = sizeof(struct XilinxAXIEnetStreamSink),
.class_init = xilinx_enet_control_stream_class_init,
.interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SINK },
--
2.26.2
next prev parent reply other threads:[~2020-09-10 7:09 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 7:01 [PATCH 0/6] misc: Some inclusive terminology changes Philippe Mathieu-Daudé
2020-09-10 7:01 ` [PATCH 1/6] hw/ssi/aspeed_smc: Rename max_slaves as max_devices Philippe Mathieu-Daudé
2020-09-10 7:03 ` Thomas Huth
2020-09-10 9:08 ` Paolo Bonzini
2020-09-10 19:25 ` Cédric Le Goater
2020-09-10 7:01 ` [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink Philippe Mathieu-Daudé
2020-09-10 7:06 ` Philippe Mathieu-Daudé
2020-09-11 7:28 ` Paolo Bonzini
2020-09-11 7:30 ` Edgar E. Iglesias
2020-09-10 7:01 ` [PATCH 3/6] hw/dma/xilinx_axidma: " Philippe Mathieu-Daudé
2020-09-11 7:28 ` Paolo Bonzini
2020-09-11 7:31 ` Edgar E. Iglesias
2020-09-10 7:01 ` Philippe Mathieu-Daudé [this message]
2020-09-11 7:28 ` [PATCH 4/6] hw/net/xilinx_axienet: " Paolo Bonzini
2020-09-11 7:32 ` Edgar E. Iglesias
2020-09-10 7:01 ` [PATCH 5/6] hw/pci-host/q35: Rename PCI 'black hole as '(memory) hole' Philippe Mathieu-Daudé
2020-09-10 7:15 ` Thomas Huth
2020-09-10 7:30 ` Philippe Mathieu-Daudé
2020-09-10 9:11 ` Paolo Bonzini
2020-09-10 9:14 ` Daniel P. Berrangé
2020-09-10 11:36 ` Paolo Bonzini
2020-09-10 7:01 ` [PATCH 6/6] target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken() Philippe Mathieu-Daudé
2020-09-10 7:08 ` Thomas Huth
2020-09-10 9:08 ` Paolo Bonzini
2020-09-10 10:13 ` Laurent Vivier
2020-09-10 7:38 ` [PATCH 0/6] misc: Some inclusive terminology changes Laurent Vivier
2020-09-17 19:02 ` Laurent Vivier
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