From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 18/36] hw/arm: versal-virt: Correct the tx/rx GEM clocks
Date: Mon, 14 Sep 2020 15:06:23 +0100 [thread overview]
Message-ID: <20200914140641.21369-19-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200914140641.21369-1-peter.maydell@linaro.org>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock.
This matches the setup with the fixed-link 100Mbit PHY.
It also avoids the following warnings from the Linux kernel
driver:
eth0: unable to generate target frequency: 125000000 Hz
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200909174647.662864-2-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/xlnx-versal-virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 5a01e856fd9..1f9409eb32a 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -214,7 +214,7 @@ static void fdt_add_gem_nodes(VersalVirt *s)
s->phandle.ethernet_phy[i]);
qemu_fdt_setprop_cells(s->fdt, name, "clocks",
s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
- s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
+ s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
qemu_fdt_setprop(s->fdt, name, "clock-names",
clocknames, sizeof(clocknames));
qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
--
2.20.1
next prev parent reply other threads:[~2020-09-14 14:14 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-14 14:06 [PULL 00/36] target-arm queue Peter Maydell
2020-09-14 14:06 ` [PULL 01/36] hw/misc/a9scu: Do not allow invalid CPU count Peter Maydell
2020-09-14 14:06 ` [PULL 02/36] hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields Peter Maydell
2020-09-14 14:06 ` [PULL 03/36] hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields Peter Maydell
2020-09-14 14:06 ` [PULL 04/36] hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP) Peter Maydell
2020-09-14 14:06 ` [PULL 05/36] hw/timer/armv7m_systick: assert that board code set system_clock_scale Peter Maydell
2020-09-14 14:06 ` [PULL 06/36] decodetree: Improve identifier matching Peter Maydell
2020-09-14 14:06 ` [PULL 07/36] target/arm: Convert Neon 3-same-fp size field to MO_* in decode Peter Maydell
2020-09-14 14:06 ` [PULL 08/36] target/arm: Convert Neon VCVT fp " Peter Maydell
2020-09-14 14:06 ` [PULL 09/36] target/arm: Convert VCMLA, VCADD " Peter Maydell
2020-09-14 14:06 ` [PULL 10/36] target/arm: Remove KVM support for 32-bit Arm hosts Peter Maydell
2020-09-14 14:06 ` [PULL 11/36] target/arm: Remove no-longer-reachable 32-bit KVM code Peter Maydell
2020-09-14 14:06 ` [PULL 12/36] hw/arm/mps2: New board model mps2-an386 Peter Maydell
2020-09-14 14:06 ` [PULL 13/36] hw/arm/mps2: New board model mps2-an500 Peter Maydell
2020-09-14 14:06 ` [PULL 14/36] docs/system/arm/mps2.rst: Make board list consistent Peter Maydell
2020-09-14 14:06 ` [PULL 15/36] Deprecate Unicore32 port Peter Maydell
2020-09-14 14:06 ` [PULL 16/36] Deprecate lm32 port Peter Maydell
2020-09-14 14:06 ` [PULL 17/36] target/arm: Count PMU events when MDCR.SPME is set Peter Maydell
2020-09-14 14:06 ` Peter Maydell [this message]
2020-09-14 14:06 ` [PULL 19/36] hw/misc: Add NPCM7xx System Global Control Registers device model Peter Maydell
2020-09-14 14:06 ` [PULL 20/36] hw/misc: Add NPCM7xx Clock Controller " Peter Maydell
2020-09-14 14:06 ` [PULL 21/36] hw/timer: Add NPCM7xx Timer " Peter Maydell
2020-09-14 14:06 ` [PULL 22/36] hw/arm: Add NPCM730 and NPCM750 SoC models Peter Maydell
2020-09-14 14:06 ` [PULL 23/36] hw/arm: Add two NPCM7xx-based machines Peter Maydell
2020-09-14 14:06 ` [PULL 24/36] roms: Add virtual Boot ROM for NPCM7xx SoCs Peter Maydell
2020-09-14 14:06 ` [PULL 25/36] hw/arm: Load -bios image as a boot ROM for npcm7xx Peter Maydell
2020-09-14 14:06 ` [PULL 26/36] hw/nvram: NPCM7xx OTP device model Peter Maydell
2020-09-14 14:06 ` [PULL 27/36] hw/mem: Stubbed out NPCM7xx Memory Controller model Peter Maydell
2020-09-14 14:06 ` [PULL 28/36] hw/ssi: NPCM7xx Flash Interface Unit device model Peter Maydell
2020-09-14 14:06 ` [PULL 29/36] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj Peter Maydell
2020-09-14 14:06 ` [PULL 30/36] hw/arm/npcm7xx: add board setup stub for CPU and UART clocks Peter Maydell
2020-09-14 14:06 ` [PULL 31/36] docs/system: Add Nuvoton machine documentation Peter Maydell
2020-09-14 14:06 ` [PULL 32/36] tests/acceptance: console boot tests for quanta-gsj Peter Maydell
2020-09-18 13:52 ` Philippe Mathieu-Daudé
2020-09-18 13:56 ` Philippe Mathieu-Daudé
2020-09-18 16:24 ` Havard Skinnemoen
2020-09-14 14:06 ` [PULL 33/36] hw/net/can: Introduce Xilinx ZynqMP CAN controller Peter Maydell
2020-09-14 14:06 ` [PULL 34/36] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers Peter Maydell
2020-09-14 14:06 ` [PULL 35/36] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller Peter Maydell
2020-09-14 14:06 ` [PULL 36/36] MAINTAINERS: Add maintainer entry " Peter Maydell
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