* [PULL v2 00/32] target-arm queue
@ 2020-09-14 15:02 Peter Maydell
2020-09-14 18:22 ` Peter Maydell
0 siblings, 1 reply; 4+ messages in thread
From: Peter Maydell @ 2020-09-14 15:02 UTC (permalink / raw)
To: qemu-devel
For some reason the xilinx can bus patches built in my local config
but not in the merge-test ones; dropped those.
-- PMM
The following changes since commit a68694cd1f3e5448cca814ff39b871f9ebd71ed5:
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging (2020-09-14 12:18:58 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200914-1
for you to fetch changes up to 4fe986dd4480308ecf07200cfbd3c3d494a0f639:
tests/acceptance: console boot tests for quanta-gsj (2020-09-14 14:24:59 +0100)
----------------------------------------------------------------
* hw/misc/a9scu: Do not allow invalid CPU count
* hw/misc/a9scu: Minor cleanups
* hw/timer/armv7m_systick: assert that board code set system_clock_scale
* decodetree: Improve identifier matching
* target/arm: Clean up neon fp insn size field decode
* target/arm: Remove KVM support for 32-bit Arm hosts
* hw/arm/mps2: New board models mps2-an386, mps2-an500
* Deprecate Unicore32 port
* Deprecate lm32 port
* target/arm: Count PMU events when MDCR.SPME is set
* hw/arm: versal-virt: Correct the tx/rx GEM clocks
* New Nuvoton iBMC board models npcm750-evb, quanta-gsj
----------------------------------------------------------------
Aaron Lindsay (1):
target/arm: Count PMU events when MDCR.SPME is set
Edgar E. Iglesias (1):
hw/arm: versal-virt: Correct the tx/rx GEM clocks
Havard Skinnemoen (14):
hw/misc: Add NPCM7xx System Global Control Registers device model
hw/misc: Add NPCM7xx Clock Controller device model
hw/timer: Add NPCM7xx Timer device model
hw/arm: Add NPCM730 and NPCM750 SoC models
hw/arm: Add two NPCM7xx-based machines
roms: Add virtual Boot ROM for NPCM7xx SoCs
hw/arm: Load -bios image as a boot ROM for npcm7xx
hw/nvram: NPCM7xx OTP device model
hw/mem: Stubbed out NPCM7xx Memory Controller model
hw/ssi: NPCM7xx Flash Interface Unit device model
hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj
hw/arm/npcm7xx: add board setup stub for CPU and UART clocks
docs/system: Add Nuvoton machine documentation
tests/acceptance: console boot tests for quanta-gsj
Peter Maydell (11):
hw/timer/armv7m_systick: assert that board code set system_clock_scale
target/arm: Convert Neon 3-same-fp size field to MO_* in decode
target/arm: Convert Neon VCVT fp size field to MO_* in decode
target/arm: Convert VCMLA, VCADD size field to MO_* in decode
target/arm: Remove KVM support for 32-bit Arm hosts
target/arm: Remove no-longer-reachable 32-bit KVM code
hw/arm/mps2: New board model mps2-an386
hw/arm/mps2: New board model mps2-an500
docs/system/arm/mps2.rst: Make board list consistent
Deprecate Unicore32 port
Deprecate lm32 port
Philippe Mathieu-Daudé (4):
hw/misc/a9scu: Do not allow invalid CPU count
hw/misc/a9scu: Simplify setting MemoryRegionOps::valid fields
hw/misc/a9scu: Simplify setting MemoryRegionOps::impl fields
hw/misc/a9scu: Report unimplemented accesses with qemu_log_mask(UNIMP)
Richard Henderson (1):
decodetree: Improve identifier matching
docs/system/arm/mps2.rst | 20 +-
docs/system/arm/nuvoton.rst | 92 +++++
docs/system/deprecated.rst | 32 +-
docs/system/target-arm.rst | 1 +
configure | 2 +-
default-configs/arm-softmmu.mak | 1 +
include/hw/arm/npcm7xx.h | 112 +++++++
include/hw/mem/npcm7xx_mc.h | 36 ++
include/hw/misc/npcm7xx_clk.h | 48 +++
include/hw/misc/npcm7xx_gcr.h | 43 +++
include/hw/nvram/npcm7xx_otp.h | 79 +++++
include/hw/ssi/npcm7xx_fiu.h | 73 ++++
include/hw/timer/npcm7xx_timer.h | 78 +++++
target/arm/kvm-consts.h | 7 -
target/arm/kvm_arm.h | 6 -
target/arm/neon-dp.decode | 18 +-
target/arm/neon-shared.decode | 18 +-
tests/decode/succ_ident1.decode | 7 +
hw/arm/mps2.c | 97 +++++-
hw/arm/npcm7xx.c | 532 +++++++++++++++++++++++++++++
hw/arm/npcm7xx_boards.c | 197 +++++++++++
hw/arm/xlnx-versal-virt.c | 2 +-
hw/mem/npcm7xx_mc.c | 84 +++++
hw/misc/a9scu.c | 59 ++--
hw/misc/npcm7xx_clk.c | 266 +++++++++++++++
hw/misc/npcm7xx_gcr.c | 269 +++++++++++++++
hw/nvram/npcm7xx_otp.c | 440 ++++++++++++++++++++++++
hw/ssi/npcm7xx_fiu.c | 572 +++++++++++++++++++++++++++++++
hw/timer/armv7m_systick.c | 8 +
hw/timer/npcm7xx_timer.c | 543 ++++++++++++++++++++++++++++++
target/arm/cpu.c | 101 +++---
target/arm/helper.c | 2 +-
target/arm/kvm.c | 7 -
target/arm/kvm32.c | 595 ---------------------------------
.gitmodules | 3 +
MAINTAINERS | 10 +
hw/arm/Kconfig | 9 +
hw/arm/meson.build | 1 +
hw/mem/meson.build | 1 +
hw/misc/meson.build | 4 +
hw/misc/trace-events | 8 +
hw/nvram/meson.build | 1 +
hw/ssi/meson.build | 1 +
hw/ssi/trace-events | 11 +
hw/timer/meson.build | 1 +
hw/timer/trace-events | 5 +
pc-bios/README | 6 +
pc-bios/meson.build | 1 +
pc-bios/npcm7xx_bootrom.bin | Bin 0 -> 768 bytes
roms/Makefile | 7 +
roms/vbootrom | 1 +
scripts/decodetree.py | 46 ++-
target/arm/meson.build | 5 +-
target/arm/translate-neon.c.inc | 42 ++-
tests/acceptance/boot_linux_console.py | 83 +++++
55 files changed, 3910 insertions(+), 783 deletions(-)
create mode 100644 docs/system/arm/nuvoton.rst
create mode 100644 include/hw/arm/npcm7xx.h
create mode 100644 include/hw/mem/npcm7xx_mc.h
create mode 100644 include/hw/misc/npcm7xx_clk.h
create mode 100644 include/hw/misc/npcm7xx_gcr.h
create mode 100644 include/hw/nvram/npcm7xx_otp.h
create mode 100644 include/hw/ssi/npcm7xx_fiu.h
create mode 100644 include/hw/timer/npcm7xx_timer.h
create mode 100644 tests/decode/succ_ident1.decode
create mode 100644 hw/arm/npcm7xx.c
create mode 100644 hw/arm/npcm7xx_boards.c
create mode 100644 hw/mem/npcm7xx_mc.c
create mode 100644 hw/misc/npcm7xx_clk.c
create mode 100644 hw/misc/npcm7xx_gcr.c
create mode 100644 hw/nvram/npcm7xx_otp.c
create mode 100644 hw/ssi/npcm7xx_fiu.c
create mode 100644 hw/timer/npcm7xx_timer.c
delete mode 100644 target/arm/kvm32.c
create mode 100644 pc-bios/npcm7xx_bootrom.bin
create mode 160000 roms/vbootrom
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PULL v2 00/32] target-arm queue
2020-09-14 15:02 [PULL v2 00/32] target-arm queue Peter Maydell
@ 2020-09-14 18:22 ` Peter Maydell
0 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2020-09-14 18:22 UTC (permalink / raw)
To: QEMU Developers
On Mon, 14 Sep 2020 at 16:02, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> For some reason the xilinx can bus patches built in my local config
> but not in the merge-test ones; dropped those.
>
> -- PMM
>
> The following changes since commit a68694cd1f3e5448cca814ff39b871f9ebd71ed5:
>
> Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging (2020-09-14 12:18:58 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200914-1
>
> for you to fetch changes up to 4fe986dd4480308ecf07200cfbd3c3d494a0f639:
>
> tests/acceptance: console boot tests for quanta-gsj (2020-09-14 14:24:59 +0100)
>
> ----------------------------------------------------------------
> * hw/misc/a9scu: Do not allow invalid CPU count
> * hw/misc/a9scu: Minor cleanups
> * hw/timer/armv7m_systick: assert that board code set system_clock_scale
> * decodetree: Improve identifier matching
> * target/arm: Clean up neon fp insn size field decode
> * target/arm: Remove KVM support for 32-bit Arm hosts
> * hw/arm/mps2: New board models mps2-an386, mps2-an500
> * Deprecate Unicore32 port
> * Deprecate lm32 port
> * target/arm: Count PMU events when MDCR.SPME is set
> * hw/arm: versal-virt: Correct the tx/rx GEM clocks
> * New Nuvoton iBMC board models npcm750-evb, quanta-gsj
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PULL v2 00/32] target-arm queue
@ 2025-08-30 16:08 Peter Maydell
2025-08-30 23:07 ` Richard Henderson
0 siblings, 1 reply; 4+ messages in thread
From: Peter Maydell @ 2025-08-30 16:08 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson
v2: handle bsd-user in the rename of isar_feature_aa64_atomics
-- PMM
The following changes since commit 4791f22a5f5571cb248b1eddff98630545b3fd3e:
Merge tag 'pull-lu-20250830' of https://gitlab.com/rth7680/qemu into staging (2025-08-30 08:24:48 +1000)
are available in the Git repository at:
https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250830
for you to fetch changes up to 2e27650bddd35477d994a795a3b1cb57c8ed5c76:
hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objects (2025-08-30 16:38:47 +0100)
----------------------------------------------------------------
target-arm queue:
* Implement FEAT_SCTLR2
* Implement FEAT_TCR2
* Implement FEAT_CSSC
* Implement FEAT_LSE128
* Clean up of register field definitions
* Trap PMCR when MDCR_EL2.TPMCR is set
* tests/functional: update aarch64 RME test images
* hw/intc/arm_gicv3_kvm: preserve pending interrupts during cpr
* hw/arm: add static NVDIMMs in device tree
* hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objects
* scripts/kernel-doc: Avoid new Perl precedence warning
* scripts/kernel-doc: Update to kernel's new Python implementation
----------------------------------------------------------------
Gustavo Romero (3):
target/arm: Clean up of register field definitions
target/arm: Implement FEAT_SCTLR2 and enable with -cpu max
target/arm: Implement FEAT_TCR2 and enable with -cpu max
Manos Pitsidianakis (1):
hw/arm: add static NVDIMMs in device tree
Peter Maydell (12):
target/arm: Implement CTZ, CNT, ABS
scripts/kernel-doc: Avoid new Perl precedence warning
docs/sphinx/kerneldoc.py: Handle new LINENO syntax
tests/qtest/libqtest.h: Remove stray space from doc comment
scripts: Import Python kerneldoc from Linux kernel
scripts/kernel-doc: strip QEMU_ from function definitions
scripts/kernel-doc: tweak for QEMU coding standards
scripts/kerneldoc: Switch to the Python kernel-doc script
scripts/kernel-doc: Delete the old Perl kernel-doc script
MAINTAINERS: Put kernel-doc under the "docs build machinery" section
target/arm: Correct condition of aa64_atomics feature function
hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objects
Pierrick Bouvier (2):
tests/functional/test_aarch64_device_passthrough: update image
tests/functional/test_aarch64_rme: update image
Richard Henderson (12):
target/arm: Add feature predicate for FEAT_CSSC
target/arm: Implement MIN/MAX (immediate)
target/arm: Implement MIN/MAX (register)
target/arm: Split out gen_wrap2_i32 helper
target/arm: Enable FEAT_CSSC for -cpu max
qemu/atomic: Finish renaming atomic128-cas.h headers
qemu/atomic: Add atomic16 primitives for xchg, fetch_and, fetch_or
accel/tcg: Add cpu_atomic_*_mmu for 16-byte xchg, fetch_and, fetch_or
tcg: Add tcg_gen_atomic_{xchg,fetch_and,fetch_or}_i128
target/arm: Rename isar_feature_aa64_atomics
target/arm: Implement FEAT_LSE128
target/arm: Enable FEAT_LSE128 for -cpu max
Smail AIDER (1):
target/arm: Trap PMCR when MDCR_EL2.TPMCR is set
Steve Sistare (1):
hw/intc/arm_gicv3_kvm: preserve pending interrupts during cpr
MAINTAINERS | 3 +
docs/conf.py | 4 +-
docs/sphinx/kerneldoc.py | 7 +-
docs/system/arm/emulation.rst | 4 +
accel/tcg/atomic_template.h | 80 +-
accel/tcg/tcg-runtime.h | 12 +
bsd-user/aarch64/target_arch_elf.h | 2 +-
host/include/aarch64/host/atomic128-cas.h | 45 -
include/accel/tcg/cpu-ldst-common.h | 13 +-
include/hw/arm/stm32f205_soc.h | 2 +-
include/hw/intc/arm_gicv3_common.h | 3 +
include/tcg/tcg-op-common.h | 7 +
include/tcg/tcg-op.h | 3 +
target/arm/cpu-features.h | 24 +-
target/arm/cpu.h | 17 +
target/arm/internals.h | 28 +-
tests/qtest/libqtest.h | 2 +-
host/include/aarch64/host/atomic128-cas.h.inc | 102 +
host/include/generic/host/atomic128-cas.h.inc | 96 +
target/arm/tcg/a64.decode | 26 +
hw/arm/boot.c | 42 +
hw/arm/stm32f205_soc.c | 10 +-
hw/arm/virt.c | 8 +-
hw/intc/arm_gicv3_kvm.c | 15 +
linux-user/aarch64/elfload.c | 4 +-
target/arm/cpregs-pmu.c | 34 +-
target/arm/cpu.c | 6 +
target/arm/helper.c | 168 +-
target/arm/ptw.c | 8 +-
target/arm/tcg/cpu64.c | 9 +-
target/arm/tcg/translate-a64.c | 195 +-
tcg/tcg-op-ldst.c | 97 +-
accel/tcg/atomic_common.c.inc | 9 +
.editorconfig | 2 +-
scripts/kernel-doc | 2442 --------------------
scripts/kernel-doc.py | 325 +++
scripts/lib/kdoc/kdoc_files.py | 291 +++
scripts/lib/kdoc/kdoc_item.py | 42 +
scripts/lib/kdoc/kdoc_output.py | 749 ++++++
scripts/lib/kdoc/kdoc_parser.py | 1670 +++++++++++++
scripts/lib/kdoc/kdoc_re.py | 270 +++
.../functional/aarch64/test_device_passthrough.py | 27 +-
tests/functional/aarch64/test_rme_sbsaref.py | 64 +-
tests/functional/aarch64/test_rme_virt.py | 85 +-
44 files changed, 4389 insertions(+), 2663 deletions(-)
delete mode 100644 host/include/aarch64/host/atomic128-cas.h
create mode 100644 host/include/aarch64/host/atomic128-cas.h.inc
delete mode 100755 scripts/kernel-doc
create mode 100755 scripts/kernel-doc.py
create mode 100644 scripts/lib/kdoc/kdoc_files.py
create mode 100644 scripts/lib/kdoc/kdoc_item.py
create mode 100644 scripts/lib/kdoc/kdoc_output.py
create mode 100644 scripts/lib/kdoc/kdoc_parser.py
create mode 100644 scripts/lib/kdoc/kdoc_re.py
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PULL v2 00/32] target-arm queue
2025-08-30 16:08 Peter Maydell
@ 2025-08-30 23:07 ` Richard Henderson
0 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2025-08-30 23:07 UTC (permalink / raw)
To: Peter Maydell, qemu-devel
On 8/31/25 02:08, Peter Maydell wrote:
> v2: handle bsd-user in the rename of isar_feature_aa64_atomics
>
> -- PMM
>
> The following changes since commit 4791f22a5f5571cb248b1eddff98630545b3fd3e:
>
> Merge tag 'pull-lu-20250830' ofhttps://gitlab.com/rth7680/qemu into staging (2025-08-30 08:24:48 +1000)
>
> are available in the Git repository at:
>
> https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20250830
>
> for you to fetch changes up to 2e27650bddd35477d994a795a3b1cb57c8ed5c76:
>
> hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objects (2025-08-30 16:38:47 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Implement FEAT_SCTLR2
> * Implement FEAT_TCR2
> * Implement FEAT_CSSC
> * Implement FEAT_LSE128
> * Clean up of register field definitions
> * Trap PMCR when MDCR_EL2.TPMCR is set
> * tests/functional: update aarch64 RME test images
> * hw/intc/arm_gicv3_kvm: preserve pending interrupts during cpr
> * hw/arm: add static NVDIMMs in device tree
> * hw/arm/stm32f205_soc: Don't leak TYPE_OR_IRQ objects
> * scripts/kernel-doc: Avoid new Perl precedence warning
> * scripts/kernel-doc: Update to kernel's new Python implementation
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate.
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2025-08-30 23:08 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-09-14 15:02 [PULL v2 00/32] target-arm queue Peter Maydell
2020-09-14 18:22 ` Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2025-08-30 16:08 Peter Maydell
2025-08-30 23:07 ` Richard Henderson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).