From: "Michael S. Tsirkin" <mst@redhat.com>
To: Gerd Hoffmann <kraxel@redhat.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>,
Sergio Lopez <slp@redhat.com>,
qemu-devel@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <rth@twiddle.net>
Subject: Re: [PATCH 2/2] microvm: add pcie support
Date: Mon, 21 Sep 2020 08:39:29 -0400 [thread overview]
Message-ID: <20200921083751-mutt-send-email-mst@kernel.org> (raw)
In-Reply-To: <20200921113347.mrdrxwskh5dzkosv@sirius.home.kraxel.org>
On Mon, Sep 21, 2020 at 01:33:47PM +0200, Gerd Hoffmann wrote:
> On Fri, Sep 18, 2020 at 08:36:14AM -0400, Michael S. Tsirkin wrote:
> > On Fri, Sep 18, 2020 at 02:19:11PM +0200, Gerd Hoffmann wrote:
> > > Uses the existing gpex device which is also used as pcie host bridge on
> > > arm/aarch64. For now only a 32bit mmio window and no ioport support.
> > >
> > > It is disabled by default, use "-machine microvm,pcie=on" to enable.
> > > ACPI support must be enabled too because the bus is declared in the
> > > DSDT table.
> > >
> > > Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> >
> > Can we do the reverse and only support a 64 bit window?
> > 32 bit resources are a pain, we support them on x86 for purposes
> > of legacy guests ...
>
> 32bit pci bars too, right?
> I suspect we can't that easily take away the 32bit window ...
>
> take care,
> Gerd
Yes I forgot, in their wisdom pci sig declared that non prefetcheable
memory windows in bridges are always 32 bit :(
--
MST
prev parent reply other threads:[~2020-09-21 12:40 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-18 12:19 [PATCH 0/2] microvm: add pcie support Gerd Hoffmann
2020-09-18 12:19 ` [PATCH 1/2] microvm: add irq table Gerd Hoffmann
2020-09-18 12:19 ` [PATCH 2/2] microvm: add pcie support Gerd Hoffmann
2020-09-18 12:36 ` Michael S. Tsirkin
2020-09-21 11:33 ` Gerd Hoffmann
2020-09-21 12:39 ` Michael S. Tsirkin [this message]
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