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[79.179.71.128]) by smtp.gmail.com with ESMTPSA id d19sm2131421wmd.0.2020.09.23.23.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Sep 2020 23:17:12 -0700 (PDT) Date: Thu, 24 Sep 2020 02:17:10 -0400 From: "Michael S. Tsirkin" To: Julia Suvorova Subject: Re: [PATCH] hw/i386/acpi-build: Explain bits in OSC method Message-ID: <20200924021247-mutt-send-email-mst@kernel.org> References: <20200923075514.110478-1-jusual@redhat.com> MIME-Version: 1.0 In-Reply-To: <20200923075514.110478-1-jusual@redhat.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=63.128.21.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/24 01:10:00 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.228, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Sep 23, 2020 at 09:55:14AM +0200, Julia Suvorova wrote: > Provide a better explanation for the enabled bits in the _OSC control > field. Base it on the latest specification due to new bits 5 and 6. > > Signed-off-by: Julia Suvorova > --- > hw/i386/acpi-build.h | 11 +++++++++++ > hw/i386/acpi-build.c | 7 ++++++- > 2 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h > index 74df5fc612..bb5269d162 100644 > --- a/hw/i386/acpi-build.h > +++ b/hw/i386/acpi-build.h > @@ -5,6 +5,17 @@ > > extern const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio; > > +/* PCI Firmware Specification 3.2, Table 4-5 */ > +typedef enum { > + ACPI_OSC_NATIVE_HP_EN = 0, > + ACPI_OSC_SHPC_EN = 1, > + ACPI_OSC_PME_EN = 2, > + ACPI_OSC_AER_EN = 3, > + ACPI_OSC_PCIE_CAP_EN = 4, > + ACPI_OSC_LTR_EN = 5, > + ACPI_OSC_ALLONES_INVALID = 6, > +} AcpiOSCField; > + > void acpi_setup(void); > > #endif > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 0e0535d2e3..b08f005a35 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -1417,6 +1417,7 @@ static Aml *build_q35_osc_method(void) > Aml *method; > Aml *a_cwd1 = aml_name("CDW1"); > Aml *a_ctrl = aml_local(0); > + unsigned osc_ctrl; > > method = aml_method("_OSC", 4, AML_NOTSERIALIZED); > aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); > @@ -1432,7 +1433,11 @@ static Aml *build_q35_osc_method(void) > * Always allow native PME, AER (no dependencies) > * Allow SHPC (PCI bridges can have SHPC controller) > */ > - aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); > + osc_ctrl = BIT(ACPI_OSC_PME_EN) | BIT(ACPI_OSC_AER_EN) | > + BIT(ACPI_OSC_PCIE_CAP_EN) | BIT(ACPI_OSC_NATIVE_HP_EN) | > + BIT(ACPI_OSC_SHPC_EN); > + > + aml_append(if_ctx, aml_and(a_ctrl, aml_int(osc_ctrl), a_ctrl)); Now the comment above somewhat duplicates the enums. And decoding what does each value mean is a head scratcher. As long as there's a single use, we prefer comments to an enum, they can match spec exactly: BIT(0) /* PCI Express Native Hotplug control */ | BIT(4) /* SHPC Native Hotplug control */ | etc ... > if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); > /* Unknown revision */ > -- > 2.25.4