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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-stable@nongnu.org
Subject: [PULL 08/11] tcg: Fix generation of dupi_vec for 32-bit host
Date: Thu,  8 Oct 2020 07:56:56 -0500	[thread overview]
Message-ID: <20201008125659.49857-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20201008125659.49857-1-richard.henderson@linaro.org>

The definition of INDEX_op_dupi_vec is that it operates on
units of tcg_target_ulong -- in this case 32 bits.  It does
not work to use this for a uint64_t value that happens to be
small enough to fit in tcg_target_ulong.

Fixes: d2fd745fe8b
Fixes: db432672dc5
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tcg-op-vec.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index ed6fb55fe1..cdbf11c573 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -252,10 +252,10 @@ TCGv_vec tcg_const_ones_vec_matching(TCGv_vec m)
 
 void tcg_gen_dup64i_vec(TCGv_vec r, uint64_t a)
 {
-    if (TCG_TARGET_REG_BITS == 32 && a == deposit64(a, 32, 32, a)) {
-        do_dupi_vec(r, MO_32, a);
-    } else if (TCG_TARGET_REG_BITS == 64 || a == (uint64_t)(int32_t)a) {
+    if (TCG_TARGET_REG_BITS == 64) {
         do_dupi_vec(r, MO_64, a);
+    } else if (a == dup_const(MO_32, a)) {
+        do_dupi_vec(r, MO_32, a);
     } else {
         TCGv_i64 c = tcg_const_i64(a);
         tcg_gen_dup_i64_vec(MO_64, r, c);
@@ -280,7 +280,11 @@ void tcg_gen_dup8i_vec(TCGv_vec r, uint32_t a)
 
 void tcg_gen_dupi_vec(unsigned vece, TCGv_vec r, uint64_t a)
 {
-    do_dupi_vec(r, MO_REG, dup_const(vece, a));
+    if (vece == MO_64) {
+        tcg_gen_dup64i_vec(r, a);
+    } else {
+        do_dupi_vec(r, MO_REG, dup_const(vece, a));
+    }
 }
 
 void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec r, TCGv_i64 a)
-- 
2.25.1



  parent reply	other threads:[~2020-10-08 13:03 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-08 12:56 [PULL 00/11] tcg patch queue Richard Henderson
2020-10-08 12:56 ` [PULL 01/11] tcg: Adjust simd_desc size encoding Richard Henderson
2020-10-08 12:56 ` [PULL 02/11] tcg: Drop union from TCGArgConstraint Richard Henderson
2020-10-08 12:56 ` [PULL 03/11] tcg: Move sorted_args into TCGArgConstraint.sort_index Richard Henderson
2020-10-08 12:56 ` [PULL 04/11] tcg: Remove TCG_CT_REG Richard Henderson
2020-10-08 12:56 ` [PULL 05/11] tcg: Move some TCG_CT_* bits to TCGArgConstraint bitfields Richard Henderson
2020-10-08 12:56 ` [PULL 06/11] tcg: Remove TCGOpDef.used Richard Henderson
2020-10-08 12:56 ` [PULL 07/11] tcg/i386: Fix dupi for avx2 32-bit hosts Richard Henderson
2020-10-08 12:56 ` Richard Henderson [this message]
2020-10-08 12:56 ` [PULL 09/11] tcg/optimize: Fold dup2_vec Richard Henderson
2020-10-08 12:56 ` [PULL 10/11] tcg: Remove TCG_TARGET_HAS_cmp_vec Richard Henderson
2020-10-08 12:56 ` [PULL 11/11] accel/tcg: Fix computing of is_write for MIPS Richard Henderson
2020-10-08 13:36 ` [PULL 00/11] tcg patch queue no-reply
2020-10-08 18:13 ` Peter Maydell

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