From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org, Victor Kamensky <kamensky@cisco.com>
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Khem Raj" <raj.khem@gmail.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aleksandar Markovic" <aleksandar.qemu.devel@gmail.com>,
"Richard Purdie" <richard.purdie@linuxfoundation.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Richard Henderson" <rth@twiddle.net>
Subject: [RFC PATCH 1/3] target/mips: Make cpu_mips_realize_env() propagate Error
Date: Tue, 13 Oct 2020 15:25:33 +0200 [thread overview]
Message-ID: <20201013132535.3599453-2-f4bug@amsat.org> (raw)
In-Reply-To: <20201013132535.3599453-1-f4bug@amsat.org>
To be able to propagate error to our caller, make
cpu_mips_realize_env() take an Error argument and
return a boolean value indicating an error is set or
not, following the example documented since commit
e3fe3988d7 ("error: Document Error API usage rules").
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 10 +++++++++-
target/mips/cpu.c | 4 +++-
target/mips/translate.c | 4 +++-
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 7f159a9230c..c2b2e79c515 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -206,7 +206,15 @@ void mips_tcg_init(void);
/* TODO QOM'ify CPU reset and remove */
void cpu_state_reset(CPUMIPSState *s);
-void cpu_mips_realize_env(CPUMIPSState *env);
+
+/**
+ * cpu_mips_realize_env: Realize CPUMIPSState
+ * @env: CPUMIPSState object
+ * @errp: pointer to error object
+ * On success, return %true.
+ * On failure, store an error through @errp and return %false.
+ */
+bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp);
/* cp0_timer.c */
uint32_t cpu_mips_get_random(CPUMIPSState *env);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index e86cd065483..117c748345e 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -147,7 +147,9 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
return;
}
- cpu_mips_realize_env(&cpu->env);
+ if (!cpu_mips_realize_env(&cpu->env, errp)) {
+ return;
+ }
cpu_reset(cs);
qemu_init_vcpu(cs);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 398edf72898..4c9b6216321 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31316,7 +31316,7 @@ void mips_tcg_init(void)
#include "translate_init.c.inc"
-void cpu_mips_realize_env(CPUMIPSState *env)
+bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp)
{
env->exception_base = (int32_t)0xBFC00000;
@@ -31325,6 +31325,8 @@ void cpu_mips_realize_env(CPUMIPSState *env)
#endif
fpu_init(env, env->cpu_model);
mvp_init(env, env->cpu_model);
+
+ return true;
}
bool cpu_supports_cps_smp(const char *cpu_type)
--
2.26.2
next prev parent reply other threads:[~2020-10-13 13:28 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-13 13:25 [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property Philippe Mathieu-Daudé
2020-10-13 13:25 ` Philippe Mathieu-Daudé [this message]
2020-10-13 13:25 ` [RFC PATCH 2/3] target/mips: Store number of TLB entries in CPUMIPSState Philippe Mathieu-Daudé
2020-10-13 13:25 ` [RFC PATCH 3/3] target/mips: Make the number of TLB entries a CPU property Philippe Mathieu-Daudé
2020-10-14 10:20 ` Jiaxun Yang
2020-10-14 10:54 ` Philippe Mathieu-Daudé
2020-10-13 23:11 ` [RFC PATCH 0/3] " Richard Henderson
2020-10-14 2:22 ` Richard Henderson
2020-10-14 3:21 ` Victor Kamensky (kamensky) via
2020-10-14 7:26 ` Richard Purdie
2020-10-14 1:36 ` Victor Kamensky (kamensky)
2020-10-14 7:14 ` Richard Purdie
2020-10-14 14:53 ` Philippe Mathieu-Daudé
2020-10-14 20:20 ` Victor Kamensky (kamensky) via
2020-10-14 20:53 ` Khem Raj
2020-10-15 18:56 ` Victor Kamensky (kamensky) via
2020-10-16 17:19 ` Richard Henderson
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