From: Alexey Baturo <baturo.alexey@gmail.com>
Cc: baturo.alexey@gmail.com,
"open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
"open list:All patches CC here" <qemu-devel@nongnu.org>,
space.monkey.delivers@gmail.com,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs
Date: Wed, 14 Oct 2020 20:01:57 +0300 [thread overview]
Message-ID: <20201014170159.26932-4-space.monkey.delivers@gmail.com> (raw)
In-Reply-To: <20201014170159.26932-1-space.monkey.delivers@gmail.com>
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
---
target/riscv/cpu.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d63031eb08..8f8ee4d29c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -255,6 +255,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
}
+ if (riscv_has_ext(env, RVH)) {
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mmte ", env->mmte);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmbase ", env->upmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmbase ", env->spmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmbase ", env->mpmbase);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "upmmask ", env->upmmask);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "spmmask ", env->spmmask);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mpmmask ", env->mpmmask);
+ }
#endif
for (i = 0; i < 32; i++) {
--
2.20.1
next prev parent reply other threads:[~2020-10-14 17:03 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20201014170159.26932-1-space.monkey.delivers@gmail.com>
2020-10-14 17:01 ` [PATCH 1/5] [RISCV_PM] Add J-extension into RISC-V Alexey Baturo
2020-10-14 17:01 ` [PATCH 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode Alexey Baturo
2020-10-14 17:01 ` Alexey Baturo [this message]
2020-10-14 18:41 ` [PATCH 3/5] [RISCV_PM] Print new PM CSRs in QEMU logs Richard Henderson
2020-10-14 20:01 ` Alexey Baturo
2020-10-14 17:01 ` [PATCH 4/5] [RISCV_PM] Add address masking functions required for RISC-V Pointer Masking extension Alexey Baturo
2020-10-14 19:19 ` Richard Henderson
2020-10-14 20:10 ` Alexey Baturo
2020-10-15 15:23 ` Alexey Baturo
2020-10-14 17:01 ` [PATCH 5/5] [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions Alexey Baturo
2020-10-14 19:24 ` Richard Henderson
2020-10-14 20:13 ` Alexey Baturo
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