[RFC PATCH v2 0/4] target/mips: Make the number of TLB entries a CPU property

[RFC PATCH v2 0/4] target/mips: Make the number of TLB entries a CPU property

[Philippe Mathieu-Daudé]

Yocto developers have expressed interest in running MIPS32
CPU with preset number of TLB:
https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html

Help them by allowing to set the TLB entries from a preset array
of valid hardware values.

Please test/review,

Phil.

Philippe Mathieu-Daudé (4):
  target/mips: Make cpu_mips_realize_env() propagate Error
  target/mips: Store number of TLB entries in CPUMIPSState
  target/mips: Make the number of TLB entries a CPU property
  target/mips: Allow using the 34Kf with 16/32/64 preset TLB entries

 target/mips/cpu.h                |  1 +
 target/mips/internal.h           | 11 ++++++++-
 target/mips/cpu.c                | 12 ++++++++--
 target/mips/translate.c          | 39 ++++++++++++++++++++++++++++++--
 target/mips/translate_init.c.inc |  3 ++-
 5 files changed, 60 insertions(+), 6 deletions(-)

-- 
2.26.2

[RFC PATCH v2 1/4] target/mips: Make cpu_mips_realize_env() propagate Error

[Philippe Mathieu-Daudé]

To be able to propagate error to our caller, make
cpu_mips_realize_env() take an Error argument and
return a boolean value indicating an error is set or
not, following the example documented since commit
e3fe3988d7 ("error: Document Error API usage rules").

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/internal.h  | 10 +++++++++-
 target/mips/cpu.c       |  4 +++-
 target/mips/translate.c |  4 +++-
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index 7f159a9230c..c2b2e79c515 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -206,7 +206,15 @@ void mips_tcg_init(void);
 
 /* TODO QOM'ify CPU reset and remove */
 void cpu_state_reset(CPUMIPSState *s);
-void cpu_mips_realize_env(CPUMIPSState *env);
+
+/**
+ * cpu_mips_realize_env: Realize CPUMIPSState
+ * @env: CPUMIPSState object
+ * @errp: pointer to error object
+ * On success, return %true.
+ * On failure, store an error through @errp and return %false.
+ */
+bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp);
 
 /* cp0_timer.c */
 uint32_t cpu_mips_get_random(CPUMIPSState *env);
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index e86cd065483..117c748345e 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -147,7 +147,9 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
         return;
     }
 
-    cpu_mips_realize_env(&cpu->env);
+    if (!cpu_mips_realize_env(&cpu->env, errp)) {
+        return;
+    }
 
     cpu_reset(cs);
     qemu_init_vcpu(cs);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 398edf72898..4c9b6216321 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31316,7 +31316,7 @@ void mips_tcg_init(void)
 
 #include "translate_init.c.inc"
 
-void cpu_mips_realize_env(CPUMIPSState *env)
+bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp)
 {
     env->exception_base = (int32_t)0xBFC00000;
 
@@ -31325,6 +31325,8 @@ void cpu_mips_realize_env(CPUMIPSState *env)
 #endif
     fpu_init(env, env->cpu_model);
     mvp_init(env, env->cpu_model);
+
+    return true;
 }
 
 bool cpu_supports_cps_smp(const char *cpu_type)
-- 
2.26.2

[RFC PATCH v2 2/4] target/mips: Store number of TLB entries in CPUMIPSState

[Philippe Mathieu-Daudé]

As we want to make the number of TLB entries configurable,
store it in CPUMIPSState. Introduce the init_tlb_entries()
helper which initializes it from the CP0C1_MMU config content.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/cpu.h                |  1 +
 target/mips/translate.c          | 13 ++++++++++++-
 target/mips/translate_init.c.inc |  2 +-
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7cf7f5239f7..b84e9a8fcae 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1140,6 +1140,7 @@ struct CPUMIPSState {
 #endif
 
     const mips_def_t *cpu_model;
+    uint8_t tlb_entries;
     void *irq[8];
     QEMUTimer *timer; /* Internal timer */
     struct MIPSITUState *itu;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4c9b6216321..698bcee8915 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31316,8 +31316,18 @@ void mips_tcg_init(void)
 
 #include "translate_init.c.inc"
 
+static bool init_tlb_entries(CPUMIPSState *env, Error **errp)
+{
+    env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1, CP0C1_MMU, 6);
+
+    return true;
+}
+
 bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp)
 {
+    if (!init_tlb_entries(env, errp)) {
+        return false;
+    }
     env->exception_base = (int32_t)0xBFC00000;
 
 #ifndef CONFIG_USER_ONLY
@@ -31357,7 +31367,8 @@ void cpu_state_reset(CPUMIPSState *env)
 #ifdef TARGET_WORDS_BIGENDIAN
     env->CP0_Config0 |= (1 << CP0C0_BE);
 #endif
-    env->CP0_Config1 = env->cpu_model->CP0_Config1;
+    env->CP0_Config1 = deposit32(env->cpu_model->CP0_Config1, CP0C1_MMU, 6,
+                                 env->tlb_entries - 1);
     env->CP0_Config2 = env->cpu_model->CP0_Config2;
     env->CP0_Config3 = env->cpu_model->CP0_Config3;
     env->CP0_Config4 = env->cpu_model->CP0_Config4;
diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 637caccd890..a426463c434 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -946,7 +946,7 @@ static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 
 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
 {
-    env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+    env->tlb->nb_tlb = env->tlb_entries;
     env->tlb->map_address = &r4k_map_address;
     env->tlb->helper_tlbwi = r4k_helper_tlbwi;
     env->tlb->helper_tlbwr = r4k_helper_tlbwr;
-- 
2.26.2

[RFC PATCH v2 3/4] target/mips: Make the number of TLB entries a CPU property

[Philippe Mathieu-Daudé]

Allow selecting the number of TLB entries from a preset array.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/internal.h  |  1 +
 target/mips/cpu.c       |  8 +++++++-
 target/mips/translate.c | 26 ++++++++++++++++++++++++--
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/target/mips/internal.h b/target/mips/internal.h
index c2b2e79c515..34f82c6e842 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -29,6 +29,7 @@ struct mips_def_t {
     int32_t CP0_PRid;
     int32_t CP0_Config0;
     int32_t CP0_Config1;
+    const unsigned *CP0_Config1_MMU_preset;
     int32_t CP0_Config2;
     int32_t CP0_Config3;
     int32_t CP0_Config4;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 117c748345e..da31831368b 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -26,7 +26,7 @@
 #include "qemu/module.h"
 #include "sysemu/kvm.h"
 #include "exec/exec-all.h"
-
+#include "hw/qdev-properties.h"
 
 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
 {
@@ -183,6 +183,11 @@ static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
     return oc;
 }
 
+static Property mips_cpu_properties[] = {
+    DEFINE_PROP_UINT8("tlb-entries", MIPSCPU, env.tlb_entries, 0),
+    DEFINE_PROP_END_OF_LIST()
+};
+
 static void mips_cpu_class_init(ObjectClass *c, void *data)
 {
     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
@@ -192,6 +197,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
     device_class_set_parent_realize(dc, mips_cpu_realizefn,
                                     &mcc->parent_realize);
     device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
+    device_class_set_props(dc, mips_cpu_properties);
 
     cc->class_by_name = mips_cpu_class_by_name;
     cc->has_work = mips_cpu_has_work;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 698bcee8915..f5815160fb6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -39,6 +39,7 @@
 #include "exec/translator.h"
 #include "exec/log.h"
 #include "qemu/qemu-print.h"
+#include "qapi/error.h"
 
 #define MIPS_DEBUG_DISAS 0
 
@@ -31318,9 +31319,30 @@ void mips_tcg_init(void)
 
 static bool init_tlb_entries(CPUMIPSState *env, Error **errp)
 {
-    env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1, CP0C1_MMU, 6);
+    const unsigned *preset = env->cpu_model->CP0_Config1_MMU_preset;
+    bool valid = false;
 
-    return true;
+    if (!env->tlb_entries) {
+        env->tlb_entries = 1 + extract32(env->cpu_model->CP0_Config1,
+                                         CP0C1_MMU, 6);
+        return true;
+    }
+    if (!preset) {
+        error_setg(errp, "Property 'tlb-entries' not modifiable for this CPU");
+        return false;
+    }
+    while (!valid && *preset) {
+        if (*preset == env->tlb_entries) {
+            valid = true;
+            break;
+        }
+        preset++;
+    }
+    if (!valid) {
+        error_setg(errp, "Invalid value '%u' for property 'tlb-entries'",
+                   env->tlb_entries);
+    }
+    return valid;
 }
 
 bool cpu_mips_realize_env(CPUMIPSState *env, Error **errp)
-- 
2.26.2

[RFC PATCH v2 4/4] target/mips: Allow using the 34Kf with 16/32/64 preset TLB entries

[Philippe Mathieu-Daudé]

Per "MIPS32 34K Processor Core Family Software User's Manual,
Revision 01.13" page 8 in "Joint TLB (JTLB)" section:

  "The JTLB is a fully associative TLB cache containing 16, 32,
   or 64-dual-entries mapping up to 128 virtual pages to their
   corresponding physical addresses."

Add these values to the CP0_Config1_MMU_preset array.

Example to use a 34Kf cpu with preset 64 TLB:

  $ qemu-system-mipsel -cpu 34Kf,tlb-entries=64 ...

This is helpful for developers of the Yocto Project [*]:

  Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit
  MIPS CI loop. It was observed that in this case CI test execution
  time was almost twice longer than 64bit MIPS variant that runs
  under MIPS64R2-generic model. It was investigated and concluded
  that the difference in number of TLBs 16 in 34Kf case vs 64 in
  MIPS64R2-generic is responsible for most of CI real time execution
  difference. Because with 16 TLBs linux user-land trashes TLB more
  and it needs to execute more instructions in TLB refill handler
  calls, as result it runs much longer.

[*] https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html

Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
Reported-by: Victor Kamensky <kamensky@cisco.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate_init.c.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index a426463c434..02500e696f4 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -258,6 +258,7 @@ const mips_def_t mips_defs[] =
                        (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
                        (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
                        (1 << CP0C1_CA),
+        .CP0_Config1_MMU_preset = (const unsigned[]){16, 32, 64, 0},
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
                        (1 << CP0C3_DSPP),
-- 
2.26.2