From: Ivan Griffin <ivan.griffin@emdalo.com>
To: Bin Meng <bin.meng@windriver.com>
Cc: qemu-trivial@nongnu.org, qemu-riscv@nongnu.org,
qemu-devel@nongnu.org, ivan.griffin@emdalo.com
Subject: [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry
Date: Fri, 16 Oct 2020 13:37:37 +0100 [thread overview]
Message-ID: <20201016123737.8118-1-ivan.griffin@emdalo.com> (raw)
Adding the PolarFire SoC IOSCBCTRL memory region to prevent QEMU
reporting a STORE/AMO Access Fault.
This region is used by the PolarFire SoC port of U-Boot to
interact with the FPGA system controller.
Signed-off-by: Ivan Griffin <ivan.griffin@emdalo.com>
---
hw/riscv/microchip_pfsoc.c | 6 ++++++
include/hw/riscv/microchip_pfsoc.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4627179cd3..20e1496e3e 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -97,6 +97,7 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
+ [MICROCHIP_PFSOC_IOSCB_CTRL] = { 0x37020000, 0x1000 },
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
[MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
};
@@ -341,6 +342,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
+
+ /* IOSCBCTRL */
+ create_unimplemented_device("microchip.pfsoc.ioscb.ctrl",
+ memmap[MICROCHIP_PFSOC_IOSCB_CTRL].base,
+ memmap[MICROCHIP_PFSOC_IOSCB_CTRL].size);
}
static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 8bfc7e1a85..3f1874b162 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -95,6 +95,7 @@ enum {
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
MICROCHIP_PFSOC_IOSCB_CFG,
+ MICROCHIP_PFSOC_IOSCB_CTRL,
MICROCHIP_PFSOC_DRAM,
};
--
2.17.1
next reply other threads:[~2020-10-16 15:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-16 12:37 Ivan Griffin [this message]
2020-10-16 16:07 ` [PATCH] hw/riscv: microchip_pfsoc: IOSCBCTRL memmap entry Alistair Francis
2020-10-16 16:31 ` Ivan Griffin
2020-10-16 16:24 ` Alistair Francis
2020-10-16 17:10 ` [PATCH v2] " Ivan Griffin
2020-10-16 17:37 ` Alistair Francis
2020-10-19 1:57 ` Bin Meng
2020-10-27 20:56 ` Alistair Francis
2020-10-19 2:05 ` [PATCH] " Bin Meng
2020-10-19 8:17 ` Ivan Griffin
2020-10-19 8:38 ` Bin Meng
2020-10-19 8:42 ` Ivan Griffin
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