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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y14sm309918wma.48.2020.10.19.08.13.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2020 08:13:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 00/10] target/arm: Various v8.1M minor features Date: Mon, 19 Oct 2020 16:12:51 +0100 Message-Id: <20201019151301.2046-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patchseries implements various minor v8.1M new features, notably the branch-future and low-overhead-loop extensions. (None of this will get enabled until we have enough to implement a CPU model which has v8.1M, which will be the Cortex-M55, but as usual we can get stuff into the tree gradually.) Changes v1->v2: * added missing check that rm!=13 for CSEL decode * folded in gen_jmp_tb() fixup for DLS/WLS/LE patch * reversed sense of branch in trans_WLS * reworked set_fpscr changes as suggested by RTH * provide an env->v7m.ltpsize now (always 4 until MVE implemented, but it avoids code changes later) Unreviewed patches: 2, 7, 9, 10 thanks -- PMM Peter Maydell (10): decodetree: Fix codegen for non-overlapping group inside overlapping group target/arm: Implement v8.1M NOCP handling target/arm: Implement v8.1M conditional-select insns target/arm: Make the t32 insn[25:23]=111 group non-overlapping target/arm: Don't allow BLX imm for M-profile target/arm: Implement v8.1M branch-future insns (as NOPs) target/arm: Implement v8.1M low-overhead-loop instructions target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16 target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension target/arm/cpu.h | 8 ++ target/arm/m-nocp.decode | 10 +- target/arm/t32.decode | 50 ++++++--- target/arm/cpu.c | 38 +++++-- target/arm/translate.c | 181 ++++++++++++++++++++++++++++++++- target/arm/vfp_helper.c | 53 ++++++---- scripts/decodetree.py | 2 +- target/arm/translate-vfp.c.inc | 17 +++- 8 files changed, 305 insertions(+), 54 deletions(-) -- 2.20.1