From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>,
Atish Patra <atish.patra@wdc.com>,
Anup Patel <anup.patel@wdc.com>,
Ivan Griffin <ivan.griffin@emdalo.com>
Subject: [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module
Date: Tue, 27 Oct 2020 22:17:37 +0800 [thread overview]
Message-ID: <20201027141740.18336-7-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20201027141740.18336-1-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
Previously SYSREG was created as an unimplemented device. Now that
we have a simple SYSREG module, connect it.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/Kconfig | 1 +
hw/riscv/microchip_pfsoc.c | 9 ++++++---
include/hw/riscv/microchip_pfsoc.h | 2 ++
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 8f043e38e0..facb0cbacc 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -7,6 +7,7 @@ config MICROCHIP_PFSOC
select MCHP_PFSOC_DMC
select MCHP_PFSOC_IOSCB
select MCHP_PFSOC_MMUART
+ select MCHP_PFSOC_SYSREG
select MSI_NONBROKEN
select SIFIVE_CLINT
select SIFIVE_PDMA
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 05fb5004a1..69117c6000 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -135,6 +135,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma-controller", &s->dma,
TYPE_SIFIVE_PDMA);
+ object_initialize_child(obj, "sysreg", &s->sysreg,
+ TYPE_MCHP_PFSOC_SYSREG);
+
object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
@@ -262,9 +265,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
}
/* SYSREG */
- create_unimplemented_device("microchip.pfsoc.sysreg",
- memmap[MICROCHIP_PFSOC_SYSREG].base,
- memmap[MICROCHIP_PFSOC_SYSREG].size);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
+ memmap[MICROCHIP_PFSOC_SYSREG].base);
/* MPUCFG */
create_unimplemented_device("microchip.pfsoc.mpucfg",
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index a244ae6d39..245c82db61 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -26,6 +26,7 @@
#include "hw/dma/sifive_pdma.h"
#include "hw/misc/mchp_pfsoc_dmc.h"
#include "hw/misc/mchp_pfsoc_ioscb.h"
+#include "hw/misc/mchp_pfsoc_sysreg.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
@@ -47,6 +48,7 @@ typedef struct MicrochipPFSoCState {
MchpPfSoCMMUartState *serial2;
MchpPfSoCMMUartState *serial3;
MchpPfSoCMMUartState *serial4;
+ MchpPfSoCSysregState sysreg;
SiFivePDMAState dma;
CadenceGEMState gem0;
CadenceGEMState gem1;
--
2.25.1
next prev parent reply other threads:[~2020-10-27 14:44 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
2020-10-27 14:17 ` [RESEND PATCH 1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Bin Meng
2020-10-27 20:45 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Bin Meng
2020-10-27 17:37 ` Alistair Francis
2020-10-28 1:43 ` Bin Meng
2020-10-28 14:13 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support Bin Meng
2020-10-27 20:48 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 4/9] hw/riscv: microchip_pfsoc: Connect the IOSCB module Bin Meng
2020-10-27 17:42 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 5/9] hw/misc: Add Microchip PolarFire SoC SYSREG module support Bin Meng
2020-10-27 20:51 ` Alistair Francis
2020-10-27 14:17 ` Bin Meng [this message]
2020-10-27 17:42 ` [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory Bin Meng
2020-10-27 17:30 ` Alistair Francis
2020-10-28 2:08 ` Bin Meng
2020-10-27 14:17 ` [RESEND PATCH 8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map Bin Meng
2020-10-27 20:55 ` Alistair Francis
2020-10-28 2:06 ` Bin Meng
2020-10-27 14:17 ` [RESEND PATCH 9/9] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Bin Meng
2020-10-27 17:19 ` Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201027141740.18336-7-bmeng.cn@gmail.com \
--to=bmeng.cn@gmail.com \
--cc=Alistair.Francis@wdc.com \
--cc=anup.patel@wdc.com \
--cc=atish.patra@wdc.com \
--cc=bin.meng@windriver.com \
--cc=ivan.griffin@emdalo.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).