* [RESEND PATCH 1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
@ 2020-10-27 14:17 ` Bin Meng
2020-10-27 20:45 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Bin Meng
` (7 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2020-10-27 14:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Bin Meng, Atish Patra, Anup Patel, Ivan Griffin
From: Bin Meng <bin.meng@windriver.com>
The PolarFire SoC DDR Memory Controller mainly includes 2 modules,
called SGMII PHY module and the CFG module, as documented in the
chipset datasheet.
This creates a single file that groups these 2 modules, providing
the minimum functionalities that make the HSS DDR initialization
codes happy.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
MAINTAINERS | 2 +
hw/misc/Kconfig | 3 +
hw/misc/mchp_pfsoc_dmc.c | 216 +++++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
include/hw/misc/mchp_pfsoc_dmc.h | 56 ++++++++
5 files changed, 278 insertions(+)
create mode 100644 hw/misc/mchp_pfsoc_dmc.c
create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h
diff --git a/MAINTAINERS b/MAINTAINERS
index ef6f5c7399..caacec401c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1326,8 +1326,10 @@ L: qemu-riscv@nongnu.org
S: Supported
F: hw/riscv/microchip_pfsoc.c
F: hw/char/mchp_pfsoc_mmuart.c
+F: hw/misc/mchp_pfsoc_dmc.c
F: include/hw/riscv/microchip_pfsoc.h
F: include/hw/char/mchp_pfsoc_mmuart.h
+F: include/hw/misc/mchp_pfsoc_dmc.h
RX Machines
-----------
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 3185456110..198bb1c6ba 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -134,6 +134,9 @@ config MAC_VIA
config AVR_POWER
bool
+config MCHP_PFSOC_DMC
+ bool
+
config SIFIVE_TEST
bool
diff --git a/hw/misc/mchp_pfsoc_dmc.c b/hw/misc/mchp_pfsoc_dmc.c
new file mode 100644
index 0000000000..15cf3d7725
--- /dev/null
+++ b/hw/misc/mchp_pfsoc_dmc.c
@@ -0,0 +1,216 @@
+/*
+ * Microchip PolarFire SoC DDR Memory Controller module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/mchp_pfsoc_dmc.h"
+
+/* DDR SGMII PHY module */
+
+#define SGMII_PHY_IOC_REG1 0x208
+#define SGMII_PHY_TRAINING_STATUS 0x814
+#define SGMII_PHY_DQ_DQS_ERR_DONE 0x834
+#define SGMII_PHY_DQDQS_STATUS1 0x84c
+#define SGMII_PHY_PVT_STAT 0xc20
+
+static uint64_t mchp_pfsoc_ddr_sgmii_phy_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint32_t val = 0;
+ static int training_status_bit;
+
+ switch (offset) {
+ case SGMII_PHY_IOC_REG1:
+ /* See ddr_pvt_calibration() in HSS */
+ val = BIT(4) | BIT(2);
+ break;
+ case SGMII_PHY_TRAINING_STATUS:
+ /*
+ * The codes logic emulates the training status change from
+ * DDR_TRAINING_IP_SM_BCLKSCLK to DDR_TRAINING_IP_SM_DQ_DQS.
+ *
+ * See ddr_setup() in mss_ddr.c in the HSS source codes.
+ */
+ val = 1 << training_status_bit;
+ training_status_bit = (training_status_bit + 1) % 5;
+ break;
+ case SGMII_PHY_DQ_DQS_ERR_DONE:
+ /*
+ * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
+ * check that DQ/DQS training passed without error.
+ */
+ val = 8;
+ break;
+ case SGMII_PHY_DQDQS_STATUS1:
+ /*
+ * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
+ * check that DQ/DQS calculated window is above 5 taps.
+ */
+ val = 0xff;
+ break;
+ case SGMII_PHY_PVT_STAT:
+ /* See sgmii_channel_setup() in HSS */
+ val = BIT(14) | BIT(6);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+ break;
+ }
+
+ return val;
+}
+
+static void mchp_pfsoc_ddr_sgmii_phy_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+ "(size %d, value 0x%" PRIx64
+ ", offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_ddr_sgmii_phy_ops = {
+ .read = mchp_pfsoc_ddr_sgmii_phy_read,
+ .write = mchp_pfsoc_ddr_sgmii_phy_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_ddr_sgmii_phy_realize(DeviceState *dev, Error **errp)
+{
+ MchpPfSoCDdrSgmiiPhyState *s = MCHP_PFSOC_DDR_SGMII_PHY(dev);
+
+ memory_region_init_io(&s->sgmii_phy, OBJECT(dev),
+ &mchp_pfsoc_ddr_sgmii_phy_ops, s,
+ "mchp.pfsoc.ddr_sgmii_phy",
+ MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sgmii_phy);
+}
+
+static void mchp_pfsoc_ddr_sgmii_phy_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Microchip PolarFire SoC DDR SGMII PHY module";
+ dc->realize = mchp_pfsoc_ddr_sgmii_phy_realize;
+}
+
+static const TypeInfo mchp_pfsoc_ddr_sgmii_phy_info = {
+ .name = TYPE_MCHP_PFSOC_DDR_SGMII_PHY,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MchpPfSoCDdrSgmiiPhyState),
+ .class_init = mchp_pfsoc_ddr_sgmii_phy_class_init,
+};
+
+static void mchp_pfsoc_ddr_sgmii_phy_register_types(void)
+{
+ type_register_static(&mchp_pfsoc_ddr_sgmii_phy_info);
+}
+
+type_init(mchp_pfsoc_ddr_sgmii_phy_register_types)
+
+/* DDR CFG module */
+
+#define CFG_MT_DONE_ACK 0x4428
+#define CFG_STAT_DFI_INIT_COMPLETE 0x10034
+#define CFG_STAT_DFI_TRAINING_COMPLETE 0x10038
+
+static uint64_t mchp_pfsoc_ddr_cfg_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint32_t val = 0;
+
+ switch (offset) {
+ case CFG_MT_DONE_ACK:
+ /* memory test in MTC_test() */
+ val = BIT(0);
+ break;
+ case CFG_STAT_DFI_INIT_COMPLETE:
+ /* DDR_TRAINING_IP_SM_START_CHECK state in ddr_setup() */
+ val = BIT(0);
+ break;
+ case CFG_STAT_DFI_TRAINING_COMPLETE:
+ /* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup() */
+ val = BIT(0);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+ break;
+ }
+
+ return val;
+}
+
+static void mchp_pfsoc_ddr_cfg_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+ "(size %d, value 0x%" PRIx64
+ ", offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_ddr_cfg_ops = {
+ .read = mchp_pfsoc_ddr_cfg_read,
+ .write = mchp_pfsoc_ddr_cfg_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_ddr_cfg_realize(DeviceState *dev, Error **errp)
+{
+ MchpPfSoCDdrCfgState *s = MCHP_PFSOC_DDR_CFG(dev);
+
+ memory_region_init_io(&s->cfg, OBJECT(dev),
+ &mchp_pfsoc_ddr_cfg_ops, s,
+ "mchp.pfsoc.ddr_cfg",
+ MCHP_PFSOC_DDR_CFG_REG_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->cfg);
+}
+
+static void mchp_pfsoc_ddr_cfg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Microchip PolarFire SoC DDR CFG module";
+ dc->realize = mchp_pfsoc_ddr_cfg_realize;
+}
+
+static const TypeInfo mchp_pfsoc_ddr_cfg_info = {
+ .name = TYPE_MCHP_PFSOC_DDR_CFG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MchpPfSoCDdrCfgState),
+ .class_init = mchp_pfsoc_ddr_cfg_class_init,
+};
+
+static void mchp_pfsoc_ddr_cfg_register_types(void)
+{
+ type_register_static(&mchp_pfsoc_ddr_cfg_info);
+}
+
+type_init(mchp_pfsoc_ddr_cfg_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 793d45b1dc..2d79a657e0 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
# RISC-V devices
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
diff --git a/include/hw/misc/mchp_pfsoc_dmc.h b/include/hw/misc/mchp_pfsoc_dmc.h
new file mode 100644
index 0000000000..2baa1413b0
--- /dev/null
+++ b/include/hw/misc/mchp_pfsoc_dmc.h
@@ -0,0 +1,56 @@
+/*
+ * Microchip PolarFire SoC DDR Memory Controller module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MCHP_PFSOC_DMC_H
+#define MCHP_PFSOC_DMC_H
+
+/* DDR SGMII PHY module */
+
+#define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE 0x1000
+
+typedef struct MchpPfSoCDdrSgmiiPhyState {
+ SysBusDevice parent;
+ MemoryRegion sgmii_phy;
+} MchpPfSoCDdrSgmiiPhyState;
+
+#define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy"
+
+#define MCHP_PFSOC_DDR_SGMII_PHY(obj) \
+ OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \
+ TYPE_MCHP_PFSOC_DDR_SGMII_PHY)
+
+/* DDR CFG module */
+
+#define MCHP_PFSOC_DDR_CFG_REG_SIZE 0x40000
+
+typedef struct MchpPfSoCDdrCfgState {
+ SysBusDevice parent;
+ MemoryRegion cfg;
+} MchpPfSoCDdrCfgState;
+
+#define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg"
+
+#define MCHP_PFSOC_DDR_CFG(obj) \
+ OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \
+ TYPE_MCHP_PFSOC_DDR_CFG)
+
+#endif /* MCHP_PFSOC_DMC_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
2020-10-27 14:17 ` [RESEND PATCH 1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Bin Meng
@ 2020-10-27 20:45 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2020-10-27 20:45 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
On Tue, Oct 27, 2020 at 7:48 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The PolarFire SoC DDR Memory Controller mainly includes 2 modules,
> called SGMII PHY module and the CFG module, as documented in the
> chipset datasheet.
>
> This creates a single file that groups these 2 modules, providing
> the minimum functionalities that make the HSS DDR initialization
> codes happy.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> MAINTAINERS | 2 +
> hw/misc/Kconfig | 3 +
> hw/misc/mchp_pfsoc_dmc.c | 216 +++++++++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> include/hw/misc/mchp_pfsoc_dmc.h | 56 ++++++++
> 5 files changed, 278 insertions(+)
> create mode 100644 hw/misc/mchp_pfsoc_dmc.c
> create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ef6f5c7399..caacec401c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1326,8 +1326,10 @@ L: qemu-riscv@nongnu.org
> S: Supported
> F: hw/riscv/microchip_pfsoc.c
> F: hw/char/mchp_pfsoc_mmuart.c
> +F: hw/misc/mchp_pfsoc_dmc.c
> F: include/hw/riscv/microchip_pfsoc.h
> F: include/hw/char/mchp_pfsoc_mmuart.h
> +F: include/hw/misc/mchp_pfsoc_dmc.h
>
> RX Machines
> -----------
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 3185456110..198bb1c6ba 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -134,6 +134,9 @@ config MAC_VIA
> config AVR_POWER
> bool
>
> +config MCHP_PFSOC_DMC
> + bool
> +
> config SIFIVE_TEST
> bool
>
> diff --git a/hw/misc/mchp_pfsoc_dmc.c b/hw/misc/mchp_pfsoc_dmc.c
> new file mode 100644
> index 0000000000..15cf3d7725
> --- /dev/null
> +++ b/hw/misc/mchp_pfsoc_dmc.c
> @@ -0,0 +1,216 @@
> +/*
> + * Microchip PolarFire SoC DDR Memory Controller module emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + * Bin Meng <bin.meng@windriver.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/bitops.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "hw/hw.h"
> +#include "hw/sysbus.h"
> +#include "hw/misc/mchp_pfsoc_dmc.h"
> +
> +/* DDR SGMII PHY module */
> +
> +#define SGMII_PHY_IOC_REG1 0x208
> +#define SGMII_PHY_TRAINING_STATUS 0x814
> +#define SGMII_PHY_DQ_DQS_ERR_DONE 0x834
> +#define SGMII_PHY_DQDQS_STATUS1 0x84c
> +#define SGMII_PHY_PVT_STAT 0xc20
> +
> +static uint64_t mchp_pfsoc_ddr_sgmii_phy_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + uint32_t val = 0;
> + static int training_status_bit;
> +
> + switch (offset) {
> + case SGMII_PHY_IOC_REG1:
> + /* See ddr_pvt_calibration() in HSS */
> + val = BIT(4) | BIT(2);
> + break;
> + case SGMII_PHY_TRAINING_STATUS:
> + /*
> + * The codes logic emulates the training status change from
> + * DDR_TRAINING_IP_SM_BCLKSCLK to DDR_TRAINING_IP_SM_DQ_DQS.
> + *
> + * See ddr_setup() in mss_ddr.c in the HSS source codes.
> + */
> + val = 1 << training_status_bit;
> + training_status_bit = (training_status_bit + 1) % 5;
> + break;
> + case SGMII_PHY_DQ_DQS_ERR_DONE:
> + /*
> + * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
> + * check that DQ/DQS training passed without error.
> + */
> + val = 8;
> + break;
> + case SGMII_PHY_DQDQS_STATUS1:
> + /*
> + * DDR_TRAINING_IP_SM_VERIFY state in ddr_setup(),
> + * check that DQ/DQS calculated window is above 5 taps.
> + */
> + val = 0xff;
> + break;
> + case SGMII_PHY_PVT_STAT:
> + /* See sgmii_channel_setup() in HSS */
> + val = BIT(14) | BIT(6);
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
> + "(size %d, offset 0x%" HWADDR_PRIx ")\n",
> + __func__, size, offset);
> + break;
> + }
> +
> + return val;
> +}
> +
> +static void mchp_pfsoc_ddr_sgmii_phy_write(void *opaque, hwaddr offset,
> + uint64_t value, unsigned size)
> +{
> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
> + "(size %d, value 0x%" PRIx64
> + ", offset 0x%" HWADDR_PRIx ")\n",
> + __func__, size, value, offset);
> +}
> +
> +static const MemoryRegionOps mchp_pfsoc_ddr_sgmii_phy_ops = {
> + .read = mchp_pfsoc_ddr_sgmii_phy_read,
> + .write = mchp_pfsoc_ddr_sgmii_phy_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static void mchp_pfsoc_ddr_sgmii_phy_realize(DeviceState *dev, Error **errp)
> +{
> + MchpPfSoCDdrSgmiiPhyState *s = MCHP_PFSOC_DDR_SGMII_PHY(dev);
> +
> + memory_region_init_io(&s->sgmii_phy, OBJECT(dev),
> + &mchp_pfsoc_ddr_sgmii_phy_ops, s,
> + "mchp.pfsoc.ddr_sgmii_phy",
> + MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE);
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sgmii_phy);
> +}
> +
> +static void mchp_pfsoc_ddr_sgmii_phy_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "Microchip PolarFire SoC DDR SGMII PHY module";
> + dc->realize = mchp_pfsoc_ddr_sgmii_phy_realize;
> +}
> +
> +static const TypeInfo mchp_pfsoc_ddr_sgmii_phy_info = {
> + .name = TYPE_MCHP_PFSOC_DDR_SGMII_PHY,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MchpPfSoCDdrSgmiiPhyState),
> + .class_init = mchp_pfsoc_ddr_sgmii_phy_class_init,
> +};
> +
> +static void mchp_pfsoc_ddr_sgmii_phy_register_types(void)
> +{
> + type_register_static(&mchp_pfsoc_ddr_sgmii_phy_info);
> +}
> +
> +type_init(mchp_pfsoc_ddr_sgmii_phy_register_types)
> +
> +/* DDR CFG module */
> +
> +#define CFG_MT_DONE_ACK 0x4428
> +#define CFG_STAT_DFI_INIT_COMPLETE 0x10034
> +#define CFG_STAT_DFI_TRAINING_COMPLETE 0x10038
> +
> +static uint64_t mchp_pfsoc_ddr_cfg_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + uint32_t val = 0;
> +
> + switch (offset) {
> + case CFG_MT_DONE_ACK:
> + /* memory test in MTC_test() */
> + val = BIT(0);
> + break;
> + case CFG_STAT_DFI_INIT_COMPLETE:
> + /* DDR_TRAINING_IP_SM_START_CHECK state in ddr_setup() */
> + val = BIT(0);
> + break;
> + case CFG_STAT_DFI_TRAINING_COMPLETE:
> + /* DDR_TRAINING_IP_SM_VERIFY state in ddr_setup() */
> + val = BIT(0);
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
> + "(size %d, offset 0x%" HWADDR_PRIx ")\n",
> + __func__, size, offset);
> + break;
> + }
> +
> + return val;
> +}
> +
> +static void mchp_pfsoc_ddr_cfg_write(void *opaque, hwaddr offset,
> + uint64_t value, unsigned size)
> +{
> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
> + "(size %d, value 0x%" PRIx64
> + ", offset 0x%" HWADDR_PRIx ")\n",
> + __func__, size, value, offset);
> +}
> +
> +static const MemoryRegionOps mchp_pfsoc_ddr_cfg_ops = {
> + .read = mchp_pfsoc_ddr_cfg_read,
> + .write = mchp_pfsoc_ddr_cfg_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static void mchp_pfsoc_ddr_cfg_realize(DeviceState *dev, Error **errp)
> +{
> + MchpPfSoCDdrCfgState *s = MCHP_PFSOC_DDR_CFG(dev);
> +
> + memory_region_init_io(&s->cfg, OBJECT(dev),
> + &mchp_pfsoc_ddr_cfg_ops, s,
> + "mchp.pfsoc.ddr_cfg",
> + MCHP_PFSOC_DDR_CFG_REG_SIZE);
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->cfg);
> +}
> +
> +static void mchp_pfsoc_ddr_cfg_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "Microchip PolarFire SoC DDR CFG module";
> + dc->realize = mchp_pfsoc_ddr_cfg_realize;
> +}
> +
> +static const TypeInfo mchp_pfsoc_ddr_cfg_info = {
> + .name = TYPE_MCHP_PFSOC_DDR_CFG,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MchpPfSoCDdrCfgState),
> + .class_init = mchp_pfsoc_ddr_cfg_class_init,
> +};
> +
> +static void mchp_pfsoc_ddr_cfg_register_types(void)
> +{
> + type_register_static(&mchp_pfsoc_ddr_cfg_info);
> +}
> +
> +type_init(mchp_pfsoc_ddr_cfg_register_types)
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 793d45b1dc..2d79a657e0 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c'))
> softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
> # RISC-V devices
> +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
> softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
> softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
> softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
> diff --git a/include/hw/misc/mchp_pfsoc_dmc.h b/include/hw/misc/mchp_pfsoc_dmc.h
> new file mode 100644
> index 0000000000..2baa1413b0
> --- /dev/null
> +++ b/include/hw/misc/mchp_pfsoc_dmc.h
> @@ -0,0 +1,56 @@
> +/*
> + * Microchip PolarFire SoC DDR Memory Controller module emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + * Bin Meng <bin.meng@windriver.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef MCHP_PFSOC_DMC_H
> +#define MCHP_PFSOC_DMC_H
> +
> +/* DDR SGMII PHY module */
> +
> +#define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE 0x1000
> +
> +typedef struct MchpPfSoCDdrSgmiiPhyState {
> + SysBusDevice parent;
> + MemoryRegion sgmii_phy;
> +} MchpPfSoCDdrSgmiiPhyState;
> +
> +#define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy"
> +
> +#define MCHP_PFSOC_DDR_SGMII_PHY(obj) \
> + OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \
> + TYPE_MCHP_PFSOC_DDR_SGMII_PHY)
> +
> +/* DDR CFG module */
> +
> +#define MCHP_PFSOC_DDR_CFG_REG_SIZE 0x40000
> +
> +typedef struct MchpPfSoCDdrCfgState {
> + SysBusDevice parent;
> + MemoryRegion cfg;
> +} MchpPfSoCDdrCfgState;
> +
> +#define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg"
> +
> +#define MCHP_PFSOC_DDR_CFG(obj) \
> + OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \
> + TYPE_MCHP_PFSOC_DDR_CFG)
> +
> +#endif /* MCHP_PFSOC_DMC_H */
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
2020-10-27 14:17 ` [RESEND PATCH 1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Bin Meng
@ 2020-10-27 14:17 ` Bin Meng
2020-10-27 17:37 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support Bin Meng
` (6 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2020-10-27 14:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Bin Meng, Atish Patra, Anup Patel, Ivan Griffin
From: Bin Meng <bin.meng@windriver.com>
Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/Kconfig | 1 +
hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++
include/hw/riscv/microchip_pfsoc.h | 5 +++++
3 files changed, 24 insertions(+)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 2df978fe8d..c8e50bde99 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -4,6 +4,7 @@ config IBEX
config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
+ select MCHP_PFSOC_DMC
select MCHP_PFSOC_MMUART
select MSI_NONBROKEN
select SIFIVE_CLINT
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4627179cd3..85be2bcde8 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -15,6 +15,7 @@
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
* 5) SiFive Platform DMA (Direct Memory Access Controller)
* 6) GEM (Gigabit Ethernet MAC Controller)
+ * 7) DMC (DDR Memory Controller)
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -85,7 +86,9 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
+ [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
[MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
+ [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
[MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
@@ -131,6 +134,11 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma-controller", &s->dma,
TYPE_SIFIVE_PDMA);
+ object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
+ TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
+ object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
+ TYPE_MCHP_PFSOC_DDR_CFG);
+
object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
@@ -260,6 +268,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
memmap[MICROCHIP_PFSOC_MPUCFG].base,
memmap[MICROCHIP_PFSOC_MPUCFG].size);
+ /* DDR SGMII PHY */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
+ memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base);
+
+ /* DDR CFG */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
+ memmap[MICROCHIP_PFSOC_DDR_CFG].base);
+
/* SDHCI */
sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 8bfc7e1a85..5b81e26241 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -24,6 +24,7 @@
#include "hw/char/mchp_pfsoc_mmuart.h"
#include "hw/dma/sifive_pdma.h"
+#include "hw/misc/mchp_pfsoc_dmc.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
@@ -37,6 +38,8 @@ typedef struct MicrochipPFSoCState {
RISCVHartArrayState e_cpus;
RISCVHartArrayState u_cpus;
DeviceState *plic;
+ MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
+ MchpPfSoCDdrCfgState ddr_cfg;
MchpPfSoCMMUartState *serial0;
MchpPfSoCMMUartState *serial1;
MchpPfSoCMMUartState *serial2;
@@ -82,7 +85,9 @@ enum {
MICROCHIP_PFSOC_MMUART0,
MICROCHIP_PFSOC_SYSREG,
MICROCHIP_PFSOC_MPUCFG,
+ MICROCHIP_PFSOC_DDR_SGMII_PHY,
MICROCHIP_PFSOC_EMMC_SD,
+ MICROCHIP_PFSOC_DDR_CFG,
MICROCHIP_PFSOC_MMUART1,
MICROCHIP_PFSOC_MMUART2,
MICROCHIP_PFSOC_MMUART3,
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
2020-10-27 14:17 ` [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Bin Meng
@ 2020-10-27 17:37 ` Alistair Francis
2020-10-28 1:43 ` Bin Meng
0 siblings, 1 reply; 23+ messages in thread
From: Alistair Francis @ 2020-10-27 17:37 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
On Tue, Oct 27, 2020 at 7:46 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> hw/riscv/Kconfig | 1 +
> hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++
> include/hw/riscv/microchip_pfsoc.h | 5 +++++
> 3 files changed, 24 insertions(+)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 2df978fe8d..c8e50bde99 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -4,6 +4,7 @@ config IBEX
> config MICROCHIP_PFSOC
> bool
> select CADENCE_SDHCI
> + select MCHP_PFSOC_DMC
> select MCHP_PFSOC_MMUART
> select MSI_NONBROKEN
> select SIFIVE_CLINT
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 4627179cd3..85be2bcde8 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -15,6 +15,7 @@
> * 4) Cadence eMMC/SDHC controller and an SD card connected to it
> * 5) SiFive Platform DMA (Direct Memory Access Controller)
> * 6) GEM (Gigabit Ethernet MAC Controller)
> + * 7) DMC (DDR Memory Controller)
> *
> * This board currently generates devicetree dynamically that indicates at least
> * two harts and up to five harts.
> @@ -85,7 +86,9 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
> [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
> [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
> + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
> [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
> + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
Neither of these are documented....
Maybe just add a single comment above the memory layout clarifying
that this is not what is documented from the SoC but is instead based
on what guests do?
It seems to be a constant problem with this board, unless I am really
misreading the memory map.
Alistair
> [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
> [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
> [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
> @@ -131,6 +134,11 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
> object_initialize_child(obj, "dma-controller", &s->dma,
> TYPE_SIFIVE_PDMA);
>
> + object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
> + TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
> + object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
> + TYPE_MCHP_PFSOC_DDR_CFG);
> +
> object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
> object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
>
> @@ -260,6 +268,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> memmap[MICROCHIP_PFSOC_MPUCFG].base,
> memmap[MICROCHIP_PFSOC_MPUCFG].size);
>
> + /* DDR SGMII PHY */
> + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
> + memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base);
> +
> + /* DDR CFG */
> + sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
> + memmap[MICROCHIP_PFSOC_DDR_CFG].base);
> +
> /* SDHCI */
> sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
> sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index 8bfc7e1a85..5b81e26241 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -24,6 +24,7 @@
>
> #include "hw/char/mchp_pfsoc_mmuart.h"
> #include "hw/dma/sifive_pdma.h"
> +#include "hw/misc/mchp_pfsoc_dmc.h"
> #include "hw/net/cadence_gem.h"
> #include "hw/sd/cadence_sdhci.h"
>
> @@ -37,6 +38,8 @@ typedef struct MicrochipPFSoCState {
> RISCVHartArrayState e_cpus;
> RISCVHartArrayState u_cpus;
> DeviceState *plic;
> + MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
> + MchpPfSoCDdrCfgState ddr_cfg;
> MchpPfSoCMMUartState *serial0;
> MchpPfSoCMMUartState *serial1;
> MchpPfSoCMMUartState *serial2;
> @@ -82,7 +85,9 @@ enum {
> MICROCHIP_PFSOC_MMUART0,
> MICROCHIP_PFSOC_SYSREG,
> MICROCHIP_PFSOC_MPUCFG,
> + MICROCHIP_PFSOC_DDR_SGMII_PHY,
> MICROCHIP_PFSOC_EMMC_SD,
> + MICROCHIP_PFSOC_DDR_CFG,
> MICROCHIP_PFSOC_MMUART1,
> MICROCHIP_PFSOC_MMUART2,
> MICROCHIP_PFSOC_MMUART3,
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
2020-10-27 17:37 ` Alistair Francis
@ 2020-10-28 1:43 ` Bin Meng
2020-10-28 14:13 ` Alistair Francis
0 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2020-10-28 1:43 UTC (permalink / raw)
To: Alistair Francis
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
Hi Alistair,
On Wed, Oct 28, 2020 at 1:49 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Oct 27, 2020 at 7:46 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > ---
> >
> > hw/riscv/Kconfig | 1 +
> > hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++
> > include/hw/riscv/microchip_pfsoc.h | 5 +++++
> > 3 files changed, 24 insertions(+)
> >
> > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> > index 2df978fe8d..c8e50bde99 100644
> > --- a/hw/riscv/Kconfig
> > +++ b/hw/riscv/Kconfig
> > @@ -4,6 +4,7 @@ config IBEX
> > config MICROCHIP_PFSOC
> > bool
> > select CADENCE_SDHCI
> > + select MCHP_PFSOC_DMC
> > select MCHP_PFSOC_MMUART
> > select MSI_NONBROKEN
> > select SIFIVE_CLINT
> > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> > index 4627179cd3..85be2bcde8 100644
> > --- a/hw/riscv/microchip_pfsoc.c
> > +++ b/hw/riscv/microchip_pfsoc.c
> > @@ -15,6 +15,7 @@
> > * 4) Cadence eMMC/SDHC controller and an SD card connected to it
> > * 5) SiFive Platform DMA (Direct Memory Access Controller)
> > * 6) GEM (Gigabit Ethernet MAC Controller)
> > + * 7) DMC (DDR Memory Controller)
> > *
> > * This board currently generates devicetree dynamically that indicates at least
> > * two harts and up to five harts.
> > @@ -85,7 +86,9 @@ static const struct MemmapEntry {
> > [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
> > [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
> > [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
> > + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
> > [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
> > + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
>
> Neither of these are documented....
It's documented in the "Register
Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm" in
https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
>
> Maybe just add a single comment above the memory layout clarifying
> that this is not what is documented from the SoC but is instead based
> on what guests do?
>
I can add a link to the Microchip website that documents the memory
map above the memory layout.
> It seems to be a constant problem with this board, unless I am really
> misreading the memory map.
>
Regards,
Bin
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
2020-10-28 1:43 ` Bin Meng
@ 2020-10-28 14:13 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2020-10-28 14:13 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
On Tue, Oct 27, 2020 at 6:43 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Hi Alistair,
>
> On Wed, Oct 28, 2020 at 1:49 AM Alistair Francis <alistair23@gmail.com> wrote:
> >
> > On Tue, Oct 27, 2020 at 7:46 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> > >
> > > From: Bin Meng <bin.meng@windriver.com>
> > >
> > > Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.
> > >
> > > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > > ---
> > >
> > > hw/riscv/Kconfig | 1 +
> > > hw/riscv/microchip_pfsoc.c | 18 ++++++++++++++++++
> > > include/hw/riscv/microchip_pfsoc.h | 5 +++++
> > > 3 files changed, 24 insertions(+)
> > >
> > > diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> > > index 2df978fe8d..c8e50bde99 100644
> > > --- a/hw/riscv/Kconfig
> > > +++ b/hw/riscv/Kconfig
> > > @@ -4,6 +4,7 @@ config IBEX
> > > config MICROCHIP_PFSOC
> > > bool
> > > select CADENCE_SDHCI
> > > + select MCHP_PFSOC_DMC
> > > select MCHP_PFSOC_MMUART
> > > select MSI_NONBROKEN
> > > select SIFIVE_CLINT
> > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> > > index 4627179cd3..85be2bcde8 100644
> > > --- a/hw/riscv/microchip_pfsoc.c
> > > +++ b/hw/riscv/microchip_pfsoc.c
> > > @@ -15,6 +15,7 @@
> > > * 4) Cadence eMMC/SDHC controller and an SD card connected to it
> > > * 5) SiFive Platform DMA (Direct Memory Access Controller)
> > > * 6) GEM (Gigabit Ethernet MAC Controller)
> > > + * 7) DMC (DDR Memory Controller)
> > > *
> > > * This board currently generates devicetree dynamically that indicates at least
> > > * two harts and up to five harts.
> > > @@ -85,7 +86,9 @@ static const struct MemmapEntry {
> > > [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
> > > [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
> > > [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
> > > + [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
> > > [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
> > > + [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
> >
> > Neither of these are documented....
>
> It's documented in the "Register
> Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm" in
> https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
That doesn't seem to be an official version controled doc though and
it seems to conflict with the other UG document.
>
> >
> > Maybe just add a single comment above the memory layout clarifying
> > that this is not what is documented from the SoC but is instead based
> > on what guests do?
> >
>
> I can add a link to the Microchip website that documents the memory
> map above the memory layout.
Thanks, that's at least something.
Alistair
>
> > It seems to be a constant problem with this board, unless I am really
> > misreading the memory map.
> >
>
> Regards,
> Bin
^ permalink raw reply [flat|nested] 23+ messages in thread
* [RESEND PATCH 3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
2020-10-27 14:17 ` [RESEND PATCH 1/9] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Bin Meng
2020-10-27 14:17 ` [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Bin Meng
@ 2020-10-27 14:17 ` Bin Meng
2020-10-27 20:48 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 4/9] hw/riscv: microchip_pfsoc: Connect the IOSCB module Bin Meng
` (5 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2020-10-27 14:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Bin Meng, Atish Patra, Anup Patel, Ivan Griffin
From: Bin Meng <bin.meng@windriver.com>
This creates a model for PolarFire SoC IOSCB [1] module. It actually
contains lots of sub-modules like various PLLs to control different
peripherals. Only the mininum capabilities are emulated to make the
HSS DDR memory initialization codes happy. Lots of sub-modules are
created as an unimplemented devices.
[1] PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm in
https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
MAINTAINERS | 2 +
hw/misc/Kconfig | 3 +
hw/misc/mchp_pfsoc_ioscb.c | 242 +++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
include/hw/misc/mchp_pfsoc_ioscb.h | 50 ++++++
5 files changed, 298 insertions(+)
create mode 100644 hw/misc/mchp_pfsoc_ioscb.c
create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h
diff --git a/MAINTAINERS b/MAINTAINERS
index caacec401c..ebbc62a62f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1327,9 +1327,11 @@ S: Supported
F: hw/riscv/microchip_pfsoc.c
F: hw/char/mchp_pfsoc_mmuart.c
F: hw/misc/mchp_pfsoc_dmc.c
+F: hw/misc/mchp_pfsoc_ioscb.c
F: include/hw/riscv/microchip_pfsoc.h
F: include/hw/char/mchp_pfsoc_mmuart.h
F: include/hw/misc/mchp_pfsoc_dmc.h
+F: include/hw/misc/mchp_pfsoc_ioscb.h
RX Machines
-----------
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 198bb1c6ba..3db15e06b4 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -137,6 +137,9 @@ config AVR_POWER
config MCHP_PFSOC_DMC
bool
+config MCHP_PFSOC_IOSCB
+ bool
+
config SIFIVE_TEST
bool
diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c
new file mode 100644
index 0000000000..32b88f53c1
--- /dev/null
+++ b/hw/misc/mchp_pfsoc_ioscb.c
@@ -0,0 +1,242 @@
+/*
+ * Microchip PolarFire SoC IOSCB module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/mchp_pfsoc_ioscb.h"
+
+/*
+ * The whole IOSCB module registers map into the system address at 0x3000_0000,
+ * named as "System Port 0 (AXI-D0)".
+ */
+#define IOSCB_WHOLE_REG_SIZE 0x10000000
+#define IOSCB_SUBMOD_REG_SIZE 0x1000
+
+/*
+ * There are many sub-modules in the IOSCB module.
+ * See Microchip PolarFire SoC documentation (Register_Map.zip),
+ * Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
+ *
+ * The following are sub-modules offsets that are of concern.
+ */
+#define IOSCB_LANE01_BASE 0x06500000
+#define IOSCB_LANE23_BASE 0x06510000
+#define IOSCB_CTRL_BASE 0x07020000
+#define IOSCB_CFG_BASE 0x07080000
+#define IOSCB_PLL_MSS_BASE 0x0E001000
+#define IOSCB_CFM_MSS_BASE 0x0E002000
+#define IOSCB_PLL_DDR_BASE 0x0E010000
+#define IOSCB_BC_DDR_BASE 0x0E020000
+#define IOSCB_IO_CALIB_DDR_BASE 0x0E040000
+#define IOSCB_PLL_SGMII_BASE 0x0E080000
+#define IOSCB_DLL_SGMII_BASE 0x0E100000
+#define IOSCB_CFM_SGMII_BASE 0x0E200000
+#define IOSCB_BC_SGMII_BASE 0x0E400000
+#define IOSCB_IO_CALIB_SGMII_BASE 0x0E800000
+
+static uint64_t mchp_pfsoc_dummy_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+
+ return 0;
+}
+
+static void mchp_pfsoc_dummy_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+ "(size %d, value 0x%" PRIx64
+ ", offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_dummy_ops = {
+ .read = mchp_pfsoc_dummy_read,
+ .write = mchp_pfsoc_dummy_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+/* All PLL modules in IOSCB have the same register layout */
+
+#define PLL_CTRL 0x04
+
+static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint32_t val = 0;
+
+ switch (offset) {
+ case PLL_CTRL:
+ /* PLL is locked */
+ val = BIT(25);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+ break;
+ }
+
+ return val;
+}
+
+static const MemoryRegionOps mchp_pfsoc_pll_ops = {
+ .read = mchp_pfsoc_pll_read,
+ .write = mchp_pfsoc_dummy_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+/* IO_CALIB_DDR submodule */
+
+#define IO_CALIB_DDR_IOC_REG1 0x08
+
+static uint64_t mchp_pfsoc_io_calib_ddr_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint32_t val = 0;
+
+ switch (offset) {
+ case IO_CALIB_DDR_IOC_REG1:
+ /* calibration completed */
+ val = BIT(2);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+ break;
+ }
+
+ return val;
+}
+
+static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
+ .read = mchp_pfsoc_io_calib_ddr_read,
+ .write = mchp_pfsoc_dummy_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
+{
+ MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ memory_region_init(&s->container, OBJECT(s),
+ "mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE);
+ sysbus_init_mmio(sbd, &s->container);
+
+ /* add subregions for all sub-modules in IOSCB */
+
+ memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.lane01", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01);
+
+ memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
+
+ memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
+
+ memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
+
+ memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
+ "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
+
+ memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.cfm_mss", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_CFM_MSS_BASE, &s->cfm_mss);
+
+ memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s,
+ "mchp.pfsoc.ioscb.pll_ddr", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_PLL_DDR_BASE, &s->pll_ddr);
+
+ memory_region_init_io(&s->bc_ddr, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.bc_ddr", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_BC_DDR_BASE, &s->bc_ddr);
+
+ memory_region_init_io(&s->io_calib_ddr, OBJECT(s),
+ &mchp_pfsoc_io_calib_ddr_ops, s,
+ "mchp.pfsoc.ioscb.io_calib_ddr",
+ IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_DDR_BASE,
+ &s->io_calib_ddr);
+
+ memory_region_init_io(&s->pll_sgmii, OBJECT(s), &mchp_pfsoc_pll_ops, s,
+ "mchp.pfsoc.ioscb.pll_sgmii", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_PLL_SGMII_BASE,
+ &s->pll_sgmii);
+
+ memory_region_init_io(&s->dll_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.dll_sgmii", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_DLL_SGMII_BASE,
+ &s->dll_sgmii);
+
+ memory_region_init_io(&s->cfm_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.cfm_sgmii", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_CFM_SGMII_BASE,
+ &s->cfm_sgmii);
+
+ memory_region_init_io(&s->bc_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
+ "mchp.pfsoc.ioscb.bc_sgmii", IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_BC_SGMII_BASE,
+ &s->bc_sgmii);
+
+ memory_region_init_io(&s->io_calib_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops,
+ s, "mchp.pfsoc.ioscb.io_calib_sgmii",
+ IOSCB_SUBMOD_REG_SIZE);
+ memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
+ &s->io_calib_sgmii);
+}
+
+static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Microchip PolarFire SoC IOSCB";
+ dc->realize = mchp_pfsoc_ioscb_realize;
+}
+
+static const TypeInfo mchp_pfsoc_ioscb_info = {
+ .name = TYPE_MCHP_PFSOC_IOSCB,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MchpPfSoCIoscbState),
+ .class_init = mchp_pfsoc_ioscb_class_init,
+};
+
+static void mchp_pfsoc_ioscb_register_types(void)
+{
+ type_register_static(&mchp_pfsoc_ioscb_info);
+}
+
+type_init(mchp_pfsoc_ioscb_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 2d79a657e0..6d3c1a3455 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
# RISC-V devices
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h
new file mode 100644
index 0000000000..9235523e33
--- /dev/null
+++ b/include/hw/misc/mchp_pfsoc_ioscb.h
@@ -0,0 +1,50 @@
+/*
+ * Microchip PolarFire SoC IOSCB module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MCHP_PFSOC_IOSCB_H
+#define MCHP_PFSOC_IOSCB_H
+
+typedef struct MchpPfSoCIoscbState {
+ SysBusDevice parent;
+ MemoryRegion container;
+ MemoryRegion lane01;
+ MemoryRegion lane23;
+ MemoryRegion ctrl;
+ MemoryRegion cfg;
+ MemoryRegion pll_mss;
+ MemoryRegion cfm_mss;
+ MemoryRegion pll_ddr;
+ MemoryRegion bc_ddr;
+ MemoryRegion io_calib_ddr;
+ MemoryRegion pll_sgmii;
+ MemoryRegion dll_sgmii;
+ MemoryRegion cfm_sgmii;
+ MemoryRegion bc_sgmii;
+ MemoryRegion io_calib_sgmii;
+} MchpPfSoCIoscbState;
+
+#define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb"
+
+#define MCHP_PFSOC_IOSCB(obj) \
+ OBJECT_CHECK(MchpPfSoCIoscbState, (obj), TYPE_MCHP_PFSOC_IOSCB)
+
+#endif /* MCHP_PFSOC_IOSCB_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support
2020-10-27 14:17 ` [RESEND PATCH 3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support Bin Meng
@ 2020-10-27 20:48 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2020-10-27 20:48 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
On Tue, Oct 27, 2020 at 7:50 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This creates a model for PolarFire SoC IOSCB [1] module. It actually
> contains lots of sub-modules like various PLLs to control different
> peripherals. Only the mininum capabilities are emulated to make the
> HSS DDR memory initialization codes happy. Lots of sub-modules are
> created as an unimplemented devices.
>
> [1] PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm in
> https://www.microsemi.com/document-portal/doc_download/1244581-polarfire-soc-register-map
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> MAINTAINERS | 2 +
> hw/misc/Kconfig | 3 +
> hw/misc/mchp_pfsoc_ioscb.c | 242 +++++++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> include/hw/misc/mchp_pfsoc_ioscb.h | 50 ++++++
> 5 files changed, 298 insertions(+)
> create mode 100644 hw/misc/mchp_pfsoc_ioscb.c
> create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index caacec401c..ebbc62a62f 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1327,9 +1327,11 @@ S: Supported
> F: hw/riscv/microchip_pfsoc.c
> F: hw/char/mchp_pfsoc_mmuart.c
> F: hw/misc/mchp_pfsoc_dmc.c
> +F: hw/misc/mchp_pfsoc_ioscb.c
> F: include/hw/riscv/microchip_pfsoc.h
> F: include/hw/char/mchp_pfsoc_mmuart.h
> F: include/hw/misc/mchp_pfsoc_dmc.h
> +F: include/hw/misc/mchp_pfsoc_ioscb.h
>
> RX Machines
> -----------
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 198bb1c6ba..3db15e06b4 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -137,6 +137,9 @@ config AVR_POWER
> config MCHP_PFSOC_DMC
> bool
>
> +config MCHP_PFSOC_IOSCB
> + bool
> +
> config SIFIVE_TEST
> bool
>
> diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c
> new file mode 100644
> index 0000000000..32b88f53c1
> --- /dev/null
> +++ b/hw/misc/mchp_pfsoc_ioscb.c
> @@ -0,0 +1,242 @@
> +/*
> + * Microchip PolarFire SoC IOSCB module emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + * Bin Meng <bin.meng@windriver.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/bitops.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "hw/hw.h"
> +#include "hw/sysbus.h"
> +#include "hw/misc/mchp_pfsoc_ioscb.h"
> +
> +/*
> + * The whole IOSCB module registers map into the system address at 0x3000_0000,
> + * named as "System Port 0 (AXI-D0)".
> + */
> +#define IOSCB_WHOLE_REG_SIZE 0x10000000
> +#define IOSCB_SUBMOD_REG_SIZE 0x1000
> +
> +/*
> + * There are many sub-modules in the IOSCB module.
> + * See Microchip PolarFire SoC documentation (Register_Map.zip),
> + * Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
> + *
> + * The following are sub-modules offsets that are of concern.
> + */
> +#define IOSCB_LANE01_BASE 0x06500000
> +#define IOSCB_LANE23_BASE 0x06510000
> +#define IOSCB_CTRL_BASE 0x07020000
> +#define IOSCB_CFG_BASE 0x07080000
> +#define IOSCB_PLL_MSS_BASE 0x0E001000
> +#define IOSCB_CFM_MSS_BASE 0x0E002000
> +#define IOSCB_PLL_DDR_BASE 0x0E010000
> +#define IOSCB_BC_DDR_BASE 0x0E020000
> +#define IOSCB_IO_CALIB_DDR_BASE 0x0E040000
> +#define IOSCB_PLL_SGMII_BASE 0x0E080000
> +#define IOSCB_DLL_SGMII_BASE 0x0E100000
> +#define IOSCB_CFM_SGMII_BASE 0x0E200000
> +#define IOSCB_BC_SGMII_BASE 0x0E400000
> +#define IOSCB_IO_CALIB_SGMII_BASE 0x0E800000
> +
> +static uint64_t mchp_pfsoc_dummy_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
> + "(size %d, offset 0x%" HWADDR_PRIx ")\n",
> + __func__, size, offset);
> +
> + return 0;
> +}
> +
> +static void mchp_pfsoc_dummy_write(void *opaque, hwaddr offset,
> + uint64_t value, unsigned size)
> +{
> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
> + "(size %d, value 0x%" PRIx64
> + ", offset 0x%" HWADDR_PRIx ")\n",
> + __func__, size, value, offset);
> +}
> +
> +static const MemoryRegionOps mchp_pfsoc_dummy_ops = {
> + .read = mchp_pfsoc_dummy_read,
> + .write = mchp_pfsoc_dummy_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +/* All PLL modules in IOSCB have the same register layout */
> +
> +#define PLL_CTRL 0x04
> +
> +static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + uint32_t val = 0;
> +
> + switch (offset) {
> + case PLL_CTRL:
> + /* PLL is locked */
> + val = BIT(25);
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
> + "(size %d, offset 0x%" HWADDR_PRIx ")\n",
> + __func__, size, offset);
> + break;
> + }
> +
> + return val;
> +}
> +
> +static const MemoryRegionOps mchp_pfsoc_pll_ops = {
> + .read = mchp_pfsoc_pll_read,
> + .write = mchp_pfsoc_dummy_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +/* IO_CALIB_DDR submodule */
> +
> +#define IO_CALIB_DDR_IOC_REG1 0x08
> +
> +static uint64_t mchp_pfsoc_io_calib_ddr_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + uint32_t val = 0;
> +
> + switch (offset) {
> + case IO_CALIB_DDR_IOC_REG1:
> + /* calibration completed */
> + val = BIT(2);
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
> + "(size %d, offset 0x%" HWADDR_PRIx ")\n",
> + __func__, size, offset);
> + break;
> + }
> +
> + return val;
> +}
> +
> +static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
> + .read = mchp_pfsoc_io_calib_ddr_read,
> + .write = mchp_pfsoc_dummy_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
> +{
> + MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> +
> + memory_region_init(&s->container, OBJECT(s),
> + "mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE);
> + sysbus_init_mmio(sbd, &s->container);
> +
> + /* add subregions for all sub-modules in IOSCB */
> +
> + memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
> + "mchp.pfsoc.ioscb.lane01", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01);
> +
> + memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
> + "mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
> +
> + memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
> + "mchp.pfsoc.ioscb.ctrl", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
> +
> + memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
> + "mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
> +
> + memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
> + "mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
> +
> + memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
> + "mchp.pfsoc.ioscb.cfm_mss", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_CFM_MSS_BASE, &s->cfm_mss);
> +
> + memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s,
> + "mchp.pfsoc.ioscb.pll_ddr", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_PLL_DDR_BASE, &s->pll_ddr);
> +
> + memory_region_init_io(&s->bc_ddr, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
> + "mchp.pfsoc.ioscb.bc_ddr", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_BC_DDR_BASE, &s->bc_ddr);
> +
> + memory_region_init_io(&s->io_calib_ddr, OBJECT(s),
> + &mchp_pfsoc_io_calib_ddr_ops, s,
> + "mchp.pfsoc.ioscb.io_calib_ddr",
> + IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_DDR_BASE,
> + &s->io_calib_ddr);
> +
> + memory_region_init_io(&s->pll_sgmii, OBJECT(s), &mchp_pfsoc_pll_ops, s,
> + "mchp.pfsoc.ioscb.pll_sgmii", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_PLL_SGMII_BASE,
> + &s->pll_sgmii);
> +
> + memory_region_init_io(&s->dll_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
> + "mchp.pfsoc.ioscb.dll_sgmii", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_DLL_SGMII_BASE,
> + &s->dll_sgmii);
> +
> + memory_region_init_io(&s->cfm_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
> + "mchp.pfsoc.ioscb.cfm_sgmii", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_CFM_SGMII_BASE,
> + &s->cfm_sgmii);
> +
> + memory_region_init_io(&s->bc_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
> + "mchp.pfsoc.ioscb.bc_sgmii", IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_BC_SGMII_BASE,
> + &s->bc_sgmii);
> +
> + memory_region_init_io(&s->io_calib_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops,
> + s, "mchp.pfsoc.ioscb.io_calib_sgmii",
> + IOSCB_SUBMOD_REG_SIZE);
> + memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
> + &s->io_calib_sgmii);
> +}
> +
> +static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "Microchip PolarFire SoC IOSCB";
> + dc->realize = mchp_pfsoc_ioscb_realize;
> +}
> +
> +static const TypeInfo mchp_pfsoc_ioscb_info = {
> + .name = TYPE_MCHP_PFSOC_IOSCB,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MchpPfSoCIoscbState),
> + .class_init = mchp_pfsoc_ioscb_class_init,
> +};
> +
> +static void mchp_pfsoc_ioscb_register_types(void)
> +{
> + type_register_static(&mchp_pfsoc_ioscb_info);
> +}
> +
> +type_init(mchp_pfsoc_ioscb_register_types)
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 2d79a657e0..6d3c1a3455 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
>
> # RISC-V devices
> softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
> +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c'))
> softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
> softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
> softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
> diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h
> new file mode 100644
> index 0000000000..9235523e33
> --- /dev/null
> +++ b/include/hw/misc/mchp_pfsoc_ioscb.h
> @@ -0,0 +1,50 @@
> +/*
> + * Microchip PolarFire SoC IOSCB module emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + * Bin Meng <bin.meng@windriver.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef MCHP_PFSOC_IOSCB_H
> +#define MCHP_PFSOC_IOSCB_H
> +
> +typedef struct MchpPfSoCIoscbState {
> + SysBusDevice parent;
> + MemoryRegion container;
> + MemoryRegion lane01;
> + MemoryRegion lane23;
> + MemoryRegion ctrl;
> + MemoryRegion cfg;
> + MemoryRegion pll_mss;
> + MemoryRegion cfm_mss;
> + MemoryRegion pll_ddr;
> + MemoryRegion bc_ddr;
> + MemoryRegion io_calib_ddr;
> + MemoryRegion pll_sgmii;
> + MemoryRegion dll_sgmii;
> + MemoryRegion cfm_sgmii;
> + MemoryRegion bc_sgmii;
> + MemoryRegion io_calib_sgmii;
> +} MchpPfSoCIoscbState;
> +
> +#define TYPE_MCHP_PFSOC_IOSCB "mchp.pfsoc.ioscb"
> +
> +#define MCHP_PFSOC_IOSCB(obj) \
> + OBJECT_CHECK(MchpPfSoCIoscbState, (obj), TYPE_MCHP_PFSOC_IOSCB)
> +
> +#endif /* MCHP_PFSOC_IOSCB_H */
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [RESEND PATCH 4/9] hw/riscv: microchip_pfsoc: Connect the IOSCB module
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
` (2 preceding siblings ...)
2020-10-27 14:17 ` [RESEND PATCH 3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support Bin Meng
@ 2020-10-27 14:17 ` Bin Meng
2020-10-27 17:42 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 5/9] hw/misc: Add Microchip PolarFire SoC SYSREG module support Bin Meng
` (4 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2020-10-27 14:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Bin Meng, Atish Patra, Anup Patel, Ivan Griffin
From: Bin Meng <bin.meng@windriver.com>
Previously IOSCB_CFG was created as an unimplemented device. With
the new IOSCB model, its memory range is already covered by the
IOSCB hence remove the previous unimplemented device creation in
the SoC codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/Kconfig | 1 +
hw/riscv/microchip_pfsoc.c | 13 ++++++++-----
include/hw/riscv/microchip_pfsoc.h | 4 +++-
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index c8e50bde99..8f043e38e0 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -5,6 +5,7 @@ config MICROCHIP_PFSOC
bool
select CADENCE_SDHCI
select MCHP_PFSOC_DMC
+ select MCHP_PFSOC_IOSCB
select MCHP_PFSOC_MMUART
select MSI_NONBROKEN
select SIFIVE_CLINT
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 85be2bcde8..05fb5004a1 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -16,6 +16,7 @@
* 5) SiFive Platform DMA (Direct Memory Access Controller)
* 6) GEM (Gigabit Ethernet MAC Controller)
* 7) DMC (DDR Memory Controller)
+ * 8) IOSCB modules
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -100,7 +101,7 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
- [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
+ [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
[MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
};
@@ -144,6 +145,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "sd-controller", &s->sdhci,
TYPE_CADENCE_SDHCI);
+
+ object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB);
}
static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
@@ -355,10 +358,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
envm_data);
- /* IOSCBCFG */
- create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
- memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
- memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
+ /* IOSCB */
+ sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
+ memmap[MICROCHIP_PFSOC_IOSCB].base);
}
static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 5b81e26241..a244ae6d39 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -25,6 +25,7 @@
#include "hw/char/mchp_pfsoc_mmuart.h"
#include "hw/dma/sifive_pdma.h"
#include "hw/misc/mchp_pfsoc_dmc.h"
+#include "hw/misc/mchp_pfsoc_ioscb.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
@@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState {
DeviceState *plic;
MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
MchpPfSoCDdrCfgState ddr_cfg;
+ MchpPfSoCIoscbState ioscb;
MchpPfSoCMMUartState *serial0;
MchpPfSoCMMUartState *serial1;
MchpPfSoCMMUartState *serial2;
@@ -99,7 +101,7 @@ enum {
MICROCHIP_PFSOC_GPIO2,
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
- MICROCHIP_PFSOC_IOSCB_CFG,
+ MICROCHIP_PFSOC_IOSCB,
MICROCHIP_PFSOC_DRAM,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 4/9] hw/riscv: microchip_pfsoc: Connect the IOSCB module
2020-10-27 14:17 ` [RESEND PATCH 4/9] hw/riscv: microchip_pfsoc: Connect the IOSCB module Bin Meng
@ 2020-10-27 17:42 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2020-10-27 17:42 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
On Tue, Oct 27, 2020 at 7:52 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Previously IOSCB_CFG was created as an unimplemented device. With
> the new IOSCB model, its memory range is already covered by the
> IOSCB hence remove the previous unimplemented device creation in
> the SoC codes.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> hw/riscv/Kconfig | 1 +
> hw/riscv/microchip_pfsoc.c | 13 ++++++++-----
> include/hw/riscv/microchip_pfsoc.h | 4 +++-
> 3 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index c8e50bde99..8f043e38e0 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -5,6 +5,7 @@ config MICROCHIP_PFSOC
> bool
> select CADENCE_SDHCI
> select MCHP_PFSOC_DMC
> + select MCHP_PFSOC_IOSCB
> select MCHP_PFSOC_MMUART
> select MSI_NONBROKEN
> select SIFIVE_CLINT
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 85be2bcde8..05fb5004a1 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -16,6 +16,7 @@
> * 5) SiFive Platform DMA (Direct Memory Access Controller)
> * 6) GEM (Gigabit Ethernet MAC Controller)
> * 7) DMC (DDR Memory Controller)
> + * 8) IOSCB modules
> *
> * This board currently generates devicetree dynamically that indicates at least
> * two harts and up to five harts.
> @@ -100,7 +101,7 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> - [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
> + [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
This one matches the docs! :)
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> };
>
> @@ -144,6 +145,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
>
> object_initialize_child(obj, "sd-controller", &s->sdhci,
> TYPE_CADENCE_SDHCI);
> +
> + object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB);
> }
>
> static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> @@ -355,10 +358,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
> envm_data);
>
> - /* IOSCBCFG */
> - create_unimplemented_device("microchip.pfsoc.ioscb.cfg",
> - memmap[MICROCHIP_PFSOC_IOSCB_CFG].base,
> - memmap[MICROCHIP_PFSOC_IOSCB_CFG].size);
> + /* IOSCB */
> + sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
> + memmap[MICROCHIP_PFSOC_IOSCB].base);
> }
>
> static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index 5b81e26241..a244ae6d39 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -25,6 +25,7 @@
> #include "hw/char/mchp_pfsoc_mmuart.h"
> #include "hw/dma/sifive_pdma.h"
> #include "hw/misc/mchp_pfsoc_dmc.h"
> +#include "hw/misc/mchp_pfsoc_ioscb.h"
> #include "hw/net/cadence_gem.h"
> #include "hw/sd/cadence_sdhci.h"
>
> @@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState {
> DeviceState *plic;
> MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy;
> MchpPfSoCDdrCfgState ddr_cfg;
> + MchpPfSoCIoscbState ioscb;
> MchpPfSoCMMUartState *serial0;
> MchpPfSoCMMUartState *serial1;
> MchpPfSoCMMUartState *serial2;
> @@ -99,7 +101,7 @@ enum {
> MICROCHIP_PFSOC_GPIO2,
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> - MICROCHIP_PFSOC_IOSCB_CFG,
> + MICROCHIP_PFSOC_IOSCB,
> MICROCHIP_PFSOC_DRAM,
> };
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [RESEND PATCH 5/9] hw/misc: Add Microchip PolarFire SoC SYSREG module support
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
` (3 preceding siblings ...)
2020-10-27 14:17 ` [RESEND PATCH 4/9] hw/riscv: microchip_pfsoc: Connect the IOSCB module Bin Meng
@ 2020-10-27 14:17 ` Bin Meng
2020-10-27 20:51 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module Bin Meng
` (3 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2020-10-27 14:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Bin Meng, Atish Patra, Anup Patel, Ivan Griffin
From: Bin Meng <bin.meng@windriver.com>
This creates a minimum model for Microchip PolarFire SoC SYSREG
module. It only implements the ENVM_CR register to tell guest
software that eNVM is running at the configured divider rate.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
MAINTAINERS | 2 +
hw/misc/Kconfig | 3 +
hw/misc/mchp_pfsoc_sysreg.c | 99 +++++++++++++++++++++++++++++
hw/misc/meson.build | 1 +
include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++++++++
5 files changed, 144 insertions(+)
create mode 100644 hw/misc/mchp_pfsoc_sysreg.c
create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h
diff --git a/MAINTAINERS b/MAINTAINERS
index ebbc62a62f..e82f2b35e8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1328,10 +1328,12 @@ F: hw/riscv/microchip_pfsoc.c
F: hw/char/mchp_pfsoc_mmuart.c
F: hw/misc/mchp_pfsoc_dmc.c
F: hw/misc/mchp_pfsoc_ioscb.c
+F: hw/misc/mchp_pfsoc_sysreg.c
F: include/hw/riscv/microchip_pfsoc.h
F: include/hw/char/mchp_pfsoc_mmuart.h
F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
+F: include/hw/misc/mchp_pfsoc_sysreg.h
RX Machines
-----------
diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 3db15e06b4..546e2fab9b 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -140,6 +140,9 @@ config MCHP_PFSOC_DMC
config MCHP_PFSOC_IOSCB
bool
+config MCHP_PFSOC_SYSREG
+ bool
+
config SIFIVE_TEST
bool
diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
new file mode 100644
index 0000000000..248a313345
--- /dev/null
+++ b/hw/misc/mchp_pfsoc_sysreg.c
@@ -0,0 +1,99 @@
+/*
+ * Microchip PolarFire SoC SYSREG module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "hw/misc/mchp_pfsoc_sysreg.h"
+
+#define ENVM_CR 0xb8
+
+static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ uint32_t val = 0;
+
+ switch (offset) {
+ case ENVM_CR:
+ /* Indicate the eNVM is running at the configured divider rate */
+ val = BIT(6);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
+ "(size %d, offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, offset);
+ break;
+ }
+
+ return val;
+}
+
+static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
+ "(size %d, value 0x%" PRIx64
+ ", offset 0x%" HWADDR_PRIx ")\n",
+ __func__, size, value, offset);
+}
+
+static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
+ .read = mchp_pfsoc_sysreg_read,
+ .write = mchp_pfsoc_sysreg_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
+{
+ MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev);
+
+ memory_region_init_io(&s->sysreg, OBJECT(dev),
+ &mchp_pfsoc_sysreg_ops, s,
+ "mchp.pfsoc.sysreg",
+ MCHP_PFSOC_SYSREG_REG_SIZE);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
+}
+
+static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "Microchip PolarFire SoC SYSREG module";
+ dc->realize = mchp_pfsoc_sysreg_realize;
+}
+
+static const TypeInfo mchp_pfsoc_sysreg_info = {
+ .name = TYPE_MCHP_PFSOC_SYSREG,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MchpPfSoCSysregState),
+ .class_init = mchp_pfsoc_sysreg_class_init,
+};
+
+static void mchp_pfsoc_sysreg_register_types(void)
+{
+ type_register_static(&mchp_pfsoc_sysreg_info);
+}
+
+type_init(mchp_pfsoc_sysreg_register_types)
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index 6d3c1a3455..8ed75254c4 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -24,6 +24,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
# RISC-V devices
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c'))
+softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h
new file mode 100644
index 0000000000..546ba68f6a
--- /dev/null
+++ b/include/hw/misc/mchp_pfsoc_sysreg.h
@@ -0,0 +1,39 @@
+/*
+ * Microchip PolarFire SoC SYSREG module emulation
+ *
+ * Copyright (c) 2020 Wind River Systems, Inc.
+ *
+ * Author:
+ * Bin Meng <bin.meng@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 or
+ * (at your option) version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MCHP_PFSOC_SYSREG_H
+#define MCHP_PFSOC_SYSREG_H
+
+#define MCHP_PFSOC_SYSREG_REG_SIZE 0x2000
+
+typedef struct MchpPfSoCSysregState {
+ SysBusDevice parent;
+ MemoryRegion sysreg;
+} MchpPfSoCSysregState;
+
+#define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg"
+
+#define MCHP_PFSOC_SYSREG(obj) \
+ OBJECT_CHECK(MchpPfSoCSysregState, (obj), \
+ TYPE_MCHP_PFSOC_SYSREG)
+
+#endif /* MCHP_PFSOC_SYSREG_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 5/9] hw/misc: Add Microchip PolarFire SoC SYSREG module support
2020-10-27 14:17 ` [RESEND PATCH 5/9] hw/misc: Add Microchip PolarFire SoC SYSREG module support Bin Meng
@ 2020-10-27 20:51 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2020-10-27 20:51 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
On Tue, Oct 27, 2020 at 7:56 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> This creates a minimum model for Microchip PolarFire SoC SYSREG
> module. It only implements the ENVM_CR register to tell guest
> software that eNVM is running at the configured divider rate.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> MAINTAINERS | 2 +
> hw/misc/Kconfig | 3 +
> hw/misc/mchp_pfsoc_sysreg.c | 99 +++++++++++++++++++++++++++++
> hw/misc/meson.build | 1 +
> include/hw/misc/mchp_pfsoc_sysreg.h | 39 ++++++++++++
> 5 files changed, 144 insertions(+)
> create mode 100644 hw/misc/mchp_pfsoc_sysreg.c
> create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ebbc62a62f..e82f2b35e8 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1328,10 +1328,12 @@ F: hw/riscv/microchip_pfsoc.c
> F: hw/char/mchp_pfsoc_mmuart.c
> F: hw/misc/mchp_pfsoc_dmc.c
> F: hw/misc/mchp_pfsoc_ioscb.c
> +F: hw/misc/mchp_pfsoc_sysreg.c
> F: include/hw/riscv/microchip_pfsoc.h
> F: include/hw/char/mchp_pfsoc_mmuart.h
> F: include/hw/misc/mchp_pfsoc_dmc.h
> F: include/hw/misc/mchp_pfsoc_ioscb.h
> +F: include/hw/misc/mchp_pfsoc_sysreg.h
>
> RX Machines
> -----------
> diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
> index 3db15e06b4..546e2fab9b 100644
> --- a/hw/misc/Kconfig
> +++ b/hw/misc/Kconfig
> @@ -140,6 +140,9 @@ config MCHP_PFSOC_DMC
> config MCHP_PFSOC_IOSCB
> bool
>
> +config MCHP_PFSOC_SYSREG
> + bool
> +
> config SIFIVE_TEST
> bool
>
> diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c
> new file mode 100644
> index 0000000000..248a313345
> --- /dev/null
> +++ b/hw/misc/mchp_pfsoc_sysreg.c
> @@ -0,0 +1,99 @@
> +/*
> + * Microchip PolarFire SoC SYSREG module emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + * Bin Meng <bin.meng@windriver.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qemu/bitops.h"
> +#include "qemu/log.h"
> +#include "qapi/error.h"
> +#include "hw/hw.h"
> +#include "hw/sysbus.h"
> +#include "hw/misc/mchp_pfsoc_sysreg.h"
> +
> +#define ENVM_CR 0xb8
> +
> +static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + uint32_t val = 0;
> +
> + switch (offset) {
> + case ENVM_CR:
> + /* Indicate the eNVM is running at the configured divider rate */
> + val = BIT(6);
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
> + "(size %d, offset 0x%" HWADDR_PRIx ")\n",
> + __func__, size, offset);
> + break;
> + }
> +
> + return val;
> +}
> +
> +static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
> + uint64_t value, unsigned size)
> +{
> + qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
> + "(size %d, value 0x%" PRIx64
> + ", offset 0x%" HWADDR_PRIx ")\n",
> + __func__, size, value, offset);
> +}
> +
> +static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
> + .read = mchp_pfsoc_sysreg_read,
> + .write = mchp_pfsoc_sysreg_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> +static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
> +{
> + MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev);
> +
> + memory_region_init_io(&s->sysreg, OBJECT(dev),
> + &mchp_pfsoc_sysreg_ops, s,
> + "mchp.pfsoc.sysreg",
> + MCHP_PFSOC_SYSREG_REG_SIZE);
> + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
> +}
> +
> +static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->desc = "Microchip PolarFire SoC SYSREG module";
> + dc->realize = mchp_pfsoc_sysreg_realize;
> +}
> +
> +static const TypeInfo mchp_pfsoc_sysreg_info = {
> + .name = TYPE_MCHP_PFSOC_SYSREG,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(MchpPfSoCSysregState),
> + .class_init = mchp_pfsoc_sysreg_class_init,
> +};
> +
> +static void mchp_pfsoc_sysreg_register_types(void)
> +{
> + type_register_static(&mchp_pfsoc_sysreg_info);
> +}
> +
> +type_init(mchp_pfsoc_sysreg_register_types)
> diff --git a/hw/misc/meson.build b/hw/misc/meson.build
> index 6d3c1a3455..8ed75254c4 100644
> --- a/hw/misc/meson.build
> +++ b/hw/misc/meson.build
> @@ -24,6 +24,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
> # RISC-V devices
> softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c'))
> softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_IOSCB', if_true: files('mchp_pfsoc_ioscb.c'))
> +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_SYSREG', if_true: files('mchp_pfsoc_sysreg.c'))
> softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c'))
> softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c'))
> softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c'))
> diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h
> new file mode 100644
> index 0000000000..546ba68f6a
> --- /dev/null
> +++ b/include/hw/misc/mchp_pfsoc_sysreg.h
> @@ -0,0 +1,39 @@
> +/*
> + * Microchip PolarFire SoC SYSREG module emulation
> + *
> + * Copyright (c) 2020 Wind River Systems, Inc.
> + *
> + * Author:
> + * Bin Meng <bin.meng@windriver.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 or
> + * (at your option) version 3 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef MCHP_PFSOC_SYSREG_H
> +#define MCHP_PFSOC_SYSREG_H
> +
> +#define MCHP_PFSOC_SYSREG_REG_SIZE 0x2000
> +
> +typedef struct MchpPfSoCSysregState {
> + SysBusDevice parent;
> + MemoryRegion sysreg;
> +} MchpPfSoCSysregState;
> +
> +#define TYPE_MCHP_PFSOC_SYSREG "mchp.pfsoc.sysreg"
> +
> +#define MCHP_PFSOC_SYSREG(obj) \
> + OBJECT_CHECK(MchpPfSoCSysregState, (obj), \
> + TYPE_MCHP_PFSOC_SYSREG)
> +
> +#endif /* MCHP_PFSOC_SYSREG_H */
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
` (4 preceding siblings ...)
2020-10-27 14:17 ` [RESEND PATCH 5/9] hw/misc: Add Microchip PolarFire SoC SYSREG module support Bin Meng
@ 2020-10-27 14:17 ` Bin Meng
2020-10-27 17:42 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory Bin Meng
` (2 subsequent siblings)
8 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2020-10-27 14:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Bin Meng, Atish Patra, Anup Patel, Ivan Griffin
From: Bin Meng <bin.meng@windriver.com>
Previously SYSREG was created as an unimplemented device. Now that
we have a simple SYSREG module, connect it.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/Kconfig | 1 +
hw/riscv/microchip_pfsoc.c | 9 ++++++---
include/hw/riscv/microchip_pfsoc.h | 2 ++
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 8f043e38e0..facb0cbacc 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -7,6 +7,7 @@ config MICROCHIP_PFSOC
select MCHP_PFSOC_DMC
select MCHP_PFSOC_IOSCB
select MCHP_PFSOC_MMUART
+ select MCHP_PFSOC_SYSREG
select MSI_NONBROKEN
select SIFIVE_CLINT
select SIFIVE_PDMA
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 05fb5004a1..69117c6000 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -135,6 +135,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma-controller", &s->dma,
TYPE_SIFIVE_PDMA);
+ object_initialize_child(obj, "sysreg", &s->sysreg,
+ TYPE_MCHP_PFSOC_SYSREG);
+
object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
@@ -262,9 +265,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
}
/* SYSREG */
- create_unimplemented_device("microchip.pfsoc.sysreg",
- memmap[MICROCHIP_PFSOC_SYSREG].base,
- memmap[MICROCHIP_PFSOC_SYSREG].size);
+ sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
+ memmap[MICROCHIP_PFSOC_SYSREG].base);
/* MPUCFG */
create_unimplemented_device("microchip.pfsoc.mpucfg",
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index a244ae6d39..245c82db61 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -26,6 +26,7 @@
#include "hw/dma/sifive_pdma.h"
#include "hw/misc/mchp_pfsoc_dmc.h"
#include "hw/misc/mchp_pfsoc_ioscb.h"
+#include "hw/misc/mchp_pfsoc_sysreg.h"
#include "hw/net/cadence_gem.h"
#include "hw/sd/cadence_sdhci.h"
@@ -47,6 +48,7 @@ typedef struct MicrochipPFSoCState {
MchpPfSoCMMUartState *serial2;
MchpPfSoCMMUartState *serial3;
MchpPfSoCMMUartState *serial4;
+ MchpPfSoCSysregState sysreg;
SiFivePDMAState dma;
CadenceGEMState gem0;
CadenceGEMState gem1;
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module
2020-10-27 14:17 ` [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module Bin Meng
@ 2020-10-27 17:42 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2020-10-27 17:42 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
On Tue, Oct 27, 2020 at 7:43 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Previously SYSREG was created as an unimplemented device. Now that
> we have a simple SYSREG module, connect it.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/Kconfig | 1 +
> hw/riscv/microchip_pfsoc.c | 9 ++++++---
> include/hw/riscv/microchip_pfsoc.h | 2 ++
> 3 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 8f043e38e0..facb0cbacc 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -7,6 +7,7 @@ config MICROCHIP_PFSOC
> select MCHP_PFSOC_DMC
> select MCHP_PFSOC_IOSCB
> select MCHP_PFSOC_MMUART
> + select MCHP_PFSOC_SYSREG
> select MSI_NONBROKEN
> select SIFIVE_CLINT
> select SIFIVE_PDMA
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 05fb5004a1..69117c6000 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -135,6 +135,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
> object_initialize_child(obj, "dma-controller", &s->dma,
> TYPE_SIFIVE_PDMA);
>
> + object_initialize_child(obj, "sysreg", &s->sysreg,
> + TYPE_MCHP_PFSOC_SYSREG);
> +
> object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
> TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
> object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
> @@ -262,9 +265,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> }
>
> /* SYSREG */
> - create_unimplemented_device("microchip.pfsoc.sysreg",
> - memmap[MICROCHIP_PFSOC_SYSREG].base,
> - memmap[MICROCHIP_PFSOC_SYSREG].size);
> + sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
> + memmap[MICROCHIP_PFSOC_SYSREG].base);
>
> /* MPUCFG */
> create_unimplemented_device("microchip.pfsoc.mpucfg",
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index a244ae6d39..245c82db61 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -26,6 +26,7 @@
> #include "hw/dma/sifive_pdma.h"
> #include "hw/misc/mchp_pfsoc_dmc.h"
> #include "hw/misc/mchp_pfsoc_ioscb.h"
> +#include "hw/misc/mchp_pfsoc_sysreg.h"
> #include "hw/net/cadence_gem.h"
> #include "hw/sd/cadence_sdhci.h"
>
> @@ -47,6 +48,7 @@ typedef struct MicrochipPFSoCState {
> MchpPfSoCMMUartState *serial2;
> MchpPfSoCMMUartState *serial3;
> MchpPfSoCMMUartState *serial4;
> + MchpPfSoCSysregState sysreg;
> SiFivePDMAState dma;
> CadenceGEMState gem0;
> CadenceGEMState gem1;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
` (5 preceding siblings ...)
2020-10-27 14:17 ` [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module Bin Meng
@ 2020-10-27 14:17 ` Bin Meng
2020-10-27 17:30 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map Bin Meng
2020-10-27 14:17 ` [RESEND PATCH 9/9] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Bin Meng
8 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2020-10-27 14:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Bin Meng, Atish Patra, Anup Patel, Ivan Griffin
From: Bin Meng <bin.meng@windriver.com>
Somehow HSS needs to access address 0 [1] for the DDR calibration data
which is in the chipset's debug memory. Let's map the debug memory.
[1] See the config_copy() calls in various places in ddr_setup() in
the HSS source codes.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/microchip_pfsoc.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 69117c6000..b9c2f73e7c 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -158,6 +158,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
MemoryRegion *system_memory = get_system_memory();
+ MemoryRegion *debug_mem = g_new(MemoryRegion, 1);
MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
MemoryRegion *envm_data = g_new(MemoryRegion, 1);
@@ -177,6 +178,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
+ /* Debug */
+ memory_region_init_ram(debug_mem, NULL, "microchip.pfsoc.debug_mem",
+ memmap[MICROCHIP_PFSOC_DEBUG].size, &error_fatal);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_DEBUG].base,
+ debug_mem);
+
/* E51 DTIM */
memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory
2020-10-27 14:17 ` [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory Bin Meng
@ 2020-10-27 17:30 ` Alistair Francis
2020-10-28 2:08 ` Bin Meng
0 siblings, 1 reply; 23+ messages in thread
From: Alistair Francis @ 2020-10-27 17:30 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
On Tue, Oct 27, 2020 at 7:53 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Somehow HSS needs to access address 0 [1] for the DDR calibration data
> which is in the chipset's debug memory. Let's map the debug memory.
>
> [1] See the config_copy() calls in various places in ddr_setup() in
> the HSS source codes.
Really? This is reserved memory that they just read and write to? That's crazy.
If we really need this can you add a comment saying that the
documentation is wrong (again) and that this needs to be here.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> hw/riscv/microchip_pfsoc.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 69117c6000..b9c2f73e7c 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -158,6 +158,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
> const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
> MemoryRegion *system_memory = get_system_memory();
> + MemoryRegion *debug_mem = g_new(MemoryRegion, 1);
> MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *envm_data = g_new(MemoryRegion, 1);
> @@ -177,6 +178,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
> qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
>
> + /* Debug */
This doesn't seem right.
Debug should start at 0x0000_0100 (it seems like what is currently in
tree is wrong).
Address 0x00 is marked as reserved in the documentation.
Do you mind updating the memory map to fix the debug address? Then
just add a reserved region as well.
Alistair
> + memory_region_init_ram(debug_mem, NULL, "microchip.pfsoc.debug_mem",
> + memmap[MICROCHIP_PFSOC_DEBUG].size, &error_fatal);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_DEBUG].base,
> + debug_mem);
> +
> /* E51 DTIM */
> memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
> memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory
2020-10-27 17:30 ` Alistair Francis
@ 2020-10-28 2:08 ` Bin Meng
0 siblings, 0 replies; 23+ messages in thread
From: Bin Meng @ 2020-10-28 2:08 UTC (permalink / raw)
To: Alistair Francis
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
Hi Alistair,
On Wed, Oct 28, 2020 at 1:42 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Oct 27, 2020 at 7:53 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > Somehow HSS needs to access address 0 [1] for the DDR calibration data
> > which is in the chipset's debug memory. Let's map the debug memory.
> >
> > [1] See the config_copy() calls in various places in ddr_setup() in
> > the HSS source codes.
>
> Really? This is reserved memory that they just read and write to? That's crazy.
Yes, that's crazy.
>
> If we really need this can you add a comment saying that the
> documentation is wrong (again) and that this needs to be here.
>
I will try to only map 256 bytes to see how that goes.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > ---
> >
> > hw/riscv/microchip_pfsoc.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
Regards,
Bin
^ permalink raw reply [flat|nested] 23+ messages in thread
* [RESEND PATCH 8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
` (6 preceding siblings ...)
2020-10-27 14:17 ` [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory Bin Meng
@ 2020-10-27 14:17 ` Bin Meng
2020-10-27 20:55 ` Alistair Francis
2020-10-27 14:17 ` [RESEND PATCH 9/9] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Bin Meng
8 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2020-10-27 14:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Bin Meng, Atish Patra, Anup Patel, Ivan Griffin
From: Bin Meng <bin.meng@windriver.com>
When system memory is larger than 1 GiB (high memory), PolarFire SoC
maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is
aliased to the same 1 GiB low memory with different cache attributes.
At present QEMU maps the system memory contiguously from 0x8000_0000.
This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is
the alias to the high memory, and even physical memory is only 1 GiB,
the HSS codes still tries to probe the high memory alias address.
It seems there is no issue on the real hardware, so we will have to
take that into the consideration in our emulation.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/microchip_pfsoc.c | 49 +++++++++++++++++++++++++++---
include/hw/riscv/microchip_pfsoc.h | 5 ++-
2 files changed, 48 insertions(+), 6 deletions(-)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index b9c2f73e7c..c595c9c967 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -102,7 +102,10 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
[MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
- [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
+ [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
+ [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
+ [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
+ [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
};
static void microchip_pfsoc_soc_instance_init(Object *obj)
@@ -405,7 +408,11 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
+ MemoryRegion *mem_low = g_new(MemoryRegion, 1);
+ MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
+ MemoryRegion *mem_high = g_new(MemoryRegion, 1);
+ MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
+ uint64_t mem_high_size;
DriveInfo *dinfo = drive_get_next(IF_SD);
/* Sanity check on RAM size */
@@ -422,10 +429,42 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
/* Register RAM */
- memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
- machine->ram_size, &error_fatal);
+ memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
+ memmap[MICROCHIP_PFSOC_DRAM_LO].size,
+ &error_fatal);
+ memory_region_init_alias(mem_low_alias, NULL,
+ "microchip.icicle.kit.ram_low.alias",
+ mem_low, 0,
+ memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_DRAM_LO].base,
+ mem_low);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
+ mem_low_alias);
+
+ /*
+ * Map 1 GiB high memory because HSS will do memory test against the high
+ * memory address range regardless of physical memory installed.
+ *
+ * See memory_tests() in mss_ddr.c in the HSS source code.
+ */
+ mem_high_size = machine->ram_size - 1 * GiB;
+ if (mem_high_size < 1 * GiB) {
+ mem_high_size = 1 * GiB;
+ }
+
+ memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
+ mem_high_size, &error_fatal);
+ memory_region_init_alias(mem_high_alias, NULL,
+ "microchip.icicle.kit.ram_high.alias",
+ mem_high, 0, mem_high_size);
+ memory_region_add_subregion(system_memory,
+ memmap[MICROCHIP_PFSOC_DRAM_HI].base,
+ mem_high);
memory_region_add_subregion(system_memory,
- memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
+ memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
+ mem_high_alias);
/* Load the firmware */
riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 245c82db61..dc05688d94 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -104,7 +104,10 @@ enum {
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
MICROCHIP_PFSOC_IOSCB,
- MICROCHIP_PFSOC_DRAM,
+ MICROCHIP_PFSOC_DRAM_LO,
+ MICROCHIP_PFSOC_DRAM_LO_ALIAS,
+ MICROCHIP_PFSOC_DRAM_HI,
+ MICROCHIP_PFSOC_DRAM_HI_ALIAS
};
enum {
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map
2020-10-27 14:17 ` [RESEND PATCH 8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map Bin Meng
@ 2020-10-27 20:55 ` Alistair Francis
2020-10-28 2:06 ` Bin Meng
0 siblings, 1 reply; 23+ messages in thread
From: Alistair Francis @ 2020-10-27 20:55 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
On Tue, Oct 27, 2020 at 7:48 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> When system memory is larger than 1 GiB (high memory), PolarFire SoC
> maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is
> aliased to the same 1 GiB low memory with different cache attributes.
>
> At present QEMU maps the system memory contiguously from 0x8000_0000.
> This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is
> the alias to the high memory, and even physical memory is only 1 GiB,
> the HSS codes still tries to probe the high memory alias address.
> It seems there is no issue on the real hardware, so we will have to
> take that into the consideration in our emulation.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> hw/riscv/microchip_pfsoc.c | 49 +++++++++++++++++++++++++++---
> include/hw/riscv/microchip_pfsoc.h | 5 ++-
> 2 files changed, 48 insertions(+), 6 deletions(-)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index b9c2f73e7c..c595c9c967 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -102,7 +102,10 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
> - [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> + [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
> + [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
> + [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
> + [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
> };
>
> static void microchip_pfsoc_soc_instance_init(Object *obj)
> @@ -405,7 +408,11 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
> MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
> MemoryRegion *system_memory = get_system_memory();
> - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> + MemoryRegion *mem_low = g_new(MemoryRegion, 1);
> + MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
> + MemoryRegion *mem_high = g_new(MemoryRegion, 1);
> + MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
> + uint64_t mem_high_size;
> DriveInfo *dinfo = drive_get_next(IF_SD);
>
> /* Sanity check on RAM size */
> @@ -422,10 +429,42 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
>
> /* Register RAM */
> - memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
> - machine->ram_size, &error_fatal);
> + memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
> + memmap[MICROCHIP_PFSOC_DRAM_LO].size,
> + &error_fatal);
> + memory_region_init_alias(mem_low_alias, NULL,
> + "microchip.icicle.kit.ram_low.alias",
> + mem_low, 0,
> + memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_DRAM_LO].base,
> + mem_low);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
> + mem_low_alias);
> +
> + /*
> + * Map 1 GiB high memory because HSS will do memory test against the high
> + * memory address range regardless of physical memory installed.
> + *
> + * See memory_tests() in mss_ddr.c in the HSS source code.
> + */
> + mem_high_size = machine->ram_size - 1 * GiB;
> + if (mem_high_size < 1 * GiB) {
> + mem_high_size = 1 * GiB;
This now means that the machine requires at least 2GB of memory!
Can you increase the default_ram_size so we will return an error if
the user specified less than 2GB instead of just increasing it without
their knowledge?
Alistair
> + }
> +
> + memory_region_init_ram(mem_high, NULL, "microchip.icicle.kit.ram_high",
> + mem_high_size, &error_fatal);
> + memory_region_init_alias(mem_high_alias, NULL,
> + "microchip.icicle.kit.ram_high.alias",
> + mem_high, 0, mem_high_size);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_DRAM_HI].base,
> + mem_high);
> memory_region_add_subregion(system_memory,
> - memmap[MICROCHIP_PFSOC_DRAM].base, main_mem);
> + memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
> + mem_high_alias);
>
> /* Load the firmware */
> riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL);
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index 245c82db61..dc05688d94 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -104,7 +104,10 @@ enum {
> MICROCHIP_PFSOC_ENVM_CFG,
> MICROCHIP_PFSOC_ENVM_DATA,
> MICROCHIP_PFSOC_IOSCB,
> - MICROCHIP_PFSOC_DRAM,
> + MICROCHIP_PFSOC_DRAM_LO,
> + MICROCHIP_PFSOC_DRAM_LO_ALIAS,
> + MICROCHIP_PFSOC_DRAM_HI,
> + MICROCHIP_PFSOC_DRAM_HI_ALIAS
> };
>
> enum {
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map
2020-10-27 20:55 ` Alistair Francis
@ 2020-10-28 2:06 ` Bin Meng
0 siblings, 0 replies; 23+ messages in thread
From: Bin Meng @ 2020-10-28 2:06 UTC (permalink / raw)
To: Alistair Francis
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
Hi Alistair,
On Wed, Oct 28, 2020 at 5:07 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Oct 27, 2020 at 7:48 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > When system memory is larger than 1 GiB (high memory), PolarFire SoC
> > maps it at address 0x10_0000_0000. Address 0xC000_0000 and above is
> > aliased to the same 1 GiB low memory with different cache attributes.
> >
> > At present QEMU maps the system memory contiguously from 0x8000_0000.
> > This corrects the wrong QEMU logic. Note address 0x14_0000_0000 is
> > the alias to the high memory, and even physical memory is only 1 GiB,
> > the HSS codes still tries to probe the high memory alias address.
> > It seems there is no issue on the real hardware, so we will have to
> > take that into the consideration in our emulation.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > ---
> >
> > hw/riscv/microchip_pfsoc.c | 49 +++++++++++++++++++++++++++---
> > include/hw/riscv/microchip_pfsoc.h | 5 ++-
> > 2 files changed, 48 insertions(+), 6 deletions(-)
> >
> > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> > index b9c2f73e7c..c595c9c967 100644
> > --- a/hw/riscv/microchip_pfsoc.c
> > +++ b/hw/riscv/microchip_pfsoc.c
> > @@ -102,7 +102,10 @@ static const struct MemmapEntry {
> > [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
> > [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
> > [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
> > - [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 },
> > + [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
> > + [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
> > + [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
> > + [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
> > };
> >
> > static void microchip_pfsoc_soc_instance_init(Object *obj)
> > @@ -405,7 +408,11 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> > const struct MemmapEntry *memmap = microchip_pfsoc_memmap;
> > MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
> > MemoryRegion *system_memory = get_system_memory();
> > - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
> > + MemoryRegion *mem_low = g_new(MemoryRegion, 1);
> > + MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
> > + MemoryRegion *mem_high = g_new(MemoryRegion, 1);
> > + MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
> > + uint64_t mem_high_size;
> > DriveInfo *dinfo = drive_get_next(IF_SD);
> >
> > /* Sanity check on RAM size */
> > @@ -422,10 +429,42 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
> > qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
> >
> > /* Register RAM */
> > - memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram",
> > - machine->ram_size, &error_fatal);
> > + memory_region_init_ram(mem_low, NULL, "microchip.icicle.kit.ram_low",
> > + memmap[MICROCHIP_PFSOC_DRAM_LO].size,
> > + &error_fatal);
> > + memory_region_init_alias(mem_low_alias, NULL,
> > + "microchip.icicle.kit.ram_low.alias",
> > + mem_low, 0,
> > + memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].size);
> > + memory_region_add_subregion(system_memory,
> > + memmap[MICROCHIP_PFSOC_DRAM_LO].base,
> > + mem_low);
> > + memory_region_add_subregion(system_memory,
> > + memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
> > + mem_low_alias);
> > +
> > + /*
> > + * Map 1 GiB high memory because HSS will do memory test against the high
> > + * memory address range regardless of physical memory installed.
> > + *
> > + * See memory_tests() in mss_ddr.c in the HSS source code.
> > + */
> > + mem_high_size = machine->ram_size - 1 * GiB;
> > + if (mem_high_size < 1 * GiB) {
> > + mem_high_size = 1 * GiB;
>
> This now means that the machine requires at least 2GB of memory!
Yes, unfortunately :(
>
> Can you increase the default_ram_size so we will return an error if
> the user specified less than 2GB instead of just increasing it without
> their knowledge?
>
Sure.
Regards,
Bin
^ permalink raw reply [flat|nested] 23+ messages in thread
* [RESEND PATCH 9/9] hw/riscv: microchip_pfsoc: Hook the I2C1 controller
2020-10-27 14:17 [RESEND PATCH 0/9] hw/riscv: microchip_pfsoc: Support factory HSS boot out of the box Bin Meng
` (7 preceding siblings ...)
2020-10-27 14:17 ` [RESEND PATCH 8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map Bin Meng
@ 2020-10-27 14:17 ` Bin Meng
2020-10-27 17:19 ` Alistair Francis
8 siblings, 1 reply; 23+ messages in thread
From: Bin Meng @ 2020-10-27 14:17 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
Cc: Bin Meng, Atish Patra, Anup Patel, Ivan Griffin
From: Bin Meng <bin.meng@windriver.com>
The latest SD card image [1] released by Microchip ships a Linux
kernel with built-in PolarFire SoC I2C driver support. The device
tree file includes the description for the I2C1 node hence kernel
tries to probe the I2C1 device during boot.
It is enough to create an unimplemented device for I2C1 to allow
the kernel to continue booting to the shell.
[1] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/microchip_pfsoc.c | 6 ++++++
include/hw/riscv/microchip_pfsoc.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index c595c9c967..4e878c2836 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -94,6 +94,7 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
[MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
[MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
+ [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
[MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
[MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
[MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
@@ -324,6 +325,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
serial_hd(4));
+ /* I2C1 */
+ create_unimplemented_device("microchip.pfsoc.i2c1",
+ memmap[MICROCHIP_PFSOC_I2C1].base,
+ memmap[MICROCHIP_PFSOC_I2C1].size);
+
/* GEMs */
nd = &nd_table[0];
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index dc05688d94..74ae789c03 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -96,6 +96,7 @@ enum {
MICROCHIP_PFSOC_MMUART2,
MICROCHIP_PFSOC_MMUART3,
MICROCHIP_PFSOC_MMUART4,
+ MICROCHIP_PFSOC_I2C1,
MICROCHIP_PFSOC_GEM0,
MICROCHIP_PFSOC_GEM1,
MICROCHIP_PFSOC_GPIO0,
--
2.25.1
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [RESEND PATCH 9/9] hw/riscv: microchip_pfsoc: Hook the I2C1 controller
2020-10-27 14:17 ` [RESEND PATCH 9/9] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Bin Meng
@ 2020-10-27 17:19 ` Alistair Francis
0 siblings, 0 replies; 23+ messages in thread
From: Alistair Francis @ 2020-10-27 17:19 UTC (permalink / raw)
To: Bin Meng
Cc: Bin Meng, open list:RISC-V, Anup Patel,
qemu-devel@nongnu.org Developers, Atish Patra, Alistair Francis,
Ivan Griffin
On Tue, Oct 27, 2020 at 7:55 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The latest SD card image [1] released by Microchip ships a Linux
> kernel with built-in PolarFire SoC I2C driver support. The device
> tree file includes the description for the I2C1 node hence kernel
> tries to probe the I2C1 device during boot.
>
> It is enough to create an unimplemented device for I2C1 to allow
> the kernel to continue booting to the shell.
>
> [1] ftp://ftpsoc.microsemi.com/outgoing/core-image-minimal-dev-icicle-kit-es-sd-20201009141623.rootfs.wic.gz
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
>
> ---
>
> hw/riscv/microchip_pfsoc.c | 6 ++++++
> include/hw/riscv/microchip_pfsoc.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index c595c9c967..4e878c2836 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -94,6 +94,7 @@ static const struct MemmapEntry {
> [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
> [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
> [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
> + [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
> [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
> [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
> [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
> @@ -324,6 +325,11 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
> serial_hd(4));
>
> + /* I2C1 */
> + create_unimplemented_device("microchip.pfsoc.i2c1",
> + memmap[MICROCHIP_PFSOC_I2C1].base,
> + memmap[MICROCHIP_PFSOC_I2C1].size);
> +
> /* GEMs */
>
> nd = &nd_table[0];
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index dc05688d94..74ae789c03 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -96,6 +96,7 @@ enum {
> MICROCHIP_PFSOC_MMUART2,
> MICROCHIP_PFSOC_MMUART3,
> MICROCHIP_PFSOC_MMUART4,
> + MICROCHIP_PFSOC_I2C1,
> MICROCHIP_PFSOC_GEM0,
> MICROCHIP_PFSOC_GEM1,
> MICROCHIP_PFSOC_GPIO0,
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread