[PULL v2 00/19] riscv-to-apply queue

[Alistair Francis <alistair.francis@wdc.com>]

The following changes since commit 83851c7c60c90e9fb6a23ff48076387a77bc33cd:

  Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2020-10-27-v3-tag' into staging (2020-11-03 12:47:58 +0000)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201103

for you to fetch changes up to 422819776101520cb56658ee5facf926526cf870:

  target/riscv/csr.c : add space before the open parenthesis '(' (2020-11-03 07:17:23 -0800)

----------------------------------------------------------------
This series adds support for migration to RISC-V QEMU and expands the
Microchip PFSoC to allow unmodified HSS and Linux boots.

----------------------------------------------------------------
Anup Patel (2):
      hw/riscv: sifive_u: Allow passing custom DTB
      hw/riscv: virt: Allow passing custom DTB

Bin Meng (10):
      hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps
      hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
      hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
      hw/misc: Add Microchip PolarFire SoC IOSCB module support
      hw/riscv: microchip_pfsoc: Connect the IOSCB module
      hw/misc: Add Microchip PolarFire SoC SYSREG module support
      hw/riscv: microchip_pfsoc: Connect the SYSREG module
      hw/riscv: microchip_pfsoc: Map the reserved memory at address 0
      hw/riscv: microchip_pfsoc: Correct DDR memory map
      hw/riscv: microchip_pfsoc: Hook the I2C1 controller

Xinhao Zhang (1):
      target/riscv/csr.c : add space before the open parenthesis '('

Yifei Jiang (6):
      target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit
      target/riscv: Add basic vmstate description of CPU
      target/riscv: Add PMP state description
      target/riscv: Add H extension state description
      target/riscv: Add V extension state description
      target/riscv: Add sifive_plic vmstate

 include/hw/intc/sifive_plic.h       |   1 +
 include/hw/misc/mchp_pfsoc_dmc.h    |  56 +++++++++
 include/hw/misc/mchp_pfsoc_ioscb.h  |  50 ++++++++
 include/hw/misc/mchp_pfsoc_sysreg.h |  39 ++++++
 include/hw/riscv/microchip_pfsoc.h  |  18 ++-
 target/riscv/cpu.h                  |  24 ++--
 target/riscv/cpu_bits.h             |  19 +--
 target/riscv/internals.h            |   4 +
 target/riscv/pmp.h                  |   2 +
 hw/intc/sifive_plic.c               |  26 +++-
 hw/misc/mchp_pfsoc_dmc.c            | 216 ++++++++++++++++++++++++++++++++
 hw/misc/mchp_pfsoc_ioscb.c          | 242 ++++++++++++++++++++++++++++++++++++
 hw/misc/mchp_pfsoc_sysreg.c         |  99 +++++++++++++++
 hw/riscv/microchip_pfsoc.c          | 125 ++++++++++++++++---
 hw/riscv/sifive_u.c                 |  28 +++--
 hw/riscv/virt.c                     |  27 ++--
 target/riscv/cpu.c                  |  16 +--
 target/riscv/cpu_helper.c           |  35 ++----
 target/riscv/csr.c                  |  20 +--
 target/riscv/machine.c              | 196 +++++++++++++++++++++++++++++
 target/riscv/op_helper.c            |  11 +-
 target/riscv/pmp.c                  |  29 +++--
 MAINTAINERS                         |   6 +
 hw/misc/Kconfig                     |   9 ++
 hw/misc/meson.build                 |   3 +
 hw/riscv/Kconfig                    |   3 +
 target/riscv/meson.build            |   3 +-
 27 files changed, 1180 insertions(+), 127 deletions(-)
 create mode 100644 include/hw/misc/mchp_pfsoc_dmc.h
 create mode 100644 include/hw/misc/mchp_pfsoc_ioscb.h
 create mode 100644 include/hw/misc/mchp_pfsoc_sysreg.h
 create mode 100644 hw/misc/mchp_pfsoc_dmc.c
 create mode 100644 hw/misc/mchp_pfsoc_ioscb.c
 create mode 100644 hw/misc/mchp_pfsoc_sysreg.c
 create mode 100644 target/riscv/machine.c