From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Yifei Jiang <jiangyifei@huawei.com>,
Yipeng Yin <yinyipeng1@huawei.com>
Subject: [PULL v2 04/19] target/riscv: Add basic vmstate description of CPU
Date: Tue, 3 Nov 2020 07:21:35 -0800 [thread overview]
Message-ID: <20201103152150.2677566-5-alistair.francis@wdc.com> (raw)
In-Reply-To: <20201103152150.2677566-1-alistair.francis@wdc.com>
From: Yifei Jiang <jiangyifei@huawei.com>
Add basic CPU state description to the newly created machine.c
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-3-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/internals.h | 4 +++
target/riscv/cpu.c | 8 +----
target/riscv/machine.c | 74 ++++++++++++++++++++++++++++++++++++++++
target/riscv/meson.build | 3 +-
4 files changed, 81 insertions(+), 8 deletions(-)
create mode 100644 target/riscv/machine.c
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index f1a546dba6..b15ad394bb 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -38,6 +38,10 @@ target_ulong fclass_d(uint64_t frs1);
#define SEW32 2
#define SEW64 3
+#ifndef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_riscv_cpu;
+#endif
+
static inline uint64_t nanbox_s(float32 f)
{
return f | MAKE_64BIT_MASK(32, 32);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dd05a220c7..6a0264fc6b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -22,6 +22,7 @@
#include "qemu/ctype.h"
#include "qemu/log.h"
#include "cpu.h"
+#include "internals.h"
#include "exec/exec-all.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
@@ -498,13 +499,6 @@ static void riscv_cpu_init(Object *obj)
cpu_set_cpustate_pointers(cpu);
}
-#ifndef CONFIG_USER_ONLY
-static const VMStateDescription vmstate_riscv_cpu = {
- .name = "cpu",
- .unmigratable = 1,
-};
-#endif
-
static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
new file mode 100644
index 0000000000..32edbcba7c
--- /dev/null
+++ b/target/riscv/machine.c
@@ -0,0 +1,74 @@
+/*
+ * RISC-V VMState Description
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/error-report.h"
+#include "sysemu/kvm.h"
+#include "migration/cpu.h"
+
+const VMStateDescription vmstate_riscv_cpu = {
+ .name = "cpu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
+ VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
+ VMSTATE_UINTTL(env.pc, RISCVCPU),
+ VMSTATE_UINTTL(env.load_res, RISCVCPU),
+ VMSTATE_UINTTL(env.load_val, RISCVCPU),
+ VMSTATE_UINTTL(env.frm, RISCVCPU),
+ VMSTATE_UINTTL(env.badaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
+ VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
+ VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
+ VMSTATE_UINTTL(env.misa, RISCVCPU),
+ VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
+ VMSTATE_UINT32(env.features, RISCVCPU),
+ VMSTATE_UINTTL(env.priv, RISCVCPU),
+ VMSTATE_UINTTL(env.virt, RISCVCPU),
+ VMSTATE_UINTTL(env.resetvec, RISCVCPU),
+ VMSTATE_UINTTL(env.mhartid, RISCVCPU),
+ VMSTATE_UINT64(env.mstatus, RISCVCPU),
+ VMSTATE_UINTTL(env.mip, RISCVCPU),
+ VMSTATE_UINT32(env.miclaim, RISCVCPU),
+ VMSTATE_UINTTL(env.mie, RISCVCPU),
+ VMSTATE_UINTTL(env.mideleg, RISCVCPU),
+ VMSTATE_UINTTL(env.sptbr, RISCVCPU),
+ VMSTATE_UINTTL(env.satp, RISCVCPU),
+ VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
+ VMSTATE_UINTTL(env.medeleg, RISCVCPU),
+ VMSTATE_UINTTL(env.stvec, RISCVCPU),
+ VMSTATE_UINTTL(env.sepc, RISCVCPU),
+ VMSTATE_UINTTL(env.scause, RISCVCPU),
+ VMSTATE_UINTTL(env.mtvec, RISCVCPU),
+ VMSTATE_UINTTL(env.mepc, RISCVCPU),
+ VMSTATE_UINTTL(env.mcause, RISCVCPU),
+ VMSTATE_UINTTL(env.mtval, RISCVCPU),
+ VMSTATE_UINTTL(env.scounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
+ VMSTATE_UINTTL(env.sscratch, RISCVCPU),
+ VMSTATE_UINTTL(env.mscratch, RISCVCPU),
+ VMSTATE_UINT64(env.mfromhost, RISCVCPU),
+ VMSTATE_UINT64(env.mtohost, RISCVCPU),
+ VMSTATE_UINT64(env.timecmp, RISCVCPU),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index abd647fea1..14a5c62dac 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -27,7 +27,8 @@ riscv_ss.add(files(
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
'pmp.c',
- 'monitor.c'
+ 'monitor.c',
+ 'machine.c'
))
target_arch += {'riscv': riscv_ss}
--
2.28.0
next prev parent reply other threads:[~2020-11-03 15:35 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-03 15:21 [PULL v2 00/19] riscv-to-apply queue Alistair Francis
2020-11-03 15:21 ` [PULL v2 01/19] hw/riscv: sifive_u: Allow passing custom DTB Alistair Francis
2020-11-03 15:21 ` [PULL v2 02/19] hw/riscv: virt: " Alistair Francis
2020-11-03 15:21 ` [PULL v2 03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Alistair Francis
2020-11-03 15:21 ` Alistair Francis [this message]
2020-11-03 15:21 ` [PULL v2 05/19] target/riscv: Add PMP state description Alistair Francis
2020-11-03 15:21 ` [PULL v2 06/19] target/riscv: Add H extension " Alistair Francis
2020-11-03 15:21 ` [PULL v2 07/19] target/riscv: Add V " Alistair Francis
2020-11-03 15:21 ` [PULL v2 08/19] target/riscv: Add sifive_plic vmstate Alistair Francis
2020-11-03 15:21 ` [PULL v2 09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps Alistair Francis
2020-11-03 15:21 ` [PULL v2 10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Alistair Francis
2020-11-03 15:21 ` [PULL v2 11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Alistair Francis
2020-11-03 15:21 ` [PULL v2 12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support Alistair Francis
2020-11-03 15:21 ` [PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module Alistair Francis
2020-11-03 15:21 ` [PULL v2 14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support Alistair Francis
2020-11-03 15:21 ` [PULL v2 15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module Alistair Francis
2020-11-03 15:21 ` [PULL v2 16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 Alistair Francis
2020-11-03 15:21 ` [PULL v2 17/19] hw/riscv: microchip_pfsoc: Correct DDR memory map Alistair Francis
2020-11-03 15:21 ` [PULL v2 18/19] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Alistair Francis
2020-11-03 15:21 ` [PULL v2 19/19] target/riscv/csr.c : add space before the open parenthesis '(' Alistair Francis
2020-11-03 21:07 ` [PULL v2 00/19] riscv-to-apply queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201103152150.2677566-5-alistair.francis@wdc.com \
--to=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=jiangyifei@huawei.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=yinyipeng1@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).