From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
Richard Henderson <richard.henderson@linaro.org>,
Yifei Jiang <jiangyifei@huawei.com>,
Yipeng Yin <yinyipeng1@huawei.com>
Subject: [PULL v2 07/19] target/riscv: Add V extension state description
Date: Tue, 3 Nov 2020 07:21:38 -0800 [thread overview]
Message-ID: <20201103152150.2677566-8-alistair.francis@wdc.com> (raw)
In-Reply-To: <20201103152150.2677566-1-alistair.francis@wdc.com>
From: Yifei Jiang <jiangyifei@huawei.com>
In the case of supporting V extension, add V extension description
to vmstate_riscv_cpu.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201026115530.304-6-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/machine.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index ae60050898..44d4015bd6 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -76,6 +76,30 @@ static bool hyper_needed(void *opaque)
return riscv_has_ext(env, RVH);
}
+static bool vector_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_has_ext(env, RVV);
+}
+
+static const VMStateDescription vmstate_vector = {
+ .name = "cpu/vector",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = vector_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(env.vreg, RISCVCPU, 32 * RV_VLEN_MAX / 64),
+ VMSTATE_UINTTL(env.vxrm, RISCVCPU),
+ VMSTATE_UINTTL(env.vxsat, RISCVCPU),
+ VMSTATE_UINTTL(env.vl, RISCVCPU),
+ VMSTATE_UINTTL(env.vstart, RISCVCPU),
+ VMSTATE_UINTTL(env.vtype, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_hyper = {
.name = "cpu/hyper",
.version_id = 1,
@@ -166,6 +190,7 @@ const VMStateDescription vmstate_riscv_cpu = {
.subsections = (const VMStateDescription * []) {
&vmstate_pmp,
&vmstate_hyper,
+ &vmstate_vector,
NULL
}
};
--
2.28.0
next prev parent reply other threads:[~2020-11-03 15:43 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-03 15:21 [PULL v2 00/19] riscv-to-apply queue Alistair Francis
2020-11-03 15:21 ` [PULL v2 01/19] hw/riscv: sifive_u: Allow passing custom DTB Alistair Francis
2020-11-03 15:21 ` [PULL v2 02/19] hw/riscv: virt: " Alistair Francis
2020-11-03 15:21 ` [PULL v2 03/19] target/riscv: Merge m/vsstatus and m/vsstatush into one uint64_t unit Alistair Francis
2020-11-03 15:21 ` [PULL v2 04/19] target/riscv: Add basic vmstate description of CPU Alistair Francis
2020-11-03 15:21 ` [PULL v2 05/19] target/riscv: Add PMP state description Alistair Francis
2020-11-03 15:21 ` [PULL v2 06/19] target/riscv: Add H extension " Alistair Francis
2020-11-03 15:21 ` Alistair Francis [this message]
2020-11-03 15:21 ` [PULL v2 08/19] target/riscv: Add sifive_plic vmstate Alistair Francis
2020-11-03 15:21 ` [PULL v2 09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps Alistair Francis
2020-11-03 15:21 ` [PULL v2 10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support Alistair Francis
2020-11-03 15:21 ` [PULL v2 11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules Alistair Francis
2020-11-03 15:21 ` [PULL v2 12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support Alistair Francis
2020-11-03 15:21 ` [PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module Alistair Francis
2020-11-03 15:21 ` [PULL v2 14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support Alistair Francis
2020-11-03 15:21 ` [PULL v2 15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module Alistair Francis
2020-11-03 15:21 ` [PULL v2 16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0 Alistair Francis
2020-11-03 15:21 ` [PULL v2 17/19] hw/riscv: microchip_pfsoc: Correct DDR memory map Alistair Francis
2020-11-03 15:21 ` [PULL v2 18/19] hw/riscv: microchip_pfsoc: Hook the I2C1 controller Alistair Francis
2020-11-03 15:21 ` [PULL v2 19/19] target/riscv/csr.c : add space before the open parenthesis '(' Alistair Francis
2020-11-03 21:07 ` [PULL v2 00/19] riscv-to-apply queue Peter Maydell
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