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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: j@getutm.app
Subject: [PATCH v3 12/41] tcg: Make tb arg to synchronize_from_tb const
Date: Thu,  5 Nov 2020 19:28:52 -0800	[thread overview]
Message-ID: <20201106032921.600200-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20201106032921.600200-1-richard.henderson@linaro.org>

There is nothing within the translators that ought to be
changing the TranslationBlock data, so make it const.

This does not actually use the read-only copy of the
data structure that exists within the rx region.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/hw/core/cpu.h   | 3 ++-
 target/arm/cpu.c        | 3 ++-
 target/avr/cpu.c        | 3 ++-
 target/hppa/cpu.c       | 3 ++-
 target/i386/cpu.c       | 3 ++-
 target/microblaze/cpu.c | 3 ++-
 target/mips/cpu.c       | 3 ++-
 target/riscv/cpu.c      | 3 ++-
 target/rx/cpu.c         | 3 ++-
 target/sh4/cpu.c        | 3 ++-
 target/sparc/cpu.c      | 3 ++-
 target/tricore/cpu.c    | 2 +-
 12 files changed, 23 insertions(+), 12 deletions(-)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 3d92c967ff..44c336a96a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -189,7 +189,8 @@ struct CPUClass {
     void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
                                Error **errp);
     void (*set_pc)(CPUState *cpu, vaddr value);
-    void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
+    void (*synchronize_from_tb)(CPUState *cpu,
+                                const struct TranslationBlock *tb);
     bool (*tlb_fill)(CPUState *cpu, vaddr address, int size,
                      MMUAccessType access_type, int mmu_idx,
                      bool probe, uintptr_t retaddr);
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 07492e9f9a..2f9be1c0ee 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -54,7 +54,8 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
     }
 }
 
-static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+static void arm_cpu_synchronize_from_tb(CPUState *cs,
+                                        const TranslationBlock *tb)
 {
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 5d9c4ad5bf..6f3d5a9e4a 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -41,7 +41,8 @@ static bool avr_cpu_has_work(CPUState *cs)
             && cpu_interrupts_enabled(env);
 }
 
-static void avr_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+static void avr_cpu_synchronize_from_tb(CPUState *cs,
+                                        const TranslationBlock *tb)
 {
     AVRCPU *cpu = AVR_CPU(cs);
     CPUAVRState *env = &cpu->env;
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 71b6aca45d..e28f047d10 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -35,7 +35,8 @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.iaoq_b = value + 4;
 }
 
-static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+static void hppa_cpu_synchronize_from_tb(CPUState *cs,
+                                         const TranslationBlock *tb)
 {
     HPPACPU *cpu = HPPA_CPU(cs);
 
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 0d8606958e..01a8acafe3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7012,7 +7012,8 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.eip = value;
 }
 
-static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+static void x86_cpu_synchronize_from_tb(CPUState *cs,
+                                        const TranslationBlock *tb)
 {
     X86CPU *cpu = X86_CPU(cs);
 
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 9b2482159d..c8e754cfb1 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -83,7 +83,8 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.iflags = 0;
 }
 
-static void mb_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+static void mb_cpu_synchronize_from_tb(CPUState *cs,
+                                       const TranslationBlock *tb)
 {
     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 76d50b00b4..79eee215cf 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -44,7 +44,8 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value)
     }
 }
 
-static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+static void mips_cpu_synchronize_from_tb(CPUState *cs,
+                                         const TranslationBlock *tb)
 {
     MIPSCPU *cpu = MIPS_CPU(cs);
     CPUMIPSState *env = &cpu->env;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6a0264fc6b..1b2f40de47 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -285,7 +285,8 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
     env->pc = value;
 }
 
-static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+static void riscv_cpu_synchronize_from_tb(CPUState *cs,
+                                          const TranslationBlock *tb)
 {
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 23ee17a701..2bb14144a7 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -33,7 +33,8 @@ static void rx_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.pc = value;
 }
 
-static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+static void rx_cpu_synchronize_from_tb(CPUState *cs,
+                                       const TranslationBlock *tb)
 {
     RXCPU *cpu = RX_CPU(cs);
 
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 3c68021c56..1e0f05a15b 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -34,7 +34,8 @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.pc = value;
 }
 
-static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+static void superh_cpu_synchronize_from_tb(CPUState *cs,
+                                           const TranslationBlock *tb)
 {
     SuperHCPU *cpu = SUPERH_CPU(cs);
 
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index cf21efd85f..b9241208b1 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -691,7 +691,8 @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.npc = value + 4;
 }
 
-static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
+static void sparc_cpu_synchronize_from_tb(CPUState *cs,
+                                          const TranslationBlock *tb)
 {
     SPARCCPU *cpu = SPARC_CPU(cs);
 
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index 2f2e5b029f..4bff1d4718 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -42,7 +42,7 @@ static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
 }
 
 static void tricore_cpu_synchronize_from_tb(CPUState *cs,
-                                            TranslationBlock *tb)
+                                            const TranslationBlock *tb)
 {
     TriCoreCPU *cpu = TRICORE_CPU(cs);
     CPUTriCoreState *env = &cpu->env;
-- 
2.25.1



  parent reply	other threads:[~2020-11-06  3:39 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-06  3:28 [PATCH v3 00/41] Mirror map JIT memory for TCG Richard Henderson
2020-11-06  3:28 ` [PATCH v3 01/41] tcg: Enhance flush_icache_range with separate data pointer Richard Henderson
2020-11-06 20:31   ` Alex Bennée
2020-11-06 22:51     ` Richard Henderson
2020-11-07 21:08       ` Alex Bennée
2020-11-06  3:28 ` [PATCH v3 02/41] tcg: Move tcg prologue pointer out of TCGContext Richard Henderson
2020-11-07 21:10   ` Alex Bennée
2020-11-06  3:28 ` [PATCH v3 03/41] tcg: Move tcg epilogue " Richard Henderson
2020-11-06  3:28 ` [PATCH v3 04/41] tcg: Add in_code_gen_buffer Richard Henderson
2020-11-06  3:28 ` [PATCH v3 05/41] tcg: Introduce tcg_splitwx_to_{rx,rw} Richard Henderson
2020-11-06  3:28 ` [PATCH v3 06/41] tcg: Adjust TCGLabel for const Richard Henderson
2020-11-06  3:28 ` [PATCH v3 07/41] tcg: Adjust tcg_out_call " Richard Henderson
2020-11-06  3:28 ` [PATCH v3 08/41] tcg: Adjust tcg_out_label " Richard Henderson
2020-11-06  3:28 ` [PATCH v3 09/41] tcg: Adjust tcg_register_jit " Richard Henderson
2020-11-06  3:28 ` [PATCH v3 10/41] tcg: Adjust tb_target_set_jmp_target for split-wx Richard Henderson
2020-11-06  3:28 ` [PATCH v3 11/41] tcg: Make DisasContextBase.tb const Richard Henderson
2020-11-06  3:28 ` Richard Henderson [this message]
2020-11-06  3:28 ` [PATCH v3 13/41] tcg: Use Error with alloc_code_gen_buffer Richard Henderson
2020-11-06  3:28 ` [PATCH v3 14/41] tcg: Add --accel tcg,split-wx property Richard Henderson
2020-11-06  3:28 ` [PATCH v3 15/41] accel/tcg: Support split-wx for linux with memfd Richard Henderson
2020-11-10 17:03   ` Alex Bennée
2020-11-10 17:26     ` Richard Henderson
2020-11-06  3:28 ` [PATCH v3 16/41] accel/tcg: Support split-wx for darwin/iOS with vm_remap Richard Henderson
2020-11-08  3:37   ` Joelle van Dyne
2020-11-10 17:37   ` Alex Bennée
2020-11-10 17:57     ` Joelle van Dyne
2020-11-06  3:28 ` [PATCH v3 17/41] tcg: Return the TB pointer from the rx region from exit_tb Richard Henderson
2020-11-06  3:28 ` [PATCH v3 18/41] tcg/i386: Support split-wx code generation Richard Henderson
2020-11-06  3:28 ` [PATCH v3 19/41] tcg/aarch64: Use B not BL for tcg_out_goto_long Richard Henderson
2020-11-06  3:29 ` [PATCH v3 20/41] tcg/aarch64: Implement flush_idcache_range manually Richard Henderson
2020-11-06  3:29 ` [PATCH v3 21/41] tcg/aarch64: Support split-wx code generation Richard Henderson
2020-11-06  3:29 ` [PATCH v3 22/41] disas: Push const down through host disasassembly Richard Henderson
2020-11-06  3:29 ` [PATCH v3 23/41] tcg/tci: Push const down through bytecode reading Richard Henderson
2020-11-06  3:29 ` [PATCH v3 24/41] tcg: Introduce tcg_tbrel_diff Richard Henderson
2020-11-06  3:29 ` [PATCH v3 25/41] tcg/ppc: Use tcg_tbrel_diff Richard Henderson
2020-11-06  3:29 ` [PATCH v3 26/41] tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TB Richard Henderson
2020-11-06  3:29 ` [PATCH v3 27/41] tcg/ppc: Support split-wx code generation Richard Henderson
2020-11-06  3:29 ` [PATCH v3 28/41] tcg/sparc: Use tcg_tbrel_diff Richard Henderson
2020-11-06  3:29 ` [PATCH v3 29/41] tcg/sparc: Support split-wx code generation Richard Henderson
2020-11-06  3:29 ` [PATCH v3 30/41] tcg/s390: Use tcg_tbrel_diff Richard Henderson
2020-11-06  3:29 ` [PATCH v3 31/41] tcg/s390: Support split-wx code generation Richard Henderson
2020-11-06  3:29 ` [PATCH v3 32/41] tcg/riscv: Fix branch range checks Richard Henderson
2020-11-06  3:29 ` [PATCH v3 33/41] tcg/riscv: Remove branch-over-branch fallback Richard Henderson
2020-11-06  3:29 ` [PATCH v3 34/41] tcg/riscv: Support split-wx code generation Richard Henderson
2020-11-06  3:29 ` [PATCH v3 35/41] accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd Richard Henderson
2020-11-06  3:29 ` [PATCH v3 36/41] tcg/mips: Do not assert on relocation overflow Richard Henderson
2020-11-06  3:29 ` [PATCH v3 37/41] tcg/mips: Support split-wx code generation Richard Henderson
2020-11-06  3:29 ` [PATCH v3 38/41] tcg/arm: " Richard Henderson
2020-11-06  3:29 ` [PATCH v3 39/41] tcg: Remove TCG_TARGET_SUPPORT_MIRROR Richard Henderson
2020-11-06  3:29 ` [PATCH v3 40/41] tcg: Constify tcg_code_gen_epilogue Richard Henderson
2020-11-06  3:29 ` [PATCH v3 41/41] tcg: Constify TCGLabelQemuLdst.raddr Richard Henderson
2020-11-06  4:00 ` [PATCH v3 00/41] Mirror map JIT memory for TCG no-reply
2020-11-08  3:38 ` Joelle van Dyne
2020-11-17  3:47 ` Joelle van Dyne
2020-11-17 15:20   ` Richard Henderson
2020-11-17 15:31     ` Joelle van Dyne
2020-11-17 17:26       ` Alex Bennée

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