[PATCH 1/2] ppc/translate: Implement lxvwsx opcode

[PATCH 1/2] ppc/translate: Implement lxvwsx opcode

[LemonBoy]

Implement the "Load VSX Vector Word & Splat Indexed" opcode, introduced
in Power ISA v3.0.

Buglink: https://bugs.launchpad.net/qemu/+bug/1793608
Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
---
 target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++++++
 target/ppc/translate/vsx-ops.c.inc  |  1 +
 2 files changed, 31 insertions(+)

diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index b518de46db..075f063e98 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -139,6 +139,36 @@ static void gen_lxvw4x(DisasContext *ctx)
     tcg_temp_free_i64(xtl);
 }
 
+static void gen_lxvwsx(DisasContext *ctx)
+{
+    TCGv EA;
+    TCGv_i32 data;
+
+    if (xT(ctx->opcode) < 32) {
+        if (unlikely(!ctx->vsx_enabled)) {
+            gen_exception(ctx, POWERPC_EXCP_VSXU);
+            return;
+        }
+    } else {
+        if (unlikely(!ctx->altivec_enabled)) {
+            gen_exception(ctx, POWERPC_EXCP_VPU);
+            return;
+        }
+    }
+
+    gen_set_access_type(ctx, ACCESS_INT);
+    EA = tcg_temp_new();
+
+    gen_addr_reg_index(ctx, EA);
+
+    data = tcg_temp_new_i32();
+    tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_TEUL);
+    tcg_gen_gvec_dup_i32(MO_UL, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
+
+    tcg_temp_free(EA);
+    tcg_temp_free_i32(data);
+}
+
 static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
                           TCGv_i64 inh, TCGv_i64 inl)
 {
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 7fd3942b84..1d41beef26 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -5,6 +5,7 @@ GEN_HANDLER_E(lxsibzx, 0x1F, 0x0D, 0x18, 0, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER_E(lxsihzx, 0x1F, 0x0D, 0x19, 0, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvwsx, 0x1F, 0x0C, 0x0B, 0, PPC_NONE, PPC2_ISA300),
 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
 GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE,  PPC2_ISA300),
-- 
2.27.0

[PATCH 2/2] ppc/translate: Rewrite gen_lxvdsx to use gvec primitives

[LemonBoy]

Make the implementation match the lxvwsx one.
The code is now shorter smaller and potentially faster as the
translation will use the host SIMD capabilities if available.

No functional change.

Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
---
 target/ppc/translate/vsx-impl.c.inc | 46 ++++++++++++++---------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 075f063e98..b817d31260 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -75,29 +75,6 @@ static void gen_lxvd2x(DisasContext *ctx)
     tcg_temp_free_i64(t0);
 }
 
-static void gen_lxvdsx(DisasContext *ctx)
-{
-    TCGv EA;
-    TCGv_i64 t0;
-    TCGv_i64 t1;
-    if (unlikely(!ctx->vsx_enabled)) {
-        gen_exception(ctx, POWERPC_EXCP_VSXU);
-        return;
-    }
-    t0 = tcg_temp_new_i64();
-    t1 = tcg_temp_new_i64();
-    gen_set_access_type(ctx, ACCESS_INT);
-    EA = tcg_temp_new();
-    gen_addr_reg_index(ctx, EA);
-    gen_qemu_ld64_i64(ctx, t0, EA);
-    set_cpu_vsrh(xT(ctx->opcode), t0);
-    tcg_gen_mov_i64(t1, t0);
-    set_cpu_vsrl(xT(ctx->opcode), t1);
-    tcg_temp_free(EA);
-    tcg_temp_free_i64(t0);
-    tcg_temp_free_i64(t1);
-}
-
 static void gen_lxvw4x(DisasContext *ctx)
 {
     TCGv EA;
@@ -169,6 +146,29 @@ static void gen_lxvwsx(DisasContext *ctx)
     tcg_temp_free_i32(data);
 }
 
+static void gen_lxvdsx(DisasContext *ctx)
+{
+    TCGv EA;
+    TCGv_i64 data;
+
+    if (unlikely(!ctx->vsx_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VSXU);
+        return;
+    }
+
+    gen_set_access_type(ctx, ACCESS_INT);
+    EA = tcg_temp_new();
+
+    gen_addr_reg_index(ctx, EA);
+
+    data = tcg_temp_new_i64();
+    tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_TEQ);
+    tcg_gen_gvec_dup_i64(MO_Q, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
+
+    tcg_temp_free(EA);
+    tcg_temp_free_i64(data);
+}
+
 static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
                           TCGv_i64 inh, TCGv_i64 inl)
 {
-- 
2.27.0

Re: [PATCH 2/2] ppc/translate: Rewrite gen_lxvdsx to use gvec primitives

[Richard Henderson]

On 11/9/20 1:17 AM, LemonBoy wrote:
> Make the implementation match the lxvwsx one.
> The code is now shorter smaller and potentially faster as the
> translation will use the host SIMD capabilities if available.
> 
> No functional change.
> 
> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
> ---
>  target/ppc/translate/vsx-impl.c.inc | 46 ++++++++++++++---------------
>  1 file changed, 23 insertions(+), 23 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 1/2] ppc/translate: Implement lxvwsx opcode

[Richard Henderson]

On 11/9/20 1:17 AM, LemonBoy wrote:
> Implement the "Load VSX Vector Word & Splat Indexed" opcode, introduced
> in Power ISA v3.0.
> 
> Buglink: https://bugs.launchpad.net/qemu/+bug/1793608
> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
> ---
>  target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++++++
>  target/ppc/translate/vsx-ops.c.inc  |  1 +
>  2 files changed, 31 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

Re: [PATCH 1/2] ppc/translate: Implement lxvwsx opcode

[LemonBoy]

Is there any chance for this patch series to be merged for 5.2?

On 09/11/20 18:39, Richard Henderson wrote:
> On 11/9/20 1:17 AM, LemonBoy wrote:
>> Implement the "Load VSX Vector Word & Splat Indexed" opcode, introduced
>> in Power ISA v3.0.
>>
>> Buglink: https://bugs.launchpad.net/qemu/+bug/1793608
>> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
>> ---
>>  target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++++++
>>  target/ppc/translate/vsx-ops.c.inc  |  1 +
>>  2 files changed, 31 insertions(+)
> 
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> 
> r~
> 

Re: [PATCH 1/2] ppc/translate: Implement lxvwsx opcode

[David Gibson]

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On Tue, Nov 10, 2020 at 10:14:23AM +0100, LemonBoy wrote:
> Is there any chance for this patch series to be merged for 5.2?

No.  We are now in hard freeze, and this is not a bugfix.

> 
> On 09/11/20 18:39, Richard Henderson wrote:
> > On 11/9/20 1:17 AM, LemonBoy wrote:
> >> Implement the "Load VSX Vector Word & Splat Indexed" opcode, introduced
> >> in Power ISA v3.0.
> >>
> >> Buglink: https://bugs.launchpad.net/qemu/+bug/1793608
> >> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
> >> ---
> >>  target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++++++
> >>  target/ppc/translate/vsx-ops.c.inc  |  1 +
> >>  2 files changed, 31 insertions(+)
> > 
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > 
> > r~
> > 
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [PATCH 1/2] ppc/translate: Implement lxvwsx opcode

[Richard Henderson]

On 11/10/20 10:22 PM, David Gibson wrote:
> On Tue, Nov 10, 2020 at 10:14:23AM +0100, LemonBoy wrote:
>> Is there any chance for this patch series to be merged for 5.2?
> 
> No.  We are now in hard freeze, and this is not a bugfix.

Actually, patch 1/2 is a bugfix -- a missing instruction from an ISA that we
claim to implement.


r~

> 
>>
>> On 09/11/20 18:39, Richard Henderson wrote:
>>> On 11/9/20 1:17 AM, LemonBoy wrote:
>>>> Implement the "Load VSX Vector Word & Splat Indexed" opcode, introduced
>>>> in Power ISA v3.0.
>>>>
>>>> Buglink: https://bugs.launchpad.net/qemu/+bug/1793608
>>>> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
>>>> ---
>>>>  target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++++++
>>>>  target/ppc/translate/vsx-ops.c.inc  |  1 +
>>>>  2 files changed, 31 insertions(+)
>>>
>>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>>>
>>> r~
>>>
>>
> 

Re: [PATCH 1/2] ppc/translate: Implement lxvwsx opcode

[David Gibson]

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On Sat, Nov 14, 2020 at 09:13:33AM -0800, Richard Henderson wrote:
> On 11/10/20 10:22 PM, David Gibson wrote:
> > On Tue, Nov 10, 2020 at 10:14:23AM +0100, LemonBoy wrote:
> >> Is there any chance for this patch series to be merged for 5.2?
> > 
> > No.  We are now in hard freeze, and this is not a bugfix.
> 
> Actually, patch 1/2 is a bugfix -- a missing instruction from an ISA that we
> claim to implement.

Fair point.  I'm applying 1/2 to ppc-for-5.2 and 2/2 to ppc-for-6.0.

> 
> 
> r~
> 
> > 
> >>
> >> On 09/11/20 18:39, Richard Henderson wrote:
> >>> On 11/9/20 1:17 AM, LemonBoy wrote:
> >>>> Implement the "Load VSX Vector Word & Splat Indexed" opcode, introduced
> >>>> in Power ISA v3.0.
> >>>>
> >>>> Buglink: https://bugs.launchpad.net/qemu/+bug/1793608
> >>>> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
> >>>> ---
> >>>>  target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++++++
> >>>>  target/ppc/translate/vsx-ops.c.inc  |  1 +
> >>>>  2 files changed, 31 insertions(+)
> >>>
> >>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> >>>
> >>> r~
> >>>
> >>
> > 
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [PATCH 1/2] ppc/translate: Implement lxvwsx opcode

[Greg Kurz]

On Tue, 10 Nov 2020 10:14:23 +0100
LemonBoy <thatlemon@gmail.com> wrote:

> Is there any chance for this patch series to be merged for 5.2?
> 

Not a chance. We're in hard freeze now.

> On 09/11/20 18:39, Richard Henderson wrote:
> > On 11/9/20 1:17 AM, LemonBoy wrote:
> >> Implement the "Load VSX Vector Word & Splat Indexed" opcode, introduced
> >> in Power ISA v3.0.
> >>
> >> Buglink: https://bugs.launchpad.net/qemu/+bug/1793608
> >> Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
> >> ---
> >>  target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++++++
> >>  target/ppc/translate/vsx-ops.c.inc  |  1 +
> >>  2 files changed, 31 insertions(+)
> > 
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > 
> > r~
> > 
>