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Mon, 23 Nov 2020 01:59:29 -0500 (EST) From: Klaus Jensen To: qemu-devel@nongnu.org Subject: [PATCH 0/3] hw/block/nvme: allow cmb and pmr to coexist Date: Mon, 23 Nov 2020 07:59:24 +0100 Message-Id: <20201123065927.108923-1-its@irrelevant.dk> X-Mailer: git-send-email 2.29.2 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=66.111.4.28; envelope-from=its@irrelevant.dk; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Klaus Jensen , Andrzej Jakowski , Keith Busch Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen =0D This is a resurrection of Andrzej's series[1] from back July.=0D =0D Andrzej's main patch basically moved the the CMB from BAR 2 into an=0D offset in BAR 4 (located after the MSI-X table and PBA). Having an=0D offset on the CMB causes a bunch of calculations related to address=0D mapping to change.=0D =0D So, since I couldn't get the patch to apply cleanly I took a stab at=0D implementing the suggestion I originally came up with: simply move the=0D MSI-X table and PBA from BAR 4 into BAR 0 (up-aligned to a 4 KiB=0D boundary, after the main NVMe controller registers). This way we can=0D keep the CMB at offset zero in its own BAR and free up BAR 4 for use by=0D PMR. This makes the patch simpler and does not impact any of the=0D existing address mapping code.=0D =0D Andrzej, I would prefer an Ack from you, since I pretty much voided your=0D main patch.=0D =0D [1]: https://lore.kernel.org/qemu-devel/20200729220107.37758-1-andrzej.ja= kowski@linux.intel.com/=0D =0D CC: Andrzej Jakowski =0D =0D Andrzej Jakowski (1):=0D hw/block/nvme: indicate CMB support through controller capabilities=0D register=0D =0D Klaus Jensen (2):=0D hw/block/nvme: move msix table and pba to BAR 0=0D hw/block/nvme: allow cmb and pmr to coexist=0D =0D hw/block/nvme.h | 1 +=0D include/block/nvme.h | 10 +++++++---=0D hw/block/nvme.c | 42 +++++++++++++++++++++++++++++++-----------=0D 3 files changed, 39 insertions(+), 14 deletions(-)=0D =0D -- =0D 2.29.2=0D =0D