* [PULL 0/1] ppc-for-5.2 queue 20201124
@ 2020-11-24 5:51 David Gibson
2020-11-24 5:51 ` [PULL 1/1] ppc/translate: Implement lxvwsx opcode David Gibson
2020-11-24 15:22 ` [PULL 0/1] ppc-for-5.2 queue 20201124 Peter Maydell
0 siblings, 2 replies; 3+ messages in thread
From: David Gibson @ 2020-11-24 5:51 UTC (permalink / raw)
To: peter.maydell; +Cc: David Gibson, qemu-ppc, groug, qemu-devel
The following changes since commit 23895cbd82be95428e90168b12e925d0d3ca2f06:
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20201123.0' into staging (2020-11-23 18:51:13 +0000)
are available in the Git repository at:
https://gitlab.com/dgibson/qemu.git tags/ppc-for-5.2-20201124
for you to fetch changes up to afae37d98ae991c0792c867dbd9f32f988044318:
ppc/translate: Implement lxvwsx opcode (2020-11-24 11:34:18 +1100)
----------------------------------------------------------------
ppc patch queue for 2020-11-24
One final update for qemu-5.2, implementing an instruction that we
already should have, given the ISA version we claim to support. Sorry
for the lateness, I've been on holiday.
This isn't a regression, obviously, so if it misses qemu-5.2 it's not
a disaster, but it would be nice to have. The risk is low that it
would break any existing instructions.
----------------------------------------------------------------
LemonBoy (1):
ppc/translate: Implement lxvwsx opcode
target/ppc/translate/vsx-impl.c.inc | 30 ++++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.c.inc | 1 +
2 files changed, 31 insertions(+)
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PULL 1/1] ppc/translate: Implement lxvwsx opcode
2020-11-24 5:51 [PULL 0/1] ppc-for-5.2 queue 20201124 David Gibson
@ 2020-11-24 5:51 ` David Gibson
2020-11-24 15:22 ` [PULL 0/1] ppc-for-5.2 queue 20201124 Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: David Gibson @ 2020-11-24 5:51 UTC (permalink / raw)
To: peter.maydell
Cc: LemonBoy, Richard Henderson, groug, qemu-devel, qemu-ppc,
David Gibson
From: LemonBoy <thatlemon@gmail.com>
Implement the "Load VSX Vector Word & Splat Indexed" opcode, introduced
in Power ISA v3.0.
Buglink: https://bugs.launchpad.net/qemu/+bug/1793608
Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com>
Message-Id: <d7d533e18c2bc10d924ee3e09907ff2b41fddb3a.1604912739.git.thatlemon@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.c.inc | 30 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.c.inc | 1 +
2 files changed, 31 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index b518de46db..075f063e98 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -139,6 +139,36 @@ static void gen_lxvw4x(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
+static void gen_lxvwsx(DisasContext *ctx)
+{
+ TCGv EA;
+ TCGv_i32 data;
+
+ if (xT(ctx->opcode) < 32) {
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ } else {
+ if (unlikely(!ctx->altivec_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VPU);
+ return;
+ }
+ }
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ EA = tcg_temp_new();
+
+ gen_addr_reg_index(ctx, EA);
+
+ data = tcg_temp_new_i32();
+ tcg_gen_qemu_ld_i32(data, EA, ctx->mem_idx, MO_TEUL);
+ tcg_gen_gvec_dup_i32(MO_UL, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
+
+ tcg_temp_free(EA);
+ tcg_temp_free_i32(data);
+}
+
static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
TCGv_i64 inh, TCGv_i64 inl)
{
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 7fd3942b84..1d41beef26 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -5,6 +5,7 @@ GEN_HANDLER_E(lxsibzx, 0x1F, 0x0D, 0x18, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxsihzx, 0x1F, 0x0D, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
+GEN_HANDLER_E(lxvwsx, 0x1F, 0x0C, 0x0B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
--
2.28.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PULL 0/1] ppc-for-5.2 queue 20201124
2020-11-24 5:51 [PULL 0/1] ppc-for-5.2 queue 20201124 David Gibson
2020-11-24 5:51 ` [PULL 1/1] ppc/translate: Implement lxvwsx opcode David Gibson
@ 2020-11-24 15:22 ` Peter Maydell
1 sibling, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2020-11-24 15:22 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, Greg Kurz, QEMU Developers
On Tue, 24 Nov 2020 at 05:51, David Gibson <david@gibson.dropbear.id.au> wrote:
>
> The following changes since commit 23895cbd82be95428e90168b12e925d0d3ca2f06:
>
> Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20201123.0' into staging (2020-11-23 18:51:13 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/dgibson/qemu.git tags/ppc-for-5.2-20201124
>
> for you to fetch changes up to afae37d98ae991c0792c867dbd9f32f988044318:
>
> ppc/translate: Implement lxvwsx opcode (2020-11-24 11:34:18 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue for 2020-11-24
>
> One final update for qemu-5.2, implementing an instruction that we
> already should have, given the ISA version we claim to support. Sorry
> for the lateness, I've been on holiday.
>
> This isn't a regression, obviously, so if it misses qemu-5.2 it's not
> a disaster, but it would be nice to have. The risk is low that it
> would break any existing instructions.
>
> ----------------------------------------------------------------
> LemonBoy (1):
> ppc/translate: Implement lxvwsx opcode
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 3+ messages in thread
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