From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH 09/11] target/arm: Enforce alignment for VLDn/VSTn (multiple)
Date: Tue, 24 Nov 2020 20:06:40 -0800 [thread overview]
Message-ID: <20201125040642.2339476-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20201125040642.2339476-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-neon.c.inc | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index 32e47331a5..c4be019d9c 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -427,9 +427,12 @@ static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn,
static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
{
+ static const MemOp mop_align[4] = {
+ 0, MO_ALIGN_8, MO_ALIGN_16, MO_ALIGN_32
+ };
/* Neon load/store multiple structures */
int nregs, interleave, spacing, reg, n;
- MemOp endian = s->be_data;
+ MemOp mop, endian = s->be_data;
int mmu_idx = get_mem_index(s);
int size = a->size;
TCGv_i64 tmp64;
@@ -487,6 +490,10 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
addr = tcg_temp_new_i32();
tmp = tcg_const_i32(1 << size);
load_reg_var(s, addr, a->rn);
+
+ /* Enforce the requested alignment for the first memory operation. */
+ mop = endian | size | mop_align[a->align];
+
for (reg = 0; reg < nregs; reg++) {
for (n = 0; n < 8 >> size; n++) {
int xs;
@@ -494,13 +501,16 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
int tt = a->vd + reg + spacing * xs;
if (a->l) {
- gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
+ gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, mop);
neon_store_element64(tt, n, size, tmp64);
} else {
neon_load_element64(tmp64, tt, n, size);
- gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
+ gen_aa32_st_i64(s, tmp64, addr, mmu_idx, mop);
}
tcg_gen_add_i32(addr, addr, tmp);
+
+ /* Subsequent memory operations inherit alignment */
+ mop &= ~MO_AMASK;
}
}
}
--
2.25.1
next prev parent reply other threads:[~2020-11-25 4:13 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-25 4:06 [PATCH for-6.0 00/11] target/arm: enforce alignment Richard Henderson
2020-11-25 4:06 ` [PATCH 01/11] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2020-11-25 8:11 ` Philippe Mathieu-Daudé
2020-11-25 4:06 ` [PATCH 02/11] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2020-11-25 8:13 ` Philippe Mathieu-Daudé
2020-11-25 4:06 ` [PATCH 03/11] target/arm: Enforce alignment for LDM/STM Richard Henderson
2020-11-25 4:06 ` [PATCH 04/11] target/arm: Enforce alignment for RFE Richard Henderson
2020-11-25 4:06 ` [PATCH 05/11] target/arm: Enforce alignment for SRS Richard Henderson
2020-12-03 11:38 ` Peter Maydell
2020-11-25 4:06 ` [PATCH 06/11] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2020-11-25 4:06 ` [PATCH 07/11] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2020-11-25 4:06 ` [PATCH 08/11] target/arm: Enforce alignment for VLD1 (all lanes) Richard Henderson
2020-11-25 4:06 ` Richard Henderson [this message]
2020-11-25 4:06 ` [PATCH 10/11] target/arm: Fix decode of align in VLDST_single Richard Henderson
2020-12-01 14:09 ` Peter Maydell
2020-11-25 4:06 ` [PATCH 11/11] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2020-12-01 14:27 ` [PATCH for-6.0 00/11] target/arm: enforce alignment Peter Maydell
2020-12-01 14:37 ` Richard Henderson
2020-12-01 15:55 ` Peter Maydell
2020-12-03 12:30 ` Philippe Mathieu-Daudé
2020-12-03 16:10 ` Pavel Dovgalyuk
2020-12-03 16:14 ` Peter Maydell
2020-12-04 6:17 ` Pavel Dovgalyuk
2020-12-04 16:36 ` Peter Maydell
2020-12-04 17:28 ` Richard Henderson
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