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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 34sm15809722wrh.78.2020.11.27.11.12.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Nov 2020 11:12:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PATCH 0/2] target/nios2: Roll cpu_pic code into CPU itself Date: Fri, 27 Nov 2020 19:12:31 +0000 Message-Id: <20201127191233.11200-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marek Vasut , Sandra Loosemore , Chris Wulff , Wentong Wu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" (As well as the listed nios2 maintainers, I've cc'd a couple of the more recent contributors to this target in case they're interested or wish to test the changes.) The nios2 code uses an old style of interrupt handling, where a separate standalone set of qemu_irqs invoke a function nios2_pic_cpu_handler() which signals the interrupt to the CPU proper by directly calling cpu_interrupt() and cpu_reset_interrupt(). Because CPU objects now inherit (indirectly) from TYPE_DEVICE, they can have GPIO input lines themselves, and the neater modern way to implement this is to simply have the CPU object itself provide the input IRQ lines. This allows us to roll all of the code in hw/nios/cpu_pic.c into target/nios2 one way or another. The motivation here is fixing a trivial Coverity-reported leak (CID 1421916) of the IRQ array allocated in nios2_cpu_pic_init(), and also part of the extremely slow refactoring of code away from using qemu_allocate_irqs() at all. Tested with 'make check' and 'make check-acceptance' (which does include a boot test of a nios2 10m50 guest). thanks -- PMM Peter Maydell (2): target/nios2: Move cpu_pic code into CPU object proper target/nios2: Move nios2_check_interrupts() into target/nios2 target/nios2/cpu.h | 3 -- hw/nios2/10m50_devboard.c | 8 ++--- hw/nios2/cpu_pic.c | 67 --------------------------------------- target/nios2/cpu.c | 34 ++++++++++++++++++++ target/nios2/op_helper.c | 9 ++++++ hw/nios2/meson.build | 2 +- 6 files changed, 47 insertions(+), 76 deletions(-) delete mode 100644 hw/nios2/cpu_pic.c -- 2.20.1