* [PATCH v4 1/2] hw/virtio-pci Added counter for pcie capabilities offsets.
2020-12-03 11:07 [PATCH v4 0/2] hw/virtio-pci: " andrew
@ 2020-12-03 11:07 ` andrew
0 siblings, 0 replies; 5+ messages in thread
From: andrew @ 2020-12-03 11:07 UTC (permalink / raw)
To: qemu-devel; +Cc: berrange, mst
From: Andrew <andrew@daynix.com>
Removed hardcoded offset for ats. Added cap offset counter
for future capabilities like AER.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
---
hw/virtio/virtio-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 36524a5728..ceaa233129 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1798,6 +1798,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
if (pcie_port && pci_is_express(pci_dev)) {
int pos;
+ uint16_t last_pcie_cap_offset = PCI_CONFIG_SPACE_SIZE;
pos = pcie_endpoint_cap_init(pci_dev, 0);
assert(pos > 0);
@@ -1833,7 +1834,8 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
}
if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
- pcie_ats_init(pci_dev, 256);
+ pcie_ats_init(pci_dev, last_pcie_cap_offset);
+ last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF;
}
if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
--
2.29.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4 0/2] hw/virtio-pci: AER capability
@ 2020-12-03 13:25 Andrew Melnychenko
2020-12-03 13:25 ` [PATCH v4 1/2] hw/virtio-pci Added counter for pcie capabilities offsets Andrew Melnychenko
2020-12-03 13:25 ` [PATCH v4 2/2] hw/virtio-pci Added AER capability Andrew Melnychenko
0 siblings, 2 replies; 5+ messages in thread
From: Andrew Melnychenko @ 2020-12-03 13:25 UTC (permalink / raw)
To: mst; +Cc: intel-wired-lan, qemu-devel, alexander.duyck
Main motivation:
According to Microsoft driver\device certification requirements
for next version of Window Server, PCIe device must support AER.
"Windows Server PCI Express devices are required to support
Advanced Error Reporting [AER] as defined in
PCI Express Base Specification version 2.1."
AER capability for virtio-pci is disabled by default.
AER capability is only for PCI with PCIe interface on PCIe bus.
During migration - device "realize" should initialize AER
if requested by device properties.
Fixed commit message.
Andrew (2):
hw/virtio-pci Added counter for pcie capabilities offsets.
hw/virtio-pci Added AER capability.
hw/virtio/virtio-pci.c | 20 +++++++++++++++++++-
hw/virtio/virtio-pci.h | 4 ++++
2 files changed, 23 insertions(+), 1 deletion(-)
--
2.29.2
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v4 1/2] hw/virtio-pci Added counter for pcie capabilities offsets.
2020-12-03 13:25 [PATCH v4 0/2] hw/virtio-pci: AER capability Andrew Melnychenko
@ 2020-12-03 13:25 ` Andrew Melnychenko
2020-12-03 13:25 ` [PATCH v4 2/2] hw/virtio-pci Added AER capability Andrew Melnychenko
1 sibling, 0 replies; 5+ messages in thread
From: Andrew Melnychenko @ 2020-12-03 13:25 UTC (permalink / raw)
To: mst; +Cc: intel-wired-lan, qemu-devel, alexander.duyck
From: Andrew <andrew@daynix.com>
Removed hardcoded offset for ats. Added cap offset counter
for future capabilities like AER.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
---
hw/virtio/virtio-pci.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 36524a5728..ceaa233129 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1798,6 +1798,7 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
if (pcie_port && pci_is_express(pci_dev)) {
int pos;
+ uint16_t last_pcie_cap_offset = PCI_CONFIG_SPACE_SIZE;
pos = pcie_endpoint_cap_init(pci_dev, 0);
assert(pos > 0);
@@ -1833,7 +1834,8 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
}
if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {
- pcie_ats_init(pci_dev, 256);
+ pcie_ats_init(pci_dev, last_pcie_cap_offset);
+ last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF;
}
if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {
--
2.29.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4 2/2] hw/virtio-pci Added AER capability.
2020-12-03 13:25 [PATCH v4 0/2] hw/virtio-pci: AER capability Andrew Melnychenko
2020-12-03 13:25 ` [PATCH v4 1/2] hw/virtio-pci Added counter for pcie capabilities offsets Andrew Melnychenko
@ 2020-12-03 13:25 ` Andrew Melnychenko
2020-12-03 21:57 ` Michael S. Tsirkin
1 sibling, 1 reply; 5+ messages in thread
From: Andrew Melnychenko @ 2020-12-03 13:25 UTC (permalink / raw)
To: mst; +Cc: intel-wired-lan, qemu-devel, alexander.duyck
From: Andrew <andrew@daynix.com>
Added AER capability for virtio-pci devices.
Also added property for devices, by default AER is disabled.
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
---
hw/virtio/virtio-pci.c | 16 ++++++++++++++++
hw/virtio/virtio-pci.h | 4 ++++
2 files changed, 20 insertions(+)
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index ceaa233129..f863f69ede 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -1817,6 +1817,12 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
*/
pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
+ if (proxy->flags & VIRTIO_PCI_FLAG_AER) {
+ pcie_aer_init(pci_dev, PCI_ERR_VER, last_pcie_cap_offset,
+ PCI_ERR_SIZEOF, NULL);
+ last_pcie_cap_offset += PCI_ERR_SIZEOF;
+ }
+
if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
/* Init error enabling flags */
pcie_cap_deverr_init(pci_dev);
@@ -1858,7 +1864,15 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
static void virtio_pci_exit(PCIDevice *pci_dev)
{
+ VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
+ bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
+ !pci_bus_is_root(pci_get_bus(pci_dev));
+
msix_uninit_exclusive_bar(pci_dev);
+ if (proxy->flags & VIRTIO_PCI_FLAG_AER && pcie_port &&
+ pci_is_express(pci_dev)) {
+ pcie_aer_exit(pci_dev);
+ }
}
static void virtio_pci_reset(DeviceState *qdev)
@@ -1911,6 +1925,8 @@ static Property virtio_pci_properties[] = {
VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
+ DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
+ VIRTIO_PCI_FLAG_AER_BIT, false),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
index 06e2af12de..d7d5d403a9 100644
--- a/hw/virtio/virtio-pci.h
+++ b/hw/virtio/virtio-pci.h
@@ -41,6 +41,7 @@ enum {
VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT,
VIRTIO_PCI_FLAG_INIT_PM_BIT,
VIRTIO_PCI_FLAG_INIT_FLR_BIT,
+ VIRTIO_PCI_FLAG_AER_BIT,
};
/* Need to activate work-arounds for buggy guests at vmstate load. */
@@ -80,6 +81,9 @@ enum {
/* Init Function Level Reset capability */
#define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
+/* Advanced Error Reporting capability */
+#define VIRTIO_PCI_FLAG_AER (1 << VIRTIO_PCI_FLAG_AER_BIT)
+
typedef struct {
MSIMessage msg;
int virq;
--
2.29.2
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v4 2/2] hw/virtio-pci Added AER capability.
2020-12-03 13:25 ` [PATCH v4 2/2] hw/virtio-pci Added AER capability Andrew Melnychenko
@ 2020-12-03 21:57 ` Michael S. Tsirkin
0 siblings, 0 replies; 5+ messages in thread
From: Michael S. Tsirkin @ 2020-12-03 21:57 UTC (permalink / raw)
To: Andrew Melnychenko; +Cc: intel-wired-lan, qemu-devel, alexander.duyck
On Thu, Dec 03, 2020 at 03:25:17PM +0200, Andrew Melnychenko wrote:
> From: Andrew <andrew@daynix.com>
>
> Added AER capability for virtio-pci devices.
> Also added property for devices, by default AER is disabled.
>
> Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
> ---
> hw/virtio/virtio-pci.c | 16 ++++++++++++++++
> hw/virtio/virtio-pci.h | 4 ++++
> 2 files changed, 20 insertions(+)
>
> diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
> index ceaa233129..f863f69ede 100644
> --- a/hw/virtio/virtio-pci.c
> +++ b/hw/virtio/virtio-pci.c
> @@ -1817,6 +1817,12 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
> */
> pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
>
> + if (proxy->flags & VIRTIO_PCI_FLAG_AER) {
> + pcie_aer_init(pci_dev, PCI_ERR_VER, last_pcie_cap_offset,
> + PCI_ERR_SIZEOF, NULL);
> + last_pcie_cap_offset += PCI_ERR_SIZEOF;
> + }
> +
What I dislike here is that the property can be added to
pci devices (not express) and will apparently succeed.
Pls add code to validate and fail init.
> if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {
> /* Init error enabling flags */
> pcie_cap_deverr_init(pci_dev);
> @@ -1858,7 +1864,15 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
>
> static void virtio_pci_exit(PCIDevice *pci_dev)
> {
> + VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);
> + bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&
> + !pci_bus_is_root(pci_get_bus(pci_dev));
> +
> msix_uninit_exclusive_bar(pci_dev);
> + if (proxy->flags & VIRTIO_PCI_FLAG_AER && pcie_port &&
> + pci_is_express(pci_dev)) {
> + pcie_aer_exit(pci_dev);
> + }
> }
>
> static void virtio_pci_reset(DeviceState *qdev)
> @@ -1911,6 +1925,8 @@ static Property virtio_pci_properties[] = {
> VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
> DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
> VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
> + DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
> + VIRTIO_PCI_FLAG_AER_BIT, false),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/hw/virtio/virtio-pci.h b/hw/virtio/virtio-pci.h
> index 06e2af12de..d7d5d403a9 100644
> --- a/hw/virtio/virtio-pci.h
> +++ b/hw/virtio/virtio-pci.h
> @@ -41,6 +41,7 @@ enum {
> VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT,
> VIRTIO_PCI_FLAG_INIT_PM_BIT,
> VIRTIO_PCI_FLAG_INIT_FLR_BIT,
> + VIRTIO_PCI_FLAG_AER_BIT,
> };
>
> /* Need to activate work-arounds for buggy guests at vmstate load. */
> @@ -80,6 +81,9 @@ enum {
> /* Init Function Level Reset capability */
> #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
>
> +/* Advanced Error Reporting capability */
> +#define VIRTIO_PCI_FLAG_AER (1 << VIRTIO_PCI_FLAG_AER_BIT)
> +
> typedef struct {
> MSIMessage msg;
> int virq;
> --
> 2.29.2
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-12-03 21:58 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2020-12-03 13:25 [PATCH v4 0/2] hw/virtio-pci: AER capability Andrew Melnychenko
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2020-12-03 13:25 ` [PATCH v4 2/2] hw/virtio-pci Added AER capability Andrew Melnychenko
2020-12-03 21:57 ` Michael S. Tsirkin
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2020-12-03 11:07 ` [PATCH v4 1/2] hw/virtio-pci Added counter for pcie capabilities offsets andrew
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