From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Jiahui Cen <cenjiahui@huawei.com>,
Eduardo Habkost <ehabkost@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Yubo Miao <miaoyubo@huawei.com>,
Igor Mammedov <imammedo@redhat.com>,
Paolo Bonzini <pbonzini@redhat.com>
Subject: [PULL v2 11/65] acpi: Extract crs build form acpi_build.c
Date: Wed, 9 Dec 2020 13:07:33 -0500 [thread overview]
Message-ID: <20201209180546.721296-12-mst@redhat.com> (raw)
In-Reply-To: <20201209180546.721296-1-mst@redhat.com>
From: Yubo Miao <miaoyubo@huawei.com>
Extract crs build form acpi_build.c, the function could also be used
to build the crs for pxbs for arm. The resources are composed by two parts:
1. The bar space of pci-bridge/pcie-root-ports
2. The resources needed by devices behind PXBs.
The base and limit of memory/io are obtained from the config via two APIs:
pci_bridge_get_base and pci_bridge_get_limit
Signed-off-by: Yubo Miao <miaoyubo@huawei.com>
Signed-off-by: Jiahui Cen <cenjiahui@huawei.com>
Message-Id: <20201119014841.7298-5-cenjiahui@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
include/hw/acpi/aml-build.h | 22 +++
hw/acpi/aml-build.c | 285 +++++++++++++++++++++++++++++++++++
hw/i386/acpi-build.c | 293 ------------------------------------
3 files changed, 307 insertions(+), 293 deletions(-)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index fe0055fffb..e727bea1bc 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -224,6 +224,20 @@ struct AcpiBuildTables {
BIOSLinker *linker;
} AcpiBuildTables;
+typedef
+struct CrsRangeEntry {
+ uint64_t base;
+ uint64_t limit;
+} CrsRangeEntry;
+
+typedef
+struct CrsRangeSet {
+ GPtrArray *io_ranges;
+ GPtrArray *mem_ranges;
+ GPtrArray *mem_64bit_ranges;
+} CrsRangeSet;
+
+
/*
* ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors
* Serial Bus Type
@@ -432,6 +446,14 @@ build_append_gas_from_struct(GArray *table, const struct AcpiGenericAddress *s)
s->access_width, s->address);
}
+void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit);
+void crs_replace_with_free_ranges(GPtrArray *ranges,
+ uint64_t start, uint64_t end);
+void crs_range_set_init(CrsRangeSet *range_set);
+void crs_range_set_free(CrsRangeSet *range_set);
+
+Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set);
+
void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
uint64_t len, int node, MemoryAffinityFlags flags);
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 3792ba96ce..f976aa667b 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -27,6 +27,9 @@
#include "sysemu/numa.h"
#include "hw/boards.h"
#include "hw/acpi/tpm.h"
+#include "hw/pci/pci_host.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci/pci_bridge.h"
static GArray *build_alloc_array(void)
{
@@ -55,6 +58,128 @@ static void build_append_array(GArray *array, GArray *val)
#define ACPI_NAMESEG_LEN 4
+void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
+{
+ CrsRangeEntry *entry;
+
+ entry = g_malloc(sizeof(*entry));
+ entry->base = base;
+ entry->limit = limit;
+
+ g_ptr_array_add(ranges, entry);
+}
+
+static void crs_range_free(gpointer data)
+{
+ CrsRangeEntry *entry = (CrsRangeEntry *)data;
+ g_free(entry);
+}
+
+void crs_range_set_init(CrsRangeSet *range_set)
+{
+ range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
+ range_set->mem_64bit_ranges =
+ g_ptr_array_new_with_free_func(crs_range_free);
+}
+
+void crs_range_set_free(CrsRangeSet *range_set)
+{
+ g_ptr_array_free(range_set->io_ranges, true);
+ g_ptr_array_free(range_set->mem_ranges, true);
+ g_ptr_array_free(range_set->mem_64bit_ranges, true);
+}
+
+static gint crs_range_compare(gconstpointer a, gconstpointer b)
+{
+ CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
+ CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
+
+ if (entry_a->base < entry_b->base) {
+ return -1;
+ } else if (entry_a->base > entry_b->base) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/*
+ * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
+ * interval, computes the 'free' ranges from the same interval.
+ * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
+ * will return { [base - a1], [a2 - b1], [b2 - limit] }.
+ */
+void crs_replace_with_free_ranges(GPtrArray *ranges,
+ uint64_t start, uint64_t end)
+{
+ GPtrArray *free_ranges = g_ptr_array_new();
+ uint64_t free_base = start;
+ int i;
+
+ g_ptr_array_sort(ranges, crs_range_compare);
+ for (i = 0; i < ranges->len; i++) {
+ CrsRangeEntry *used = g_ptr_array_index(ranges, i);
+
+ if (free_base < used->base) {
+ crs_range_insert(free_ranges, free_base, used->base - 1);
+ }
+
+ free_base = used->limit + 1;
+ }
+
+ if (free_base < end) {
+ crs_range_insert(free_ranges, free_base, end);
+ }
+
+ g_ptr_array_set_size(ranges, 0);
+ for (i = 0; i < free_ranges->len; i++) {
+ g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
+ }
+
+ g_ptr_array_free(free_ranges, true);
+}
+
+/*
+ * crs_range_merge - merges adjacent ranges in the given array.
+ * Array elements are deleted and replaced with the merged ranges.
+ */
+static void crs_range_merge(GPtrArray *range)
+{
+ GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
+ CrsRangeEntry *entry;
+ uint64_t range_base, range_limit;
+ int i;
+
+ if (!range->len) {
+ return;
+ }
+
+ g_ptr_array_sort(range, crs_range_compare);
+
+ entry = g_ptr_array_index(range, 0);
+ range_base = entry->base;
+ range_limit = entry->limit;
+ for (i = 1; i < range->len; i++) {
+ entry = g_ptr_array_index(range, i);
+ if (entry->base - 1 == range_limit) {
+ range_limit = entry->limit;
+ } else {
+ crs_range_insert(tmp, range_base, range_limit);
+ range_base = entry->base;
+ range_limit = entry->limit;
+ }
+ }
+ crs_range_insert(tmp, range_base, range_limit);
+
+ g_ptr_array_set_size(range, 0);
+ for (i = 0; i < tmp->len; i++) {
+ entry = g_ptr_array_index(tmp, i);
+ crs_range_insert(range, entry->base, entry->limit);
+ }
+ g_ptr_array_free(tmp, true);
+}
+
static void
build_append_nameseg(GArray *array, const char *seg)
{
@@ -1951,6 +2076,166 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
tpm2_ptr, "TPM2", table_data->len - tpm2_start, 4, NULL, NULL);
}
+Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
+{
+ Aml *crs = aml_resource_template();
+ CrsRangeSet temp_range_set;
+ CrsRangeEntry *entry;
+ uint8_t max_bus = pci_bus_num(host->bus);
+ uint8_t type;
+ int devfn;
+ int i;
+
+ crs_range_set_init(&temp_range_set);
+ for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
+ uint64_t range_base, range_limit;
+ PCIDevice *dev = host->bus->devices[devfn];
+
+ if (!dev) {
+ continue;
+ }
+
+ for (i = 0; i < PCI_NUM_REGIONS; i++) {
+ PCIIORegion *r = &dev->io_regions[i];
+
+ range_base = r->addr;
+ range_limit = r->addr + r->size - 1;
+
+ /*
+ * Work-around for old bioses
+ * that do not support multiple root buses
+ */
+ if (!range_base || range_base > range_limit) {
+ continue;
+ }
+
+ if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
+ crs_range_insert(temp_range_set.io_ranges,
+ range_base, range_limit);
+ } else { /* "memory" */
+ uint64_t length = range_limit - range_base + 1;
+ if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
+ crs_range_insert(temp_range_set.mem_ranges, range_base,
+ range_limit);
+ } else {
+ crs_range_insert(temp_range_set.mem_64bit_ranges,
+ range_base, range_limit);
+ }
+ }
+ }
+
+ type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
+ if (type == PCI_HEADER_TYPE_BRIDGE) {
+ uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
+ if (subordinate > max_bus) {
+ max_bus = subordinate;
+ }
+
+ range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
+ range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
+
+ /*
+ * Work-around for old bioses
+ * that do not support multiple root buses
+ */
+ if (range_base && range_base <= range_limit) {
+ crs_range_insert(temp_range_set.io_ranges,
+ range_base, range_limit);
+ }
+
+ range_base =
+ pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
+ range_limit =
+ pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
+
+ /*
+ * Work-around for old bioses
+ * that do not support multiple root buses
+ */
+ if (range_base && range_base <= range_limit) {
+ uint64_t length = range_limit - range_base + 1;
+ if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
+ crs_range_insert(temp_range_set.mem_ranges,
+ range_base, range_limit);
+ } else {
+ crs_range_insert(temp_range_set.mem_64bit_ranges,
+ range_base, range_limit);
+ }
+ }
+
+ range_base =
+ pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
+ range_limit =
+ pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
+
+ /*
+ * Work-around for old bioses
+ * that do not support multiple root buses
+ */
+ if (range_base && range_base <= range_limit) {
+ uint64_t length = range_limit - range_base + 1;
+ if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
+ crs_range_insert(temp_range_set.mem_ranges,
+ range_base, range_limit);
+ } else {
+ crs_range_insert(temp_range_set.mem_64bit_ranges,
+ range_base, range_limit);
+ }
+ }
+ }
+ }
+
+ crs_range_merge(temp_range_set.io_ranges);
+ for (i = 0; i < temp_range_set.io_ranges->len; i++) {
+ entry = g_ptr_array_index(temp_range_set.io_ranges, i);
+ aml_append(crs,
+ aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_POS_DECODE, AML_ENTIRE_RANGE,
+ 0, entry->base, entry->limit, 0,
+ entry->limit - entry->base + 1));
+ crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
+ }
+
+ crs_range_merge(temp_range_set.mem_ranges);
+ for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
+ entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
+ assert(entry->limit <= UINT32_MAX &&
+ (entry->limit - entry->base + 1) <= UINT32_MAX);
+ aml_append(crs,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED, AML_NON_CACHEABLE,
+ AML_READ_WRITE,
+ 0, entry->base, entry->limit, 0,
+ entry->limit - entry->base + 1));
+ crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
+ }
+
+ crs_range_merge(temp_range_set.mem_64bit_ranges);
+ for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
+ entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
+ aml_append(crs,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED, AML_NON_CACHEABLE,
+ AML_READ_WRITE,
+ 0, entry->base, entry->limit, 0,
+ entry->limit - entry->base + 1));
+ crs_range_insert(range_set->mem_64bit_ranges,
+ entry->base, entry->limit);
+ }
+
+ crs_range_set_free(&temp_range_set);
+
+ aml_append(crs,
+ aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ 0,
+ pci_bus_num(host->bus),
+ max_bus,
+ 0,
+ max_bus - pci_bus_num(host->bus) + 1));
+
+ return crs;
+}
+
/* ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors */
static Aml *aml_serial_bus_device(uint8_t serial_bus_type, uint8_t flags,
uint16_t type_flags,
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 1f5c211245..76e27f8fad 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -613,299 +613,6 @@ static Aml *build_prt(bool is_pci0_prt)
return method;
}
-typedef struct CrsRangeEntry {
- uint64_t base;
- uint64_t limit;
-} CrsRangeEntry;
-
-static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
-{
- CrsRangeEntry *entry;
-
- entry = g_malloc(sizeof(*entry));
- entry->base = base;
- entry->limit = limit;
-
- g_ptr_array_add(ranges, entry);
-}
-
-static void crs_range_free(gpointer data)
-{
- CrsRangeEntry *entry = (CrsRangeEntry *)data;
- g_free(entry);
-}
-
-typedef struct CrsRangeSet {
- GPtrArray *io_ranges;
- GPtrArray *mem_ranges;
- GPtrArray *mem_64bit_ranges;
- } CrsRangeSet;
-
-static void crs_range_set_init(CrsRangeSet *range_set)
-{
- range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
- range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
- range_set->mem_64bit_ranges =
- g_ptr_array_new_with_free_func(crs_range_free);
-}
-
-static void crs_range_set_free(CrsRangeSet *range_set)
-{
- g_ptr_array_free(range_set->io_ranges, true);
- g_ptr_array_free(range_set->mem_ranges, true);
- g_ptr_array_free(range_set->mem_64bit_ranges, true);
-}
-
-static gint crs_range_compare(gconstpointer a, gconstpointer b)
-{
- CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
- CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
-
- if (entry_a->base < entry_b->base) {
- return -1;
- } else if (entry_a->base > entry_b->base) {
- return 1;
- } else {
- return 0;
- }
-}
-
-/*
- * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
- * interval, computes the 'free' ranges from the same interval.
- * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
- * will return { [base - a1], [a2 - b1], [b2 - limit] }.
- */
-static void crs_replace_with_free_ranges(GPtrArray *ranges,
- uint64_t start, uint64_t end)
-{
- GPtrArray *free_ranges = g_ptr_array_new();
- uint64_t free_base = start;
- int i;
-
- g_ptr_array_sort(ranges, crs_range_compare);
- for (i = 0; i < ranges->len; i++) {
- CrsRangeEntry *used = g_ptr_array_index(ranges, i);
-
- if (free_base < used->base) {
- crs_range_insert(free_ranges, free_base, used->base - 1);
- }
-
- free_base = used->limit + 1;
- }
-
- if (free_base < end) {
- crs_range_insert(free_ranges, free_base, end);
- }
-
- g_ptr_array_set_size(ranges, 0);
- for (i = 0; i < free_ranges->len; i++) {
- g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
- }
-
- g_ptr_array_free(free_ranges, true);
-}
-
-/*
- * crs_range_merge - merges adjacent ranges in the given array.
- * Array elements are deleted and replaced with the merged ranges.
- */
-static void crs_range_merge(GPtrArray *range)
-{
- GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
- CrsRangeEntry *entry;
- uint64_t range_base, range_limit;
- int i;
-
- if (!range->len) {
- return;
- }
-
- g_ptr_array_sort(range, crs_range_compare);
-
- entry = g_ptr_array_index(range, 0);
- range_base = entry->base;
- range_limit = entry->limit;
- for (i = 1; i < range->len; i++) {
- entry = g_ptr_array_index(range, i);
- if (entry->base - 1 == range_limit) {
- range_limit = entry->limit;
- } else {
- crs_range_insert(tmp, range_base, range_limit);
- range_base = entry->base;
- range_limit = entry->limit;
- }
- }
- crs_range_insert(tmp, range_base, range_limit);
-
- g_ptr_array_set_size(range, 0);
- for (i = 0; i < tmp->len; i++) {
- entry = g_ptr_array_index(tmp, i);
- crs_range_insert(range, entry->base, entry->limit);
- }
- g_ptr_array_free(tmp, true);
-}
-
-static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
-{
- Aml *crs = aml_resource_template();
- CrsRangeSet temp_range_set;
- CrsRangeEntry *entry;
- uint8_t max_bus = pci_bus_num(host->bus);
- uint8_t type;
- int devfn;
- int i;
-
- crs_range_set_init(&temp_range_set);
- for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
- uint64_t range_base, range_limit;
- PCIDevice *dev = host->bus->devices[devfn];
-
- if (!dev) {
- continue;
- }
-
- for (i = 0; i < PCI_NUM_REGIONS; i++) {
- PCIIORegion *r = &dev->io_regions[i];
-
- range_base = r->addr;
- range_limit = r->addr + r->size - 1;
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (!range_base || range_base > range_limit) {
- continue;
- }
-
- if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
- crs_range_insert(temp_range_set.io_ranges,
- range_base, range_limit);
- } else { /* "memory" */
- uint64_t length = range_limit - range_base + 1;
- if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
- crs_range_insert(temp_range_set.mem_ranges, range_base,
- range_limit);
- } else {
- crs_range_insert(temp_range_set.mem_64bit_ranges,
- range_base, range_limit);
- }
- }
- }
-
- type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
- if (type == PCI_HEADER_TYPE_BRIDGE) {
- uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
- if (subordinate > max_bus) {
- max_bus = subordinate;
- }
-
- range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
- range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (range_base && range_base <= range_limit) {
- crs_range_insert(temp_range_set.io_ranges,
- range_base, range_limit);
- }
-
- range_base =
- pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
- range_limit =
- pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (range_base && range_base <= range_limit) {
- uint64_t length = range_limit - range_base + 1;
- if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
- crs_range_insert(temp_range_set.mem_ranges,
- range_base, range_limit);
- } else {
- crs_range_insert(temp_range_set.mem_64bit_ranges,
- range_base, range_limit);
- }
- }
-
- range_base =
- pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
- range_limit =
- pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
-
- /*
- * Work-around for old bioses
- * that do not support multiple root buses
- */
- if (range_base && range_base <= range_limit) {
- uint64_t length = range_limit - range_base + 1;
- if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
- crs_range_insert(temp_range_set.mem_ranges,
- range_base, range_limit);
- } else {
- crs_range_insert(temp_range_set.mem_64bit_ranges,
- range_base, range_limit);
- }
- }
- }
- }
-
- crs_range_merge(temp_range_set.io_ranges);
- for (i = 0; i < temp_range_set.io_ranges->len; i++) {
- entry = g_ptr_array_index(temp_range_set.io_ranges, i);
- aml_append(crs,
- aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
- AML_POS_DECODE, AML_ENTIRE_RANGE,
- 0, entry->base, entry->limit, 0,
- entry->limit - entry->base + 1));
- crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
- }
-
- crs_range_merge(temp_range_set.mem_ranges);
- for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
- entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
- assert(entry->limit <= UINT32_MAX &&
- (entry->limit - entry->base + 1) <= UINT32_MAX);
- aml_append(crs,
- aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
- AML_MAX_FIXED, AML_NON_CACHEABLE,
- AML_READ_WRITE,
- 0, entry->base, entry->limit, 0,
- entry->limit - entry->base + 1));
- crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
- }
-
- crs_range_merge(temp_range_set.mem_64bit_ranges);
- for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
- entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
- aml_append(crs,
- aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
- AML_MAX_FIXED, AML_NON_CACHEABLE,
- AML_READ_WRITE,
- 0, entry->base, entry->limit, 0,
- entry->limit - entry->base + 1));
- crs_range_insert(range_set->mem_64bit_ranges,
- entry->base, entry->limit);
- }
-
- crs_range_set_free(&temp_range_set);
-
- aml_append(crs,
- aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
- 0,
- pci_bus_num(host->bus),
- max_bus,
- 0,
- max_bus - pci_bus_num(host->bus) + 1));
-
- return crs;
-}
-
static void build_hpet_aml(Aml *table)
{
Aml *crs;
--
MST
next prev parent reply other threads:[~2020-12-09 18:25 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-09 18:06 [PULL v2 00/65] pc,pci,virtio: fixes, cleanups Michael S. Tsirkin
2020-12-09 18:06 ` [PULL v2 01/65] vhost-user-scsi: Fix memleaks in vus_proc_req() Michael S. Tsirkin
2020-12-09 18:06 ` [PULL v2 02/65] memory: Rename memory_region_notify_one to memory_region_notify_iommu_one Michael S. Tsirkin
2020-12-09 18:06 ` [PULL v2 03/65] memory: Add IOMMUTLBEvent Michael S. Tsirkin
2020-12-09 18:06 ` [PULL v2 04/65] memory: Add IOMMU_NOTIFIER_DEVIOTLB_UNMAP IOMMUTLBNotificationType Michael S. Tsirkin
2020-12-09 18:06 ` [PULL v2 05/65] intel_iommu: Skip page walking on device iotlb invalidations Michael S. Tsirkin
2020-12-09 18:07 ` [PULL v2 06/65] memory: Skip bad range assertion if notifier is DEVIOTLB_UNMAP type Michael S. Tsirkin
2020-12-09 18:07 ` [PULL v2 07/65] virtio: reset device on bad guest index in virtio_load() Michael S. Tsirkin
2020-12-09 18:07 ` [PULL v2 08/65] acpi/gpex: Extract two APIs from acpi_dsdt_add_pci Michael S. Tsirkin
2020-12-09 18:07 ` [PULL v2 09/65] fw_cfg: Refactor extra pci roots addition Michael S. Tsirkin
2020-12-09 18:07 ` [PULL v2 10/65] hw/arm/virt: Write extra pci roots into fw_cfg Michael S. Tsirkin
2020-12-09 18:07 ` Michael S. Tsirkin [this message]
2020-12-09 18:07 ` [PULL v2 12/65] acpi/gpex: Build tables for pxb Michael S. Tsirkin
2020-12-09 18:07 ` [PULL v2 13/65] acpi: Align the size to 128k Michael S. Tsirkin
2020-12-09 18:07 ` [PULL v2 14/65] unit-test: The files changed Michael S. Tsirkin
2020-12-09 18:07 ` [PULL v2 15/65] unit-test: Add testcase for pxb Michael S. Tsirkin
2020-12-09 18:07 ` [PULL v2 16/65] unit-test: Add the binary file and clear diff.h Michael S. Tsirkin
2020-12-09 18:07 ` [PULL v2 17/65] failover: fix indentantion Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 18/65] failover: Use always atomics for primary_should_be_hidden Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 19/65] failover: primary bus is only used once, and where it is set Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 20/65] failover: Remove unused parameter Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 21/65] failover: Remove external partially_hotplugged property Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 22/65] failover: qdev_device_add() returns err or dev set Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 23/65] failover: Rename bool to failover_primary_hidden Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 24/65] failover: g_strcmp0() knows how to handle NULL Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 25/65] failover: Remove primary_device_opts Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 26/65] failover: remove standby_id variable Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 27/65] failover: Remove primary_device_dict Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 28/65] failover: Remove memory leak Michael S. Tsirkin
2020-12-09 18:08 ` [PULL v2 29/65] failover: simplify virtio_net_find_primary() Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 30/65] failover: should_be_hidden() should take a bool Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 31/65] failover: Rename function to hide_device() Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 32/65] failover: virtio_net_connect_failover_devices() does nothing Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 33/65] failover: Rename to failover_find_primary_device() Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 34/65] failover: simplify qdev_device_add() failover case Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 35/65] failover: simplify qdev_device_add() Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 36/65] failover: make sure that id always exist Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 37/65] failover: remove failover_find_primary_device() error parameter Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 38/65] failover: split failover_find_primary_device_id() Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 39/65] failover: We don't need to cache primary_device_id anymore Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 40/65] failover: Caller of this two functions already have primary_dev Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 41/65] failover: simplify failover_unplug_primary Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 42/65] failover: Remove primary_dev member Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 43/65] hw: add compat machines for 6.0 Michael S. Tsirkin
2020-12-09 18:09 ` [PULL v2 44/65] libvhost-user: replace qemu/bswap.h with glibc endian.h Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 45/65] libvhost-user: replace qemu/memfd.h usage Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 46/65] libvhost-user: remove qemu/compiler.h usage Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 47/65] libvhost-user: drop qemu/osdep.h dependency Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 48/65] libvhost-user: make it a meson subproject Michael S. Tsirkin
2020-12-10 16:09 ` Peter Maydell
2020-12-10 16:17 ` Paolo Bonzini
2020-12-10 16:26 ` Peter Maydell
2020-12-09 18:10 ` [PULL v2 49/65] libvhost-user: add a simple link test without glib Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 50/65] .gitlab-ci: add build-libvhost-user Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 51/65] contrib/vhost-user-blk: avoid g_return_val_if() input validation Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 52/65] contrib/vhost-user-gpu: " Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 53/65] contrib/vhost-user-input: " Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 54/65] block/export: " Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 55/65] hw/i386/pc: add max combined fw size as machine configuration option Michael S. Tsirkin
2020-12-09 18:10 ` [PULL v2 56/65] acpi: cpuhp: introduce 'firmware performs eject' status/control bits Michael S. Tsirkin
2020-12-09 18:11 ` [PULL v2 57/65] x86: acpi: introduce AcpiPmInfo::smi_on_cpu_unplug Michael S. Tsirkin
2020-12-09 18:11 ` [PULL v2 58/65] tests/acpi: allow expected files change Michael S. Tsirkin
2020-12-09 18:11 ` [PULL v2 59/65] x86: acpi: let the firmware handle pending "CPU remove" events in SMM Michael S. Tsirkin
2020-12-09 18:11 ` [PULL v2 60/65] tests/acpi: update expected files Michael S. Tsirkin
2020-12-09 18:11 ` [PULL v2 61/65] x86: ich9: factor out "guest_cpu_hotplug_features" Michael S. Tsirkin
2020-12-09 18:11 ` [PULL v2 62/65] x86: ich9: let firmware negotiate 'CPU hot-unplug with SMI' feature Michael S. Tsirkin
2020-12-09 18:11 ` [PULL v2 63/65] pcie_aer: Fix help message of pcie_aer_inject_error command Michael S. Tsirkin
2020-12-09 18:11 ` [PULL v2 64/65] hw/virtio-pci Added counter for pcie capabilities offsets Michael S. Tsirkin
2020-12-09 18:11 ` [PULL v2 65/65] hw/virtio-pci Added AER capability Michael S. Tsirkin
2020-12-09 21:42 ` [PULL v2 00/65] pc,pci,virtio: fixes, cleanups Peter Maydell
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