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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/36] i.MX6: Fix bad printf format specifiers
Date: Thu, 10 Dec 2020 11:47:30 +0000	[thread overview]
Message-ID: <20201210114756.16501-11-peter.maydell@linaro.org> (raw)
In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org>

From: Alex Chen <alex.chen@huawei.com>

We should use printf format specifier "%u" instead of "%d" for
argument of type "unsigned int".

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Alex Chen <alex.chen@huawei.com>
Message-id: 20201126111109.112238-4-alex.chen@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/misc/imx6_ccm.c | 20 ++++++++++----------
 hw/misc/imx6_src.c |  2 +-
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
index 7fec8f0a476..cb740427eca 100644
--- a/hw/misc/imx6_ccm.c
+++ b/hw/misc/imx6_ccm.c
@@ -96,7 +96,7 @@ static const char *imx6_ccm_reg_name(uint32_t reg)
     case CCM_CMEOR:
         return "CMEOR";
     default:
-        sprintf(unknown, "%d ?", reg);
+        sprintf(unknown, "%u ?", reg);
         return unknown;
     }
 }
@@ -235,7 +235,7 @@ static const char *imx6_analog_reg_name(uint32_t reg)
     case USB_ANALOG_DIGPROG:
         return "USB_ANALOG_DIGPROG";
     default:
-        sprintf(unknown, "%d ?", reg);
+        sprintf(unknown, "%u ?", reg);
         return unknown;
     }
 }
@@ -263,7 +263,7 @@ static uint64_t imx6_analog_get_pll2_clk(IMX6CCMState *dev)
         freq *= 20;
     }
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -275,7 +275,7 @@ static uint64_t imx6_analog_get_pll2_pfd0_clk(IMX6CCMState *dev)
     freq = imx6_analog_get_pll2_clk(dev) * 18
            / EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD0_FRAC);
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -287,7 +287,7 @@ static uint64_t imx6_analog_get_pll2_pfd2_clk(IMX6CCMState *dev)
     freq = imx6_analog_get_pll2_clk(dev) * 18
            / EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD2_FRAC);
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -315,7 +315,7 @@ static uint64_t imx6_analog_get_periph_clk(IMX6CCMState *dev)
         break;
     }
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -327,7 +327,7 @@ static uint64_t imx6_ccm_get_ahb_clk(IMX6CCMState *dev)
     freq = imx6_analog_get_periph_clk(dev)
            / (1 + EXTRACT(dev->ccm[CCM_CBCDR], AHB_PODF));
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -339,7 +339,7 @@ static uint64_t imx6_ccm_get_ipg_clk(IMX6CCMState *dev)
     freq = imx6_ccm_get_ahb_clk(dev)
            / (1 + EXTRACT(dev->ccm[CCM_CBCDR], IPG_PODF));
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -351,7 +351,7 @@ static uint64_t imx6_ccm_get_per_clk(IMX6CCMState *dev)
     freq = imx6_ccm_get_ipg_clk(dev)
            / (1 + EXTRACT(dev->ccm[CCM_CSCMR1], PERCLK_PODF));
 
-    DPRINTF("freq = %d\n", (uint32_t)freq);
+    DPRINTF("freq = %u\n", (uint32_t)freq);
 
     return freq;
 }
@@ -385,7 +385,7 @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
         break;
     }
 
-    DPRINTF("Clock = %d) = %d\n", clock, freq);
+    DPRINTF("Clock = %d) = %u\n", clock, freq);
 
     return freq;
 }
diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
index dd99cc7acf0..79f43759113 100644
--- a/hw/misc/imx6_src.c
+++ b/hw/misc/imx6_src.c
@@ -68,7 +68,7 @@ static const char *imx6_src_reg_name(uint32_t reg)
     case SRC_GPR10:
         return "SRC_GPR10";
     default:
-        sprintf(unknown, "%d ?", reg);
+        sprintf(unknown, "%u ?", reg);
         return unknown;
     }
 }
-- 
2.20.1



  parent reply	other threads:[~2020-12-10 11:50 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-10 11:47 [PULL 00/36] target-arm queue Peter Maydell
2020-12-10 11:47 ` [PULL 01/36] hw/arm/smmuv3: Fix up L1STD_SPAN decoding Peter Maydell
2020-12-10 11:47 ` [PULL 02/36] hw/net/can: Introduce Xilinx ZynqMP CAN controller Peter Maydell
2020-12-10 11:47 ` [PULL 03/36] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers Peter Maydell
2020-12-10 11:47 ` [PULL 04/36] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller Peter Maydell
2020-12-10 11:47 ` [PULL 05/36] MAINTAINERS: Add maintainer entry " Peter Maydell
2020-12-10 11:47 ` [PULL 06/36] sbsa-ref: allow to use Cortex-A53/57/72 cpus Peter Maydell
2020-12-10 11:47 ` [PULL 07/36] tests/qtest/npcm7xx_rng-test: dump random data on failure Peter Maydell
2020-12-10 11:47 ` [PULL 08/36] i.MX25: Fix bad printf format specifiers Peter Maydell
2020-12-10 11:47 ` [PULL 09/36] i.MX31: " Peter Maydell
2020-12-10 11:47 ` Peter Maydell [this message]
2020-12-10 11:47 ` [PULL 11/36] i.MX6ul: " Peter Maydell
2020-12-10 11:47 ` [PULL 12/36] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault Peter Maydell
2020-12-10 11:47 ` [PULL 13/36] target/arm: Implement v8.1M PXN extension Peter Maydell
2020-12-10 11:47 ` [PULL 14/36] target/arm: Don't clobber ID_PFR1.Security on M-profile cores Peter Maydell
2020-12-10 11:47 ` [PULL 15/36] target/arm: Implement VSCCLRM insn Peter Maydell
2020-12-10 11:47 ` [PULL 16/36] target/arm: Implement CLRM instruction Peter Maydell
2020-12-10 11:47 ` [PULL 17/36] target/arm: Enforce M-profile VMRS/VMSR register restrictions Peter Maydell
2020-12-10 11:47 ` [PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling Peter Maydell
2020-12-10 11:47 ` [PULL 19/36] target/arm: Move general-use constant expanders up in translate.c Peter Maydell
2020-12-10 11:47 ` [PULL 20/36] target/arm: Implement VLDR/VSTR system register Peter Maydell
2020-12-10 11:47 ` [PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc Peter Maydell
2020-12-10 11:47 ` [PULL 22/36] target/arm: Use new FPCR_NZCV_MASK constant Peter Maydell
2020-12-10 11:47 ` [PULL 23/36] target/arm: Factor out preserve-fp-state from full_vfp_access_check() Peter Maydell
2020-12-10 11:47 ` [PULL 24/36] target/arm: Implement FPCXT_S fp system register Peter Maydell
2020-12-10 11:47 ` [PULL 25/36] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M Peter Maydell
2020-12-10 11:47 ` [PULL 26/36] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry Peter Maydell
2020-12-10 11:47 ` [PULL 27/36] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures Peter Maydell
2020-12-10 11:47 ` [PULL 28/36] target/arm: Implement v8.1M REVIDR register Peter Maydell
2020-12-10 11:47 ` [PULL 29/36] target/arm: Implement new v8.1M NOCP check for exception return Peter Maydell
2020-12-10 11:47 ` [PULL 30/36] target/arm: Implement new v8.1M VLLDM and VLSTM encodings Peter Maydell
2020-12-10 11:47 ` [PULL 31/36] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit Peter Maydell
2020-12-10 11:47 ` [PULL 32/36] target/arm: Implement CCR_S.TRD behaviour for SG insns Peter Maydell
2020-12-10 11:47 ` [PULL 33/36] hw/intc/armv7m_nvic: Fix "return from inactive handler" check Peter Maydell
2020-12-10 11:47 ` [PULL 34/36] target/arm: Implement M-profile "minimal RAS implementation" Peter Maydell
2020-12-10 11:47 ` [PULL 35/36] hw/intc/armv7m_nvic: Implement read/write for RAS register block Peter Maydell
2020-12-10 11:47 ` [PULL 36/36] hw/arm/armv7m: Correct typo in QOM object name Peter Maydell
2020-12-10 12:51 ` [PULL 00/36] target-arm queue Peter Maydell

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