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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/36] sbsa-ref: allow to use Cortex-A53/57/72 cpus
Date: Thu, 10 Dec 2020 11:47:26 +0000	[thread overview]
Message-ID: <20201210114756.16501-7-peter.maydell@linaro.org> (raw)
In-Reply-To: <20201210114756.16501-1-peter.maydell@linaro.org>

From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

Trusted Firmware now supports A72 on sbsa-ref by default [1] so enable
it for QEMU as well. A53 was already enabled there.

1. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7117

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201120141705.246690-1-marcin.juszkiewicz@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 7d9e180c0db..4a5ea42938a 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -143,6 +143,24 @@ static const int sbsa_ref_irqmap[] = {
     [SBSA_GWDT] = 16,
 };
 
+static const char * const valid_cpus[] = {
+    ARM_CPU_TYPE_NAME("cortex-a53"),
+    ARM_CPU_TYPE_NAME("cortex-a57"),
+    ARM_CPU_TYPE_NAME("cortex-a72"),
+};
+
+static bool cpu_type_valid(const char *cpu)
+{
+    int i;
+
+    for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
+        if (strcmp(cpu, valid_cpus[i]) == 0) {
+            return true;
+        }
+    }
+    return false;
+}
+
 static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
 {
     uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
@@ -649,9 +667,8 @@ static void sbsa_ref_init(MachineState *machine)
     const CPUArchIdList *possible_cpus;
     int n, sbsa_max_cpus;
 
-    if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
-        error_report("sbsa-ref: CPU type other than the built-in "
-                     "cortex-a57 not supported");
+    if (!cpu_type_valid(machine->cpu_type)) {
+        error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
         exit(1);
     }
 
-- 
2.20.1



  parent reply	other threads:[~2020-12-10 11:56 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-10 11:47 [PULL 00/36] target-arm queue Peter Maydell
2020-12-10 11:47 ` [PULL 01/36] hw/arm/smmuv3: Fix up L1STD_SPAN decoding Peter Maydell
2020-12-10 11:47 ` [PULL 02/36] hw/net/can: Introduce Xilinx ZynqMP CAN controller Peter Maydell
2020-12-10 11:47 ` [PULL 03/36] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers Peter Maydell
2020-12-10 11:47 ` [PULL 04/36] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller Peter Maydell
2020-12-10 11:47 ` [PULL 05/36] MAINTAINERS: Add maintainer entry " Peter Maydell
2020-12-10 11:47 ` Peter Maydell [this message]
2020-12-10 11:47 ` [PULL 07/36] tests/qtest/npcm7xx_rng-test: dump random data on failure Peter Maydell
2020-12-10 11:47 ` [PULL 08/36] i.MX25: Fix bad printf format specifiers Peter Maydell
2020-12-10 11:47 ` [PULL 09/36] i.MX31: " Peter Maydell
2020-12-10 11:47 ` [PULL 10/36] i.MX6: " Peter Maydell
2020-12-10 11:47 ` [PULL 11/36] i.MX6ul: " Peter Maydell
2020-12-10 11:47 ` [PULL 12/36] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault Peter Maydell
2020-12-10 11:47 ` [PULL 13/36] target/arm: Implement v8.1M PXN extension Peter Maydell
2020-12-10 11:47 ` [PULL 14/36] target/arm: Don't clobber ID_PFR1.Security on M-profile cores Peter Maydell
2020-12-10 11:47 ` [PULL 15/36] target/arm: Implement VSCCLRM insn Peter Maydell
2020-12-10 11:47 ` [PULL 16/36] target/arm: Implement CLRM instruction Peter Maydell
2020-12-10 11:47 ` [PULL 17/36] target/arm: Enforce M-profile VMRS/VMSR register restrictions Peter Maydell
2020-12-10 11:47 ` [PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling Peter Maydell
2020-12-10 11:47 ` [PULL 19/36] target/arm: Move general-use constant expanders up in translate.c Peter Maydell
2020-12-10 11:47 ` [PULL 20/36] target/arm: Implement VLDR/VSTR system register Peter Maydell
2020-12-10 11:47 ` [PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc Peter Maydell
2020-12-10 11:47 ` [PULL 22/36] target/arm: Use new FPCR_NZCV_MASK constant Peter Maydell
2020-12-10 11:47 ` [PULL 23/36] target/arm: Factor out preserve-fp-state from full_vfp_access_check() Peter Maydell
2020-12-10 11:47 ` [PULL 24/36] target/arm: Implement FPCXT_S fp system register Peter Maydell
2020-12-10 11:47 ` [PULL 25/36] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M Peter Maydell
2020-12-10 11:47 ` [PULL 26/36] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry Peter Maydell
2020-12-10 11:47 ` [PULL 27/36] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures Peter Maydell
2020-12-10 11:47 ` [PULL 28/36] target/arm: Implement v8.1M REVIDR register Peter Maydell
2020-12-10 11:47 ` [PULL 29/36] target/arm: Implement new v8.1M NOCP check for exception return Peter Maydell
2020-12-10 11:47 ` [PULL 30/36] target/arm: Implement new v8.1M VLLDM and VLSTM encodings Peter Maydell
2020-12-10 11:47 ` [PULL 31/36] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit Peter Maydell
2020-12-10 11:47 ` [PULL 32/36] target/arm: Implement CCR_S.TRD behaviour for SG insns Peter Maydell
2020-12-10 11:47 ` [PULL 33/36] hw/intc/armv7m_nvic: Fix "return from inactive handler" check Peter Maydell
2020-12-10 11:47 ` [PULL 34/36] target/arm: Implement M-profile "minimal RAS implementation" Peter Maydell
2020-12-10 11:47 ` [PULL 35/36] hw/intc/armv7m_nvic: Implement read/write for RAS register block Peter Maydell
2020-12-10 11:47 ` [PULL 36/36] hw/arm/armv7m: Correct typo in QOM object name Peter Maydell
2020-12-10 12:51 ` [PULL 00/36] target-arm queue Peter Maydell

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