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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id bo20sm19594936edb.1.2020.12.15.14.58.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:50 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Subject: [PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar registers Date: Tue, 15 Dec 2020 23:57:42 +0100 Message-Id: <20201215225757.764263-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::642; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x642.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , kvm@vger.kernel.org, Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Commits 863f264d10f ("add msa_reset(), global msa register") and cb269f273fd ("fix multiple TCG registers covering same data") removed the FPU scalar registers and replaced them by aliases to the MSA vector registers. It is not very clear to have FPU registers displayed with MSA register names, even if MSA ASE is not present. Instead of aliasing FPU registers to the MSA ones (even when MSA is absent), we now alias the MSA ones to the FPU ones (only when MSA is present). Reviewed-by: Jiaxun Yang Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/mips/translate.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 02ea184f9a3..9b5b551b616 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31560,16 +31560,20 @@ void mips_tcg_init(void) offsetof(CPUMIPSState, active_tc.gpr[i]), regnames[i]); - for (i = 0; i < 32; i++) { int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); - msa_wr_d[i * 2] = - tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]); + + fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]); + } + /* MSA */ + for (i = 0; i < 32; i++) { + int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); + /* - * The scalar floating-point unit (FPU) registers are mapped on - * the MSA vector registers. + * The MSA vector registers are mapped on the + * scalar floating-point unit (FPU) registers. */ - fpu_f64[i] = msa_wr_d[i * 2]; + msa_wr_d[i * 2] = fpu_f64[i]; off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] = tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]); -- 2.26.2