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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id g18sm19135013edt.2.2020.12.15.14.58.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Dec 2020 14:58:16 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Subject: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper Date: Tue, 15 Dec 2020 23:57:36 +0100 Message-Id: <20201215225757.764263-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201215225757.764263-1-f4bug@amsat.org> References: <20201215225757.764263-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::543; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x543.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , kvm@vger.kernel.org, Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Introduce the isa_rel6_available() helper to check if the CPU supports the Release 6 ISA. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 1 + target/mips/cpu.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3ac21d0e9c0..c6a556efad5 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1289,6 +1289,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); bool cpu_type_supports_cps_smp(const char *cpu_type); bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); +bool isa_rel6_available(const CPUMIPSState *env); /* Check presence of multi-threading ASE implementation */ static inline bool ase_mt_available(CPUMIPSState *env) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4191c0741f4..9f082518076 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -789,6 +789,14 @@ bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) return (env->cpu_model->insn_flags & isa_mask) != 0; } +bool isa_rel6_available(const CPUMIPSState *env) +{ + if (TARGET_LONG_BITS == 64) { + return cpu_supports_isa(env, ISA_MIPS64R6); + } + return cpu_supports_isa(env, ISA_MIPS32R6); +} + bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) { const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); -- 2.26.2