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Wed, 16 Dec 2020 09:11:14 +0000 (GMT) Received: from pub.ltc.br.ibm.com (unknown [9.85.141.22]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Wed, 16 Dec 2020 09:11:13 +0000 (GMT) From: Gustavo Romero To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 6/7] target/ppc: Add support for prefixed load/store FP instructions Date: Wed, 16 Dec 2020 06:08:03 -0300 Message-Id: <20201216090804.58640-7-gromero@linux.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201216090804.58640-1-gromero@linux.ibm.com> References: <20201216090804.58640-1-gromero@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.343, 18.0.737 definitions=2020-12-16_02:2020-12-15, 2020-12-16 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 adultscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2012160055 Received-SPF: pass client-ip=148.163.156.1; envelope-from=gromero@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, gromero@linux.ibm.com, gustavo.romero@protonmail.com, Michael Roth , mroth@lamentation.net, clg@kaod.org, david@gibson.dropbear.id.au, alex.bennee@linaro.org, rth@twiddle.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Michael Roth This commit adds support for the following load/store instructions for FP registers: plf, plfd pstfs, pstfd Signed-off-by: Michael Roth Signed-off-by: Gustavo Romero --- target/ppc/translate/fp-impl.c.inc | 48 ++++++++++++++++++++++++++++++ target/ppc/translate/fp-ops.c.inc | 6 ++++ 2 files changed, 54 insertions(+) diff --git a/target/ppc/translate/fp-impl.c.inc b/target/ppc/translate/fp-impl.c.inc index 9f7868ee28..1eec98de0f 100644 --- a/target/ppc/translate/fp-impl.c.inc +++ b/target/ppc/translate/fp-impl.c.inc @@ -874,6 +874,28 @@ static void glue(gen_, name)(DisasContext *ctx) \ tcg_temp_free_i64(t0); \ } +#define GEN_PLDF(name, ldop, opc, type) \ +static void glue(gen_, p##name)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_FLOAT); \ + EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ + if (gen_addr_imm34_index(ctx, EA)) { \ + goto out; \ + } \ + gen_qemu_##ldop(ctx, t0, EA); \ + set_fpr(rD(ctx->opcode), t0); \ +out: \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + #define GEN_LDUF(name, ldop, opc, type) \ static void glue(gen_, name##u)(DisasContext *ctx) \ { \ @@ -943,6 +965,7 @@ static void glue(gen_, name##x)(DisasContext *ctx) \ #define GEN_LDFS(name, ldop, op, type) \ GEN_LDF(name, ldop, op | 0x20, type); \ +GEN_PLDF(name, ldop, op | 0x20, type); \ GEN_LDUF(name, ldop, op | 0x21, type); \ GEN_LDUXF(name, ldop, op | 0x01, type); \ GEN_LDXF(name, ldop, 0x17, op | 0x00, type) @@ -1109,6 +1132,28 @@ static void glue(gen_, name)(DisasContext *ctx) \ tcg_temp_free_i64(t0); \ } +#define GEN_PSTF(name, stop, opc, type) \ +static void glue(gen_, p##name)(DisasContext *ctx) \ +{ \ + TCGv EA; \ + TCGv_i64 t0; \ + if (unlikely(!ctx->fpu_enabled)) { \ + gen_exception(ctx, POWERPC_EXCP_FPU); \ + return; \ + } \ + gen_set_access_type(ctx, ACCESS_FLOAT); \ + EA = tcg_temp_new(); \ + t0 = tcg_temp_new_i64(); \ + if (gen_addr_imm34_index(ctx, EA)) { \ + goto out; \ + } \ + get_fpr(t0, rS(ctx->opcode)); \ + gen_qemu_##stop(ctx, t0, EA); \ +out: \ + tcg_temp_free(EA); \ + tcg_temp_free_i64(t0); \ +} + #define GEN_STUF(name, stop, opc, type) \ static void glue(gen_, name##u)(DisasContext *ctx) \ { \ @@ -1178,6 +1223,7 @@ static void glue(gen_, name##x)(DisasContext *ctx) \ #define GEN_STFS(name, stop, op, type) \ GEN_STF(name, stop, op | 0x20, type); \ +GEN_PSTF(name, stop, op | 0x20, type); \ GEN_STUF(name, stop, op | 0x21, type); \ GEN_STUXF(name, stop, op | 0x01, type); \ GEN_STXF(name, stop, 0x17, op | 0x00, type) @@ -1483,12 +1529,14 @@ static void gen_stfqx(DisasContext *ctx) #undef GEN_FLOAT_BS #undef GEN_LDF +#undef GEN_PLDF #undef GEN_LDUF #undef GEN_LDUXF #undef GEN_LDXF #undef GEN_LDFS #undef GEN_STF +#undef GEN_PSTF #undef GEN_STUF #undef GEN_STUXF #undef GEN_STXF diff --git a/target/ppc/translate/fp-ops.c.inc b/target/ppc/translate/fp-ops.c.inc index 88fab65628..fed0db8f65 100644 --- a/target/ppc/translate/fp-ops.c.inc +++ b/target/ppc/translate/fp-ops.c.inc @@ -52,6 +52,8 @@ GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT), #define GEN_LDF(name, ldop, opc, type) \ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), +#define GEN_PLDF(name, ldop, opc, type) \ +GEN_HANDLER_E_PREFIXED_M(p##name, opc, 0xFF, 0xFF, 0x0, PPC_64B, PPC2_ISA310), #define GEN_LDUF(name, ldop, opc, type) \ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), #define GEN_LDUXF(name, ldop, opc, type) \ @@ -60,6 +62,7 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_LDFS(name, ldop, op, type) \ GEN_LDF(name, ldop, op | 0x20, type) \ +GEN_PLDF(name, ldop, op | 0x20, type) \ GEN_LDUF(name, ldop, op | 0x21, type) \ GEN_LDUXF(name, ldop, op | 0x01, type) \ GEN_LDXF(name, ldop, 0x17, op | 0x00, type) @@ -73,6 +76,8 @@ GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205), #define GEN_STF(name, stop, opc, type) \ GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), +#define GEN_PSTF(name, ldop, opc, type) \ +GEN_HANDLER_E_PREFIXED_M(p##name, opc, 0xFF, 0xFF, 0x0, PPC_64B, PPC2_ISA310), #define GEN_STUF(name, stop, opc, type) \ GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), #define GEN_STUXF(name, stop, opc, type) \ @@ -81,6 +86,7 @@ GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type), GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type), #define GEN_STFS(name, stop, op, type) \ GEN_STF(name, stop, op | 0x20, type) \ +GEN_PSTF(name, stop, op | 0x20, type) \ GEN_STUF(name, stop, op | 0x21, type) \ GEN_STUXF(name, stop, op | 0x01, type) \ GEN_STXF(name, stop, 0x17, op | 0x00, type) -- 2.17.1