From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Paul Burton" <paulburton@kernel.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Laurent Vivier" <laurent@vivier.eu>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 09/11] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3
Date: Wed, 16 Dec 2020 14:43:26 +0100 [thread overview]
Message-ID: <20201216134328.851840-10-f4bug@amsat.org> (raw)
In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org>
The MIPS ISA release 3 is common to 32/64-bit CPUs.
To avoid holes in the insn_flags type, update the
definition with the next available bit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 9ef3f517aaa..171d94c16dc 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -24,7 +24,7 @@
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS_R1 0x0000000000000020ULL
#define ISA_MIPS_R2 0x0000000000000040ULL
-#define ISA_MIPS32R3 0x0000000000000200ULL
+#define ISA_MIPS_R3 0x0000000000000080ULL
#define ISA_MIPS32R5 0x0000000000000800ULL
#define ISA_MIPS32R6 0x0000000000002000ULL
#define ISA_NANOMIPS32 0x0000000000008000ULL
@@ -80,7 +80,7 @@
#define CPU_MIPS64R2 (CPU_MIPS64 | ISA_MIPS_R2)
/* MIPS Technologies "Release 3" */
-#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3)
#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3)
/* MIPS Technologies "Release 5" */
--
2.26.2
next prev parent reply other threads:[~2020-12-16 13:55 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-16 13:43 [PATCH 00/11] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 01/11] target/mips/mips-defs: Reorder CPU_MIPS5 definition Philippe Mathieu-Daudé
2020-12-16 14:56 ` Jiaxun Yang
2020-12-16 13:43 ` [PATCH 02/11] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64 Philippe Mathieu-Daudé
2020-12-16 14:59 ` Jiaxun Yang
2020-12-16 15:06 ` Jiaxun Yang
2020-12-16 16:08 ` Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 03/11] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Philippe Mathieu-Daudé
2020-12-16 15:16 ` Jiaxun Yang
2020-12-16 16:34 ` Philippe Mathieu-Daudé
2020-12-16 23:56 ` Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 04/11] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 05/11] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 06/11] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 07/11] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 08/11] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Philippe Mathieu-Daudé
2020-12-16 13:43 ` Philippe Mathieu-Daudé [this message]
2020-12-16 13:43 ` [PATCH 10/11] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 11/11] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Philippe Mathieu-Daudé
2020-12-16 14:54 ` [PATCH 00/11] target/mips/mips-defs: Simplify ISA definitions Jiaxun Yang
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