From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Paul Burton" <paulburton@kernel.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Laurent Vivier" <laurent@vivier.eu>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH 02/11] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64
Date: Wed, 16 Dec 2020 14:43:19 +0100 [thread overview]
Message-ID: <20201216134328.851840-3-f4bug@amsat.org> (raw)
In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org>
MIPS 64-bit ISA is introduced with MIPS3.
No need for another bit/definition to check for 64-bit.
Simplify CPU_MIPS64 definition as CPU_MIPS5 contains
CPU_MIPS4 which contains CPU_MIPS3 which contains ISA_MIPS3.
Suggested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/mips-defs.h | 5 ++---
hw/mips/boston.c | 2 +-
target/mips/translate.c | 10 +++++-----
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index f4d76e562d1..2756e72a9d6 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -19,12 +19,11 @@
*/
#define ISA_MIPS1 0x0000000000000001ULL
#define ISA_MIPS2 0x0000000000000002ULL
-#define ISA_MIPS3 0x0000000000000004ULL
+#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */
#define ISA_MIPS4 0x0000000000000008ULL
#define ISA_MIPS5 0x0000000000000010ULL
#define ISA_MIPS32 0x0000000000000020ULL
#define ISA_MIPS32R2 0x0000000000000040ULL
-#define ISA_MIPS64 0x0000000000000080ULL
#define ISA_MIPS64R2 0x0000000000000100ULL
#define ISA_MIPS32R3 0x0000000000000200ULL
#define ISA_MIPS64R3 0x0000000000000400ULL
@@ -78,7 +77,7 @@
/* MIPS Technologies "Release 1" */
#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
-#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
+#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32)
/* MIPS Technologies "Release 2" */
#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index c3b94c68e1b..f44f681fab5 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -463,7 +463,7 @@ static void boston_mach_init(MachineState *machine)
exit(1);
}
- is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64);
+ is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS3);
object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS);
object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type,
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 15265485f76..8c0ecfa17e1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -8538,7 +8538,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS3);
}
switch (reg) {
@@ -9264,7 +9264,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
const char *register_name = "invalid";
if (sel != 0) {
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS3);
}
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
@@ -14502,12 +14502,12 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx)
break;
#if defined(TARGET_MIPS64)
case RR_RY_CNVT_ZEW:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
case RR_RY_CNVT_SEW:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]);
break;
@@ -27203,7 +27203,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
#if defined(TARGET_MIPS64)
case OPC_DCLO:
case OPC_DCLZ:
- check_insn(ctx, ISA_MIPS64);
+ check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_cl(ctx, op1, rd, rs);
break;
--
2.26.2
next prev parent reply other threads:[~2020-12-16 13:51 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-16 13:43 [PATCH 00/11] target/mips/mips-defs: Simplify ISA definitions Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 01/11] target/mips/mips-defs: Reorder CPU_MIPS5 definition Philippe Mathieu-Daudé
2020-12-16 14:56 ` Jiaxun Yang
2020-12-16 13:43 ` Philippe Mathieu-Daudé [this message]
2020-12-16 14:59 ` [PATCH 02/11] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64 Jiaxun Yang
2020-12-16 15:06 ` Jiaxun Yang
2020-12-16 16:08 ` Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 03/11] target/mips/mips-defs: Use ISA_MIPS32R2 definition to check Release 2 Philippe Mathieu-Daudé
2020-12-16 15:16 ` Jiaxun Yang
2020-12-16 16:34 ` Philippe Mathieu-Daudé
2020-12-16 23:56 ` Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 04/11] target/mips/mips-defs: Use ISA_MIPS32R3 definition to check Release 3 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 05/11] target/mips/mips-defs: Use ISA_MIPS32R5 definition to check Release 5 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 06/11] target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 07/11] target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 08/11] target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 09/11] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 10/11] target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 Philippe Mathieu-Daudé
2020-12-16 13:43 ` [PATCH 11/11] target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 Philippe Mathieu-Daudé
2020-12-16 14:54 ` [PATCH 00/11] target/mips/mips-defs: Simplify ISA definitions Jiaxun Yang
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