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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id o13sm2685057wmc.44.2020.12.16.05.43.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Dec 2020 05:43:40 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 02/11] target/mips/mips-defs: Use ISA_MIPS3 for ISA_MIPS64 Date: Wed, 16 Dec 2020 14:43:19 +0100 Message-Id: <20201216134328.851840-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201216134328.851840-1-f4bug@amsat.org> References: <20201216134328.851840-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x431.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Paul Burton , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" MIPS 64-bit ISA is introduced with MIPS3. No need for another bit/definition to check for 64-bit. Simplify CPU_MIPS64 definition as CPU_MIPS5 contains CPU_MIPS4 which contains CPU_MIPS3 which contains ISA_MIPS3. Suggested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daudé --- target/mips/mips-defs.h | 5 ++--- hw/mips/boston.c | 2 +- target/mips/translate.c | 10 +++++----- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index f4d76e562d1..2756e72a9d6 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -19,12 +19,11 @@ */ #define ISA_MIPS1 0x0000000000000001ULL #define ISA_MIPS2 0x0000000000000002ULL -#define ISA_MIPS3 0x0000000000000004ULL +#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL #define ISA_MIPS32R2 0x0000000000000040ULL -#define ISA_MIPS64 0x0000000000000080ULL #define ISA_MIPS64R2 0x0000000000000100ULL #define ISA_MIPS32R3 0x0000000000000200ULL #define ISA_MIPS64R3 0x0000000000000400ULL @@ -78,7 +77,7 @@ /* MIPS Technologies "Release 1" */ #define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) -#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) +#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32) /* MIPS Technologies "Release 2" */ #define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index c3b94c68e1b..f44f681fab5 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -463,7 +463,7 @@ static void boston_mach_init(MachineState *machine) exit(1); } - is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS64); + is_64b = cpu_type_supports_isa(machine->cpu_type, ISA_MIPS3); object_initialize_child(OBJECT(machine), "cps", &s->cps, TYPE_MIPS_CPS); object_property_set_str(OBJECT(&s->cps), "cpu-type", machine->cpu_type, diff --git a/target/mips/translate.c b/target/mips/translate.c index 15265485f76..8c0ecfa17e1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -8538,7 +8538,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) const char *register_name = "invalid"; if (sel != 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); } switch (reg) { @@ -9264,7 +9264,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) const char *register_name = "invalid"; if (sel != 0) { - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); } if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { @@ -14502,12 +14502,12 @@ static int decode_mips16_opc(CPUMIPSState *env, DisasContext *ctx) break; #if defined(TARGET_MIPS64) case RR_RY_CNVT_ZEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); tcg_gen_ext32u_tl(cpu_gpr[rx], cpu_gpr[rx]); break; case RR_RY_CNVT_SEW: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); tcg_gen_ext32s_tl(cpu_gpr[rx], cpu_gpr[rx]); break; @@ -27203,7 +27203,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) #if defined(TARGET_MIPS64) case OPC_DCLO: case OPC_DCLZ: - check_insn(ctx, ISA_MIPS64); + check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; -- 2.26.2