From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Joelle van Dyne <j@getutm.app>
Subject: [PATCH v5 23/43] tcg/aarch64: Support split-wx code generation
Date: Tue, 5 Jan 2021 07:19:30 -1000 [thread overview]
Message-ID: <20210105171950.415486-24-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210105171950.415486-1-richard.henderson@linaro.org>
Reviewed-by: Joelle van Dyne <j@getutm.app>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target.h | 2 +-
tcg/aarch64/tcg-target.c.inc | 57 ++++++++++++++++++++----------------
2 files changed, 33 insertions(+), 26 deletions(-)
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 23bf87db3d..079828ea71 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -155,6 +155,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
#define TCG_TARGET_NEED_LDST_LABELS
#endif
#define TCG_TARGET_NEED_POOL_LABELS
-#define TCG_TARGET_SUPPORT_MIRROR 0
+#define TCG_TARGET_SUPPORT_MIRROR 1
#endif /* AARCH64_TCG_TARGET_H */
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index bd888bc66d..2e33162c03 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -78,38 +78,42 @@ static const int tcg_target_call_oarg_regs[1] = {
#define TCG_REG_GUEST_BASE TCG_REG_X28
#endif
-static inline bool reloc_pc26(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+static bool reloc_pc26(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
{
- ptrdiff_t offset = target - code_ptr;
+ const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+ ptrdiff_t offset = target - src_rx;
+
if (offset == sextract64(offset, 0, 26)) {
/* read instruction, mask away previous PC_REL26 parameter contents,
set the proper offset, then write back the instruction. */
- *code_ptr = deposit32(*code_ptr, 0, 26, offset);
+ *src_rw = deposit32(*src_rw, 0, 26, offset);
return true;
}
return false;
}
-static inline bool reloc_pc19(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+static bool reloc_pc19(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
{
- ptrdiff_t offset = target - code_ptr;
+ const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
+ ptrdiff_t offset = target - src_rx;
+
if (offset == sextract64(offset, 0, 19)) {
- *code_ptr = deposit32(*code_ptr, 5, 19, offset);
+ *src_rw = deposit32(*src_rw, 5, 19, offset);
return true;
}
return false;
}
-static inline bool patch_reloc(tcg_insn_unit *code_ptr, int type,
- intptr_t value, intptr_t addend)
+static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
+ intptr_t value, intptr_t addend)
{
tcg_debug_assert(addend == 0);
switch (type) {
case R_AARCH64_JUMP26:
case R_AARCH64_CALL26:
- return reloc_pc26(code_ptr, (tcg_insn_unit *)value);
+ return reloc_pc26(code_ptr, (const tcg_insn_unit *)value);
case R_AARCH64_CONDBR19:
- return reloc_pc19(code_ptr, (tcg_insn_unit *)value);
+ return reloc_pc19(code_ptr, (const tcg_insn_unit *)value);
default:
g_assert_not_reached();
}
@@ -1050,12 +1054,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
/* Look for host pointer values within 4G of the PC. This happens
often when loading pointers to QEMU's own data structures. */
if (type == TCG_TYPE_I64) {
- tcg_target_long disp = value - (intptr_t)s->code_ptr;
+ intptr_t src_rx = (intptr_t)tcg_splitwx_to_rx(s->code_ptr);
+ tcg_target_long disp = value - src_rx;
if (disp == sextract64(disp, 0, 21)) {
tcg_out_insn(s, 3406, ADR, rd, disp);
return;
}
- disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12);
+ disp = (value >> 12) - (src_rx >> 12);
if (disp == sextract64(disp, 0, 21)) {
tcg_out_insn(s, 3406, ADRP, rd, disp);
if (value & 0xfff) {
@@ -1308,14 +1313,14 @@ static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a,
static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
{
- ptrdiff_t offset = target - s->code_ptr;
+ ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2;
tcg_debug_assert(offset == sextract64(offset, 0, 26));
tcg_out_insn(s, 3206, B, offset);
}
-static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target)
+static void tcg_out_goto_long(TCGContext *s, const tcg_insn_unit *target)
{
- ptrdiff_t offset = target - s->code_ptr;
+ ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2;
if (offset == sextract64(offset, 0, 26)) {
tcg_out_insn(s, 3206, B, offset);
} else {
@@ -1329,9 +1334,9 @@ static inline void tcg_out_callr(TCGContext *s, TCGReg reg)
tcg_out_insn(s, 3207, BLR, reg);
}
-static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
+static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target)
{
- ptrdiff_t offset = target - s->code_ptr;
+ ptrdiff_t offset = tcg_pcrel_diff(s, target) >> 2;
if (offset == sextract64(offset, 0, 26)) {
tcg_out_insn(s, 3206, BL, offset);
} else {
@@ -1393,7 +1398,7 @@ static void tcg_out_brcond(TCGContext *s, TCGType ext, TCGCond c, TCGArg a,
tcg_out_reloc(s, s->code_ptr, R_AARCH64_CONDBR19, l, 0);
offset = tcg_in32(s) >> 5;
} else {
- offset = l->u.value_ptr - s->code_ptr;
+ offset = tcg_pcrel_diff(s, l->u.value_ptr) >> 2;
tcg_debug_assert(offset == sextract64(offset, 0, 19));
}
@@ -1568,7 +1573,7 @@ static void * const qemu_st_helpers[16] = {
[MO_BEQ] = helper_be_stq_mmu,
};
-static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)
+static inline void tcg_out_adr(TCGContext *s, TCGReg rd, const void *target)
{
ptrdiff_t offset = tcg_pcrel_diff(s, target);
tcg_debug_assert(offset == sextract64(offset, 0, 21));
@@ -1581,7 +1586,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
MemOp opc = get_memop(oi);
MemOp size = opc & MO_SIZE;
- if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
+ if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
return false;
}
@@ -1606,7 +1611,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
MemOp opc = get_memop(oi);
MemOp size = opc & MO_SIZE;
- if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
+ if (!reloc_pc19(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
return false;
}
@@ -1631,7 +1636,8 @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
label->type = ext;
label->datalo_reg = data_reg;
label->addrlo_reg = addr_reg;
- label->raddr = raddr;
+ /* TODO: Cast goes away when all hosts converted */
+ label->raddr = (void *)tcg_splitwx_to_rx(raddr);
label->label_ptr[0] = label_ptr;
}
@@ -1849,7 +1855,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
#endif /* CONFIG_SOFTMMU */
}
-static tcg_insn_unit *tb_ret_addr;
+static const tcg_insn_unit *tb_ret_addr;
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
@@ -2894,11 +2900,12 @@ static void tcg_target_qemu_prologue(TCGContext *s)
* Return path for goto_ptr. Set return value to 0, a-la exit_tb,
* and fall through to the rest of the epilogue.
*/
- tcg_code_gen_epilogue = s->code_ptr;
+ /* TODO: Cast goes away when all hosts converted */
+ tcg_code_gen_epilogue = (void *)tcg_splitwx_to_rx(s->code_ptr);
tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0);
/* TB epilogue */
- tb_ret_addr = s->code_ptr;
+ tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
/* Remove TCG locals stack space. */
tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
--
2.25.1
next prev parent reply other threads:[~2021-01-05 17:38 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-05 17:19 [PATCH v5 00/43] Mirror map JIT memory for TCG Richard Henderson
2021-01-05 17:19 ` [PATCH v5 01/43] tcg: Do not flush icache for interpreter Richard Henderson
2021-01-05 17:19 ` [PATCH v5 02/43] util: Extract flush_icache_range to cacheflush.c Richard Henderson
2021-01-05 17:19 ` [PATCH v5 03/43] util: Enhance flush_icache_range with separate data pointer Richard Henderson
2021-01-05 17:19 ` [PATCH v5 04/43] util: Specialize flush_idcache_range for aarch64 Richard Henderson
2021-01-05 17:19 ` [PATCH v5 05/43] tcg: Move tcg prologue pointer out of TCGContext Richard Henderson
2021-01-05 17:19 ` [PATCH v5 06/43] tcg: Move tcg epilogue " Richard Henderson
2021-01-05 17:19 ` [PATCH v5 07/43] tcg: Add in_code_gen_buffer Richard Henderson
2021-01-05 17:19 ` [PATCH v5 08/43] tcg: Introduce tcg_splitwx_to_{rx,rw} Richard Henderson
2021-01-05 17:19 ` [PATCH v5 09/43] tcg: Adjust TCGLabel for const Richard Henderson
2021-01-05 17:19 ` [PATCH v5 10/43] tcg: Adjust tcg_out_call " Richard Henderson
2021-01-05 17:19 ` [PATCH v5 11/43] tcg: Adjust tcg_out_label " Richard Henderson
2021-01-05 17:19 ` [PATCH v5 12/43] tcg: Adjust tcg_register_jit " Richard Henderson
2021-01-05 17:19 ` [PATCH v5 13/43] tcg: Adjust tb_target_set_jmp_target for split-wx Richard Henderson
2021-01-05 17:19 ` [PATCH v5 14/43] tcg: Make DisasContextBase.tb const Richard Henderson
2021-01-05 17:19 ` [PATCH v5 15/43] tcg: Make tb arg to synchronize_from_tb const Richard Henderson
2021-01-05 17:19 ` [PATCH v5 16/43] tcg: Use Error with alloc_code_gen_buffer Richard Henderson
2021-01-05 18:55 ` Philippe Mathieu-Daudé
2021-01-05 17:19 ` [PATCH v5 17/43] tcg: Add --accel tcg,split-wx property Richard Henderson
2021-01-05 20:30 ` Joelle van Dyne
2021-01-05 17:19 ` [PATCH v5 18/43] accel/tcg: Support split-wx for linux with memfd Richard Henderson
2021-01-05 17:19 ` [PATCH v5 19/43] accel/tcg: Support split-wx for darwin/iOS with vm_remap Richard Henderson
2021-01-05 17:19 ` [PATCH v5 20/43] tcg: Return the TB pointer from the rx region from exit_tb Richard Henderson
2021-01-05 17:19 ` [PATCH v5 21/43] tcg/i386: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 22/43] tcg/aarch64: Use B not BL for tcg_out_goto_long Richard Henderson
2021-01-05 17:19 ` Richard Henderson [this message]
2021-01-05 17:19 ` [PATCH v5 24/43] disas: Push const down through host disassembly Richard Henderson
2021-01-05 17:19 ` [PATCH v5 25/43] tcg/tci: Push const down through bytecode reading Richard Henderson
2021-01-05 18:51 ` Philippe Mathieu-Daudé
2021-01-05 17:19 ` [PATCH v5 26/43] tcg: Introduce tcg_tbrel_diff Richard Henderson
2021-01-05 17:19 ` [PATCH v5 27/43] tcg/ppc: Use tcg_tbrel_diff Richard Henderson
2021-01-05 17:19 ` [PATCH v5 28/43] tcg/ppc: Use tcg_out_mem_long to reset TCG_REG_TB Richard Henderson
2021-01-05 17:19 ` [PATCH v5 29/43] tcg/ppc: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 30/43] tcg/sparc: Use tcg_tbrel_diff Richard Henderson
2021-01-05 17:19 ` [PATCH v5 31/43] tcg/sparc: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 32/43] tcg/s390: Use tcg_tbrel_diff Richard Henderson
2021-01-05 17:19 ` [PATCH v5 33/43] tcg/s390: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 34/43] tcg/riscv: Fix branch range checks Richard Henderson
2021-01-05 17:19 ` [PATCH v5 35/43] tcg/riscv: Remove branch-over-branch fallback Richard Henderson
2021-01-05 17:19 ` [PATCH v5 36/43] tcg/riscv: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 37/43] accel/tcg: Add mips support to alloc_code_gen_buffer_splitwx_memfd Richard Henderson
2021-01-05 17:19 ` [PATCH v5 38/43] tcg/mips: Do not assert on relocation overflow Richard Henderson
2021-01-05 17:19 ` [PATCH v5 39/43] tcg/mips: Support split-wx code generation Richard Henderson
2021-01-05 17:19 ` [PATCH v5 40/43] tcg/arm: " Richard Henderson
2021-01-05 17:19 ` [PATCH v5 41/43] tcg: Remove TCG_TARGET_SUPPORT_MIRROR Richard Henderson
2021-01-05 17:19 ` [PATCH v5 42/43] tcg: Constify tcg_code_gen_epilogue Richard Henderson
2021-01-05 18:47 ` Philippe Mathieu-Daudé
2021-01-05 17:19 ` [PATCH v5 43/43] tcg: Constify TCGLabelQemuLdst.raddr Richard Henderson
2021-01-05 18:47 ` Philippe Mathieu-Daudé
2021-01-05 18:12 ` [PATCH v5 00/43] Mirror map JIT memory for TCG no-reply
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