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From: Bin Meng <bmeng.cn@gmail.com>
To: "Peter Maydell" <peter.maydell@linaro.org>,
	"Jean-Christophe Dubois" <jcd@tribudubois.net>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH v2 0/4] hw/ssi: imx_spi: Fix various bugs in the imx_spi model
Date: Wed,  6 Jan 2021 13:55:18 +0800	[thread overview]
Message-ID: <20210106055522.2031-1-bmeng.cn@gmail.com> (raw)

From: Bin Meng <bin.meng@windriver.com>

This series fixes a bunch of bugs in current implementation of the imx
spi controller, including the following issues:

- chip select signal was not lower down when spi controller is reset
- transfer incorrect data when the burst length is larger than 32 bit
- spi controller tx and rx fifo endianness is incorrect

Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7
(interrupt mode).

Changes in v2:
- Fix the "Fixes" tag in the commit message
- Use ternary operator as Philippe suggested

Bin Meng (3):
  hw/ssi: imx_spi: Use a macro for number of chip selects supported
  hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic
  hw/ssi: imx_spi: Correct tx and rx fifo endianness

Xuzhou Cheng (1):
  hw/ssi: imx_spi: Disable chip selects in imx_spi_reset()

 include/hw/ssi/imx_spi.h |  5 ++++-
 hw/ssi/imx_spi.c         | 27 ++++++++++++++++++++-------
 2 files changed, 24 insertions(+), 8 deletions(-)

-- 
2.25.1



             reply	other threads:[~2021-01-06  5:56 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-06  5:55 Bin Meng [this message]
2021-01-06  5:55 ` [PATCH v2 1/4] hw/ssi: imx_spi: Use a macro for number of chip selects supported Bin Meng
2021-01-06  5:55 ` [PATCH v2 2/4] hw/ssi: imx_spi: Disable chip selects in imx_spi_reset() Bin Meng
2021-01-06  5:55 ` [PATCH v2 3/4] hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic Bin Meng
2021-01-06  5:55 ` [PATCH v2 4/4] hw/ssi: imx_spi: Correct tx and rx fifo endianness Bin Meng

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