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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id c62sm1070503pfa.116.2021.01.05.21.55.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Jan 2021 21:55:33 -0800 (PST) From: Bin Meng To: Peter Maydell , Jean-Christophe Dubois , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 0/4] hw/ssi: imx_spi: Fix various bugs in the imx_spi model Date: Wed, 6 Jan 2021 13:55:18 +0800 Message-Id: <20210106055522.2031-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This series fixes a bunch of bugs in current implementation of the imx spi controller, including the following issues: - chip select signal was not lower down when spi controller is reset - transfer incorrect data when the burst length is larger than 32 bit - spi controller tx and rx fifo endianness is incorrect Tested with upstream U-Boot v2020.10 (polling mode) and VxWorks 7 (interrupt mode). Changes in v2: - Fix the "Fixes" tag in the commit message - Use ternary operator as Philippe suggested Bin Meng (3): hw/ssi: imx_spi: Use a macro for number of chip selects supported hw/ssi: imx_spi: Correct the burst length > 32 bit transfer logic hw/ssi: imx_spi: Correct tx and rx fifo endianness Xuzhou Cheng (1): hw/ssi: imx_spi: Disable chip selects in imx_spi_reset() include/hw/ssi/imx_spi.h | 5 ++++- hw/ssi/imx_spi.c | 27 ++++++++++++++++++++------- 2 files changed, 24 insertions(+), 8 deletions(-) -- 2.25.1